CN204316440U - The two power amplification formula logic system of a kind of new type of safe formula - Google Patents
The two power amplification formula logic system of a kind of new type of safe formula Download PDFInfo
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- CN204316440U CN204316440U CN201420726874.0U CN201420726874U CN204316440U CN 204316440 U CN204316440 U CN 204316440U CN 201420726874 U CN201420726874 U CN 201420726874U CN 204316440 U CN204316440 U CN 204316440U
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Abstract
The utility model discloses the two power amplification formula logic system of a kind of new type of safe formula, primarily of logical power amplifying circuit, the switch power amplifying circuit be connected with this logical power amplifying circuit, and the logic switching circuit be serially connected between logical power amplifying circuit and switch power amplifying circuit forms; Described switch power amplifying circuit is by power amplifier P2, and power amplifier P3, is serially connected in the composition such as resistance R1 and electric capacity C1 between the output of power amplifier P2 and negative input.Meanwhile, virtual protection amplifying circuit is also provided with in switch power amplifying circuit inside.Overall structure of the present utility model is comparatively simple, is convenient to make and apply.Meanwhile, the utility model can effectively reduce the attenuation amplitude of amplifying signal, thus guarantees the performance of amplifying signal.
Description
Technical field
The utility model relates to a kind of amplifying circuit, specifically refers to the two power amplification formula logic system of a kind of new type of safe formula.
Background technology
At present, widely, relevant voltage signal, current signal and other pulse signals are mainly carried out power amplification by according to demand in the utilization of power amplification circuit.But, traditional power amplification circuit is after carrying out power drive amplification, and not only the attenuation amplitude of its amplifying signal is comparatively large, but also can be subject to outside electromagnetic interference, and then make amplifying signal performance comparatively unstable, serious constrains using and promoting of its profound level.
Utility model content
The purpose of this utility model is to overcome the defect of the comparatively large and amplified signal unstable properties of signal attenuation amplitude after the amplification that current power amplification circuit exists, provides a kind of new type of safe formula two power amplification formula logic system.
The purpose of this utility model is achieved through the following technical solutions: the two power amplification formula logic system of a kind of new type of safe formula, primarily of logical power amplifying circuit, the switch power amplifying circuit be connected with this logical power amplifying circuit, and the logic switching circuit be serially connected between logical power amplifying circuit and switch power amplifying circuit forms, described switch power amplifying circuit is by power amplifier P2, power amplifier P3, be serially connected in the resistance R1 between the output of power amplifier P2 and negative input and electric capacity C1, base stage is connected with the output of power amplifier P2, the triode Q1 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R3, base stage is connected with the emitter of triode Q1, the triode Q2 that collector electrode is connected with the negative input of power amplifier P3 after resistance R4, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q2 and the electric capacity C3 of ground connection, and N pole is connected with the collector electrode of triode Q1, the diode D1 of the extremely external-4V voltage of P forms, the electrode input end of described power amplifier P2 is connected with logical power amplifying circuit, and the base stage of triode Q2 is connected with logic switching circuit, and the output of power amplifier P3 then forms total output.Meanwhile, between the negative input and the base stage of triode Q2 of power amplifier P2, virtual protection amplifying circuit is also serially connected with, this virtual protection amplifying circuit is primarily of power amplifier P4, power amplifier P5, NAND gate IC5, NAND gate IC6, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C6 that positive pole is connected with the negative input of NAND gate IC6 after resistance R17, one end is connected with the negative input of NAND gate IC5, the resistance R14 that the other end is connected with the electrode input end of power amplifier P4, be serially connected in the resistance R15 between the negative input of power amplifier P4 and output, one end is connected with the output of NAND gate IC5, the resistance R16 that the other end is connected with the negative input of power amplifier P5, be serially connected in the polar capacitor C8 between the electrode input end of power amplifier P5 and output, positive pole is connected with the output of NAND gate IC6, negative pole is in turn through electric capacity C7 that voltage stabilizing didoe D3 is connected with the output of power amplifier P4 after resistance R18, P pole is connected with the output of power amplifier P5, N pole is in turn through diode D4 that resistance R20 is connected with the tie point of resistance R18 with voltage stabilizing didoe D3 after resistance R19, and N pole is connected with the negative pole of electric capacity C7, the voltage stabilizing didoe D5 that P pole is connected with the tie point of resistance R20 with diode D4 forms.
The electrode input end of described NAND gate IC5 is connected with the negative input of power amplifier P4; The electrode input end of the output NAND gate IC6 of power amplifier P5 is connected, and its electrode input end is then connected with the output of power amplifier P4; The positive pole of described polar capacitor C6 is connected with the negative input of power amplifier P2, and resistance R20 is then connected with the base stage of triode Q2 with the tie point of resistance R19.
Further, described logical power amplifying circuit is by power amplifier P1, NAND gate IC1, NAND gate IC2, N pole is connected with the output of power amplifier P1, the diode D2 that P pole is connected with the negative input of NAND gate IC1 after resistance R12, one end is connected with the electrode input end of NAND gate IC1, the resistance R13 that the other end is connected with the output of NAND gate IC2 after electric capacity C2, one end is connected with the output of NAND gate IC1, the resistance R10 that the other end is connected with the tie point of electric capacity C2 with resistance R13, and one end is connected with the negative input of power amplifier P1, the resistance R11 of other end ground connection forms, the output of described power amplifier P1 is connected with switch power amplifying circuit, the output of NAND gate IC2 is then connected with logic switching circuit, simultaneously, the output of NAND gate IC1 is also connected with the electrode input end of NAND gate IC2, and the negative input of NAND gate IC2 forms total input together with the electrode input end of power amplifier P1.
Described logic switching circuit is by NAND gate IC3, NAND gate IC4, triode Q3, one end is connected with the output of NAND gate IC3, the resistance R2 that the other end is connected with the collector electrode of triode Q3 after resistance R5, one end is connected with the output of NAND gate IC4, the resistance R9 that the other end is connected with the base stage of triode Q3 after resistance R6, the electric capacity C5 be in parallel with resistance R6, one end is connected with the base stage of triode Q3, the resistance R7 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q3, the resistance R8 of the external-4V voltage of the other end, and form with the electric capacity C4 that resistance R8 is in parallel, the output of described NAND gate IC2 is then connected with the negative input of NAND gate IC4 with the electrode input end of NAND gate IC3 respectively, and the negative input of NAND gate IC3 is connected with the electrode input end of NAND gate IC4, the base stage of described triode Q2 is then connected with the tie point of resistance R5 with resistance R2.
For guaranteeing result of use, described electric capacity C1 and electric capacity C2 is patch capacitor, and electric capacity C3, electric capacity C4 and electric capacity C5 are then electrochemical capacitor.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) overall structure of the present utility model is comparatively simple, is convenient to make and apply.
(2) the utility model can effectively reduce the attenuation amplitude of amplifying signal, thus guarantees the performance of amplifying signal.
(3) the utility model can effectively reduce the interference of external electromagnetic environment, thus avoids amplifying signal to mix remaining electromagnetic wave, ensures the purity of amplifying signal.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Fig. 2 is virtual protection amplification circuit structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1; power amplification formula logical circuit described in the utility model is primarily of logical power amplifying circuit; the switch power amplifying circuit be connected with this logical power amplifying circuit; be serially connected in the logic switching circuit between logical power amplifying circuit and switch power amplifying circuit, and be arranged on the virtual protection amplifying circuit composition of switch power amplifying circuit inside.
Wherein, described logical power amplifying circuit is by power amplifier P1, NAND gate IC1, NAND gate IC2, N pole is connected with the output of power amplifier P1, the diode D2 that P pole is connected with the negative input of NAND gate IC1 after resistance R12, one end is connected with the electrode input end of NAND gate IC1, the resistance R13 that the other end is connected with the output of NAND gate IC2 after electric capacity C2, one end is connected with the output of NAND gate IC1, the resistance R10 that the other end is connected with the tie point of electric capacity C2 with resistance R13, and one end is connected with the negative input of power amplifier P1, the resistance R11 of other end ground connection forms, the output of described power amplifier P1 is connected with switch power amplifying circuit, the output of NAND gate IC2 is then connected with logic switching circuit, simultaneously, the output of NAND gate IC1 is also connected with the electrode input end of NAND gate IC2, and the negative input of NAND gate IC2 forms total input together with the electrode input end of power amplifier P1.
Described switch power amplifying circuit is by power amplifier P2, power amplifier P3, be serially connected in the resistance R1 between the output of power amplifier P2 and negative input and electric capacity C1, base stage is connected with the output of power amplifier P2, the triode Q1 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R3, base stage is connected with the emitter of triode Q1, the triode Q2 that collector electrode is connected with the negative input of power amplifier P3 after resistance R4, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q2 and the electric capacity C3 of ground connection, and N pole is connected with the collector electrode of triode Q1, the diode D1 of the extremely external-4V voltage of P forms, the electrode input end of described power amplifier P2 is connected with the output of power amplifier P1, and the base stage of triode Q2 is also connected with logic switching circuit, and the output of power amplifier P3 then forms total output.
The structure of described virtual protection amplifying circuit as shown in Figure 2, it is primarily of power amplifier P4, power amplifier P5, NAND gate IC5, NAND gate IC6, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C6 that positive pole is connected with the negative input of NAND gate IC6 after resistance R17, one end is connected with the negative input of NAND gate IC5, the resistance R14 that the other end is connected with the electrode input end of power amplifier P4, be serially connected in the resistance R15 between the negative input of power amplifier P4 and output, one end is connected with the output of NAND gate IC5, the resistance R16 that the other end is connected with the negative input of power amplifier P5, be serially connected in the polar capacitor C8 between the electrode input end of power amplifier P5 and output, positive pole is connected with the output of NAND gate IC6, negative pole is in turn through electric capacity C7 that voltage stabilizing didoe D3 is connected with the output of power amplifier P4 after resistance R18, P pole is connected with the output of power amplifier P5, N pole is in turn through diode D4 that resistance R20 is connected with the tie point of resistance R18 with voltage stabilizing didoe D3 after resistance R19, and N pole is connected with the negative pole of electric capacity C7, the voltage stabilizing didoe D5 that P pole is connected with the tie point of resistance R20 with diode D4 forms.
Meanwhile, the electrode input end of described NAND gate IC5 is connected with the negative input of power amplifier P4; The electrode input end of the output NAND gate IC6 of power amplifier P5 is connected, and its electrode input end is then connected with the output of power amplifier P4; The positive pole of described polar capacitor C6 is connected with the negative input of power amplifier P2, and resistance R20 is then connected with the base stage of triode Q2 with the tie point of resistance R19.
Described logic switching circuit is by NAND gate IC3, NAND gate IC4, triode Q3, one end is connected with the output of NAND gate IC3, the resistance R2 that the other end is connected with the collector electrode of triode Q3 after resistance R5, one end is connected with the output of NAND gate IC4, the resistance R9 that the other end is connected with the base stage of triode Q3 after resistance R6, the electric capacity C5 be in parallel with resistance R6, one end is connected with the base stage of triode Q3, the resistance R7 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q3, the resistance R8 of the external-4V voltage of the other end, and form with the electric capacity C4 that resistance R8 is in parallel, the output of described NAND gate IC2 is then connected with the negative input of NAND gate IC4 with the electrode input end of NAND gate IC3 respectively, and the negative input of NAND gate IC3 is connected with the electrode input end of NAND gate IC4, the base stage of described triode Q2 is then connected with the tie point of resistance R5 with resistance R2.
For guaranteeing result of use, electric capacity C1 described in the utility model and electric capacity C2 all preferentially adopts patch capacitor to realize, and electric capacity C3, electric capacity C4 and electric capacity C5 then all preferentially adopt electrochemical capacitor to realize.
As mentioned above, just the utility model can well be realized.
Claims (4)
1. the two power amplification formula logic system of new type of safe formula, primarily of logical power amplifying circuit, the switch power amplifying circuit be connected with this logical power amplifying circuit, and the logic switching circuit be serially connected between logical power amplifying circuit and switch power amplifying circuit forms, described switch power amplifying circuit is by power amplifier P2, power amplifier P3, be serially connected in the resistance R1 between the output of power amplifier P2 and negative input and electric capacity C1, base stage is connected with the output of power amplifier P2, the triode Q1 that collector electrode is connected with the electrode input end of power amplifier P3 after resistance R3, base stage is connected with the emitter of triode Q1, the triode Q2 that collector electrode is connected with the negative input of power amplifier P3 after resistance R4, positive pole is connected with the negative input of power amplifier P3, and negative pole is connected with the emitter of triode Q2 and the electric capacity C3 of ground connection, and N pole is connected with the collector electrode of triode Q1, the diode D1 of the extremely external-4V voltage of P forms, the electrode input end of described power amplifier P2 is connected with logical power amplifying circuit, the base stage of triode Q2 is connected with logic switching circuit, the output of power amplifier P3 then forms total output, it is characterized in that, between the negative input and the base stage of triode Q2 of power amplifier P2, be also serially connected with virtual protection amplifying circuit, this virtual protection amplifying circuit is primarily of power amplifier P4, power amplifier P5, NAND gate IC5, NAND gate IC6, negative pole is connected with the electrode input end of power amplifier P4, the polar capacitor C6 that positive pole is connected with the negative input of NAND gate IC6 after resistance R17, one end is connected with the negative input of NAND gate IC5, the resistance R14 that the other end is connected with the electrode input end of power amplifier P4, be serially connected in the resistance R15 between the negative input of power amplifier P4 and output, one end is connected with the output of NAND gate IC5, the resistance R16 that the other end is connected with the negative input of power amplifier P5, be serially connected in the polar capacitor C8 between the electrode input end of power amplifier P5 and output, positive pole is connected with the output of NAND gate IC6, negative pole is in turn through electric capacity C7 that voltage stabilizing didoe D3 is connected with the output of power amplifier P4 after resistance R18, P pole is connected with the output of power amplifier P5, N pole is in turn through diode D4 that resistance R20 is connected with the tie point of resistance R18 with voltage stabilizing didoe D3 after resistance R19, and N pole is connected with the negative pole of electric capacity C7, the voltage stabilizing didoe D5 that P pole is connected with the tie point of resistance R20 with diode D4 forms, the electrode input end of described NAND gate IC5 is connected with the negative input of power amplifier P4, the electrode input end of the output NAND gate IC6 of power amplifier P5 is connected, and its electrode input end is then connected with the output of power amplifier P4, the positive pole of described polar capacitor C6 is connected with the negative input of power amplifier P2, and resistance R20 is then connected with the base stage of triode Q2 with the tie point of resistance R19.
2. the two power amplification formula logic system of a kind of new type of safe formula according to claim 1, it is characterized in that, described logical power amplifying circuit is by power amplifier P1, NAND gate IC1, NAND gate IC2, N pole is connected with the output of power amplifier P1, the diode D2 that P pole is connected with the negative input of NAND gate IC1 after resistance R12, one end is connected with the electrode input end of NAND gate IC1, the resistance R13 that the other end is connected with the output of NAND gate IC2 after electric capacity C2, one end is connected with the output of NAND gate IC1, the resistance R10 that the other end is connected with the tie point of electric capacity C2 with resistance R13, and one end is connected with the negative input of power amplifier P1, the resistance R11 of other end ground connection forms, the output of described power amplifier P1 is connected with switch power amplifying circuit, the output of NAND gate IC2 is then connected with logic switching circuit, simultaneously, the output of NAND gate IC1 is also connected with the electrode input end of NAND gate IC2, and the negative input of NAND gate IC2 forms total input together with the electrode input end of power amplifier P1.
3. the two power amplification formula logic system of a kind of new type of safe formula according to claim 2, it is characterized in that, described logic switching circuit is by NAND gate IC3, NAND gate IC4, triode Q3, one end is connected with the output of NAND gate IC3, the resistance R2 that the other end is connected with the collector electrode of triode Q3 after resistance R5, one end is connected with the output of NAND gate IC4, the resistance R9 that the other end is connected with the base stage of triode Q3 after resistance R6, the electric capacity C5 be in parallel with resistance R6, one end is connected with the base stage of triode Q3, the resistance R7 of the external-4V voltage of the other end, one end is connected with the emitter of triode Q3, the resistance R8 of the external-4V voltage of the other end, and form with the electric capacity C4 that resistance R8 is in parallel, the output of described NAND gate IC2 is then connected with the negative input of NAND gate IC4 with the electrode input end of NAND gate IC3 respectively, and the negative input of NAND gate IC3 is connected with the electrode input end of NAND gate IC4, the base stage of described triode Q2 is then connected with the tie point of resistance R5 with resistance R2.
4. the two power amplification formula logic system of a kind of new type of safe formula according to claim 3, it is characterized in that, described electric capacity C1 and electric capacity C2 is patch capacitor, and electric capacity C3, electric capacity C4 and electric capacity C5 are then electrochemical capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420726874.0U CN204316440U (en) | 2014-11-27 | 2014-11-27 | The two power amplification formula logic system of a kind of new type of safe formula |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420726874.0U CN204316440U (en) | 2014-11-27 | 2014-11-27 | The two power amplification formula logic system of a kind of new type of safe formula |
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| Publication Number | Publication Date |
|---|---|
| CN204316440U true CN204316440U (en) | 2015-05-06 |
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| CN201420726874.0U Expired - Fee Related CN204316440U (en) | 2014-11-27 | 2014-11-27 | The two power amplification formula logic system of a kind of new type of safe formula |
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| CN (1) | CN204316440U (en) |
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- 2014-11-27 CN CN201420726874.0U patent/CN204316440U/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20151127 |