CN105161617B - A kind of resistance-variable storing device of planar structure and preparation method thereof - Google Patents
A kind of resistance-variable storing device of planar structure and preparation method thereof Download PDFInfo
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- CN105161617B CN105161617B CN201510608779.XA CN201510608779A CN105161617B CN 105161617 B CN105161617 B CN 105161617B CN 201510608779 A CN201510608779 A CN 201510608779A CN 105161617 B CN105161617 B CN 105161617B
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Abstract
The invention belongs to resistance-variable storing device technical field, specially a kind of resistance-variable storing device of planar structure and preparation method thereof.Resistance-variable storing device of the invention has the Graphene electrodes at the two ends for being formed at resistive functional layer, using the high mobility characteristic of grapheme material, realizes the low power operation of resistance-variable storing device.The resistance-variable storing device of planar structure is conducive to the observation of conductive filament shape, contributes to the study mechanism to resistance-variable storing device.The present invention obtains tens nanometers of space in graphene nanobelt using the method for electric Joule heat fusing near middle position, so as to form Graphene electrodes.Based on the characteristic of lateral growth of the resistive functional layer on Graphene in atom layer deposition process, resistive functional layer is formed.The method is simple, effective, save material cost, is capable of achieving the regulation to resistance-variable storing device device size.
Description
Technical field
The invention belongs to resistance-variable storing device technical field, and in particular to a kind of resistance-variable storing device of planar structure and its preparation
Method.
Background technology
With the further scaled down of feature sizes of semiconductor devices, traditional flash memory technology is up to the pole of size
Limit.Further to improve the performance of device, technical staff starts to carry out positive exploration to new construction, new material, new technology.Closely
Nian Lai, various new non-volatility memorizers are developed rapidly.Wherein, resistance-variable storing device（RRAM）By the letter of its structure
Single, micro ability is strong, high density, data hold time are long, can three-dimensionally integrated and and complementary metal oxide semiconductors (CMOS)
（CMOS）The advantages such as process compatible, are more and more paid close attention to by industry, it is considered to be very likely substitute static random-access
Memory（SRAM）, dynamic random access memory（DRAM）, flash memory（Flash）, hard disk drive（HDD）, as the next generation
One of strong candidate of " general " memory.
The research of the resistive mechanism on resistance-variable storing device is a study hotspot instantly, and group transition storage is designed to put down
Face structure, conductive filament when helping more intuitively to observe break-over of device（filaments）Formation.
The content of the invention
It is an object of the invention to provide a kind of resistance-variable storing device of planar structure and preparation method thereof, to realize to RRAM
The precise control of device size and the study mechanism for contributing to RRAM.
The resistance-variable storing device of the planar structure that the present invention is provided, possesses substrate, is formed at the resistive function on the substrate
Layer, and the Graphene electrodes for being formed at the two ends of the resistive functional layer.
Preferably, contact electrode is formed on the outside of Graphene electrodes respectively.
Preferably, the distance between Graphene electrodes is 20nm.
Preferably, the material of resistive functional layer is TiO2、Ta2O5、Al2O3、HfO2, one kind in ZnO, it is or wherein several
The combination planted.
The resistance-variable storing device preparation method that the present invention is provided, be with step：
Graphene layer is formed on substrate；
Patterning is carried out to the graphene layer and forms graphene nanobelt；
Make to form space in the graphene nanobelt, form Graphene electrodes pair；
Resistive functional layer is formed between the Graphene electrodes.
Preferably, before the Graphene electrodes are formed, contact electrode is formed at the graphene nanobelt two ends.
Preferably, in contact electrode two ends applied voltage, making the graphene nanobelt disconnect forming space.
Preferably, the space in the graphene nanobelt for being formed is 20nm.
Preferably, the material of the change resistance layer is TiO2、Ta2O5、Al2O3、HfO2, one kind in ZnO, it is or wherein several
Combination.
Preferably, the graphene nanobelt line width is 40~100nm.
Preferably, using low temperature ald technology growth resistive functional layer.
Invention effect
In the present invention, the method fused using electric Joule heat obtains tens nanometers wide in the centre position of graphene nanobelt
The space of degree, the method is simple, effective, save material cost.Based on side of the resistive functional layer on Graphene in ALD techniques
To growth characteristics, the resistive functional layer of RRAM device is dexterously prepared.Using the high mobility characteristic of grapheme material, realize
The low power operation of resistance-variable storing device.Additionally, the size of RRAM device is fused by the width and electric Joule heat of graphene nanobelt
The gap length for obtaining is determined, therefore the precise control to RRAM device size can be realized by both regulations above.It is flat
The RRAM device of face structure can eaily observe the shape of conductive filament, contribute to the study mechanism to RRAM.
Brief description of the drawings
Fig. 1 represents the flow chart for preparing planar structure resistance-variable storing device of the invention.
Fig. 2 represents the flow chart of preparation/transfer Graphene.
Fig. 3 represents the flow chart to form graphene nanobelt.
Fig. 4 to be represented and form the flow chart of contact electrode at black alkene nanobelt two ends.
Fig. 5 represents the flow chart to form resistive functional layer.
Fig. 6 represents the structural representation for preparing each stage during planar structure resistance-variable storing device of the invention.
Fig. 7 is planar structure resistance-variable storing device top view of the invention.
Fig. 8 is profile of the planar structure resistance-variable storing device of the invention along A-A directions.
Specific embodiment
Embodiments of the invention are described in detail hereinafter with reference to accompanying drawing, in various figures, identical element is using similar
Reference represent.Embodiment described below is exemplary, in order to simplify disclosure of the invention, hereinafter to particular case
The part and setting of son are described.Certainly, these are only example, it is intended to explain the present invention and it is not intended that to the present invention
Limitation.Additionally, the invention provides various specific techniques and the example of material, but as those skilled in the art's energy
As enough understanding, the present invention can not be realized according to these specific details.Unless hereinafter particularly point out, device
Each several part can be realized using technique well known in the art and material.In addition, fisrt feature described below second feature it
" on " structure can include that the first and second features be formed as the embodiment of directly contact, it is also possible to including other feature shapes
Into the embodiment between the first and second features, such first and second feature may not be directly contact.
Hereinafter, with reference to the accompanying drawings shown in 1~5 preparation planar structure resistance-variable storing device shown in flow chart and accompanying drawing 6
During each stage structural representation, one for the implementation method of resistance-variable storing device involved in the present invention is said
It is bright.
As shown in figure 1, in step S111, preparing/transfer Graphene.The preparation method of Graphene can use current stone
The main preparation methods of black alkene, such as mechanical stripping method, chemical stripping method, SiC epitaxial growth methods, chemical vapor deposition（CVD）Method
Deng.The main method that the controllable Graphene of currently acquired large-area high-quality, the number of plies is used in the present embodiment is chemical vapor deposition
Product method prepares Graphene.Chemical gaseous phase depositing process can be using low-carbon (LC) dissolubilities such as Ni, Cu, Pt in preparing the method for Graphene
Metal as substrate, using Copper Foil as substrate in the present embodiment.As specific one, as shown in Fig. 2 in step S1111,
Graphene is grown on Copper Foil using CVD method.Next, Graphene is transferred in target substrate.The main of Graphene turns
Shifting technology has " matrix etching " method, " volume to volume（roll-to-roll）" transfer techniques, " electrochemistry transfer " technology, " bubbling turn
Move " technology, " dry method transfer " technology, " mechanical stripping " technology etc..Substrate can be substrate commonly used in the art, such as glass substrate,
Sapphire Substrate, quartz substrate, plastic supporting base, silicon substrate or PEN substrate etc..Preferably silicon substrate.
In the present embodiment, realize being transferred to the above-mentioned Graphene grown on Copper Foil including silicon using conventional " matrix etching " method
On the substrate of substrate 101 and silicon oxide layer 102.As specific one, in the step S1112 shown in Fig. 2, on Graphene
Polymethyl methacrylate in spin coating（PMMA）.In step S1113, FeCl is placed into after baking3Solution or copper sulphate are molten
The Copper Foil below Graphene is dissolved in liquid.In step S1114, polymethyl methacrylate/Graphene is transferred to SiO2/
Si substrates.In step S1115, by PMMA/ Graphenes/SiO2/ Si structures are cleaned and dried through standard cleaning technique, are put successively
Enter in acetone, alcohol, polymethyl methacrylate is dissolved, obtain the silicon base 101 of 103/ silicon oxide layer of Graphene 102/
Complex.In step S1116, using N2/H2Mixed gas 350 DEG C of annealing acetone and organic matter that further removal is remained, obtain
To such as Fig. 6（a）Shown structure.But, the invention is not restricted to this, it is of course possible to using Graphene well known in the art prepare and
Transfer method forms Graphene in target substrate.
Next, returning to Fig. 1, in step S112, graphene nanobelt 105 is formed.As specific one, such as Fig. 3
It is shown, in shown step S1121, spin coating minus electron beam resist on Graphene 103 after the transfer is complete.In step
In S1122, expose the nanobelt figure 104 of 50nm line widths, obtain such as Fig. 6（b）Shown structure.In step S1123, adopt
The Graphene of exposed portion is etched with oxygen plasma lithographic method.Preferably, power is set to 100W in above-mentioned etching technics, when
Between be 15s, oxygen flow is 15sccm.In step S1124, the graphene nanobelt 105 of 50nm line widths is obtained after removing photoresist, such as
Fig. 6（c）It is shown.But, the present invention is not limited to this, and the line width of graphene nanobelt 105 can be 40nm~100 nm.Separately
Outward, graphene nanobelt 105 can be formed using etching technics well known in the art, and adjusts corresponding technique according to actual needs
Parameter.
Next, returning to Fig. 1, in step S113, contact electrode 106 is formed at the two ends of graphene nanobelt 105.Contact
Electrode 106 is mainly used in realizing interconnection between device or carries out electrical measurement, any contact that can realize above-mentioned functions
Electrode can be used, for example metal electrode, and the material of the metal electrode can be various metals, such as Ti, Au, Pt, Ni, Cu
Deng.As shown in figure 4, as specific one, forming titanium/gold electrode as contact electrode 106, specifically enter in accordance with the following steps
OK：The step of S1131 in, the spin coating positive photoresist on sample, such as AR-P679.04（Registration mark：ALLRESIST）.
In step S1132, electrode pad is exposed at Graphene two ends using electron beam alignment exposure method（Pad）Figure.In step
In S1133, using physical gas-phase deposite method titanium deposition and gold, it is preferable that the thickness of titanium layer is 10nm, the thickness of layer gold is
100nm.In step S1134, using stripping technology（lift-off）Obtain titanium/gold contact electrode 106.Preferably, in step
In S1135, further by above-mentioned device architecture in atmosphere of hydrogen with 400 DEG C of temperature, anneal 30 minutes, optimize contact performance.
Thus Fig. 6 is obtained（d）Shown structure.Each step and process conditions of contact electrode formed above, only preferably one,
But, the invention is not restricted to this, it is of course possible to form above-mentioned contact electrode using processing step well known in the art and condition.
Next, in the step S114 shown in Fig. 1, forming Graphene electrodes 107.As specific one, by
The two ends applied voltage of above-mentioned contact electrode 106, the Joule heat of generation fuses the location roughly halfway up of graphene nanobelt 105.
The speed of voltage increase is preferably 1V/s.As shown in Figure 5, location roughly halfway up is formed in graphene nanobelt 105
The space of 20nm or so.So as to form Fig. 6（e）Shown Graphene electrodes 107.The method has simple, effective, saving former
The effect of material cost.Furthermore, it is possible to the gap length for obtaining that fused by the width to graphene nanobelt and electric Joule heat
Regulation, realize to the precise control of RRAM device size.But, form space and be not limited to 20nm.
Finally, in step sl 15, resistive functional layer 108 is formed.Resistive functional layer 108 is preferably by TiO2、Ta2O5、
Al2O3、ZnO、HfO2Formed Deng binary metal compound.It is preferred that using low temperature ald（ALD）Form resistive functional layer
108.The thickness of resistive functional layer 108 is preferably 5 ~ 100nm.Used as specific one, the present embodiment uses low temperature ald
Method grows Al2O3Film is carried out in accordance with the following steps as resistive functional layer 108 referring in particular to Fig. 5：In step S1151,
In sample surfaces spin coating negative photoresist AR-N7720.13（Registration mark：ALLRESIST）.In step S1152, electricity is carried out
Beamlet exposes, and hereafter only metallic electrode portion is covered by photoresist.In step S1153, using low temperature ald technique
Growth Al2O3Film is used as resistive functional layer 108.For example, with trimethyl aluminium（TMA）It is precursors with water, reaction temperature is
130 DEG C, reaction chamber air pressure is 5 Torr.Single reaction time is included the trimethyl aluminium of liquid（TMA）The gas of volatilization is passed through
Reaction chamber, the reaction time is 100 ms, then is passed through the unreacted metal organic precursor of nitrogen removing and accessory substance of 1 s, will
Vapor is passed through reaction chamber, and the reaction time is 100 ms, then is passed through the unreacted vapor of nitrogen removing and accessory substance of 1 s.
Above-mentioned reaction carries out 50 cycles.In step S1154, resistance variation memory structure of the invention is obtained after removal photoresist, such as
Fig. 6（f）It is shown.In this step S115, based on ALD techniques in, in the characteristic of Graphene lateral growth, dexterously prepare RRAM
The resistive functional layer of device.Using the high mobility characteristic of grapheme material, the low power operation of resistance-variable storing device is capable of achieving.This
Outward, the RRAM device of the planar structure is conducive to the observation to the shape of conductive filament, so as to contribute to the mechanism to RRAM to grind
Study carefully.
Above-described embodiment, only realizes preferred one of the invention, and the present invention is not limited to this.For example, step S114
In, it would however also be possible to employ the high-precision photoetching process such as electron beam exposure method forms space in graphene nanobelt, so that shape
Into Graphene electrodes.Preferably, space is formed in graphene nanobelt location roughly halfway up.In addition, formed space can be with
It is tens nanometers.This manner it is also possible to omit step S113, that is, it is omitted in the step that graphene nanobelt two ends form contact electrode
Suddenly.
According to another embodiment, there is provided a kind of planar structure resistance-variable storing device, Fig. 7 is planar structure resistive of the invention
Memory top view, Fig. 8 is profile of the planar structure resistance-variable storing device of the invention along A-A directions.As shown in Figure 7 and Figure 8,
Planar structure resistance-variable storing device of the invention possess substrate, the alumina layer as resistive functional layer 108 being formed on substrate,
And it is formed at the Graphene electrodes 107 at the two ends of alumina layer.Wherein, the substrate includes silicon base 101 and silicon oxide layer
102.Preferably, contact electrode 106 is formed in the outside of Graphene electrodes 107 respectively.Contact electrode 106 can be Ti/Au electrodes.
Preferably, the distance between Graphene electrodes 107 is 20nm or so.Preferably, the width of Graphene electrodes 107 is 40~100nm.Resistance
The material for becoming functional layer 108 can be with TiO2、Ta2O5、Al2O3、HfO2, the combination of one or more in ZnO.Substrate can be
Substrate commonly used in the art, such as glass substrate, Sapphire Substrate, quartz substrate, plastic supporting base, silicon substrate or poly- naphthalenedicarboxylic acid second
Terephthalate substrate etc..Preferably silicon substrate.
More than, explained for resistance-variable storing device of the invention and preparation method thereof, but the present invention is not limited
Example more than, in the scope for not departing from idea of the invention, naturally it is also possible to carry out various improvement, deformation.
Claims (9)
1. a kind of resistance-variable storing device of planar structure, including, substrate, the resistive functional layer being formed on the substrate and shape
The electrode at resistive functional layer two ends described in Cheng Yu, it is characterised in that the electrode is Graphene electrodes；Including：Contact electrode, point
The Graphene electrodes outside is not formed at.
2. resistance-variable storing device according to claim 1, it is characterised in that distance between the Graphene electrodes is received for 20
Rice.
3. resistance-variable storing device according to claim 1, it is characterised in that the material of the resistive functional layer is TiO2、
Ta2O5、Al2O3、HfO2, one kind in ZnO, or wherein several combination.
4. the resistance-variable storing device preparation method of a kind of planar structure, it is characterised in that concretely comprise the following steps：
Graphene layer is formed on substrate；
Patterning is carried out to the graphene layer and forms graphene nanobelt；
Make to form space in the graphene nanobelt, form Graphene electrodes；
Resistive functional layer is formed between the Graphene electrodes.
5. resistance-variable storing device preparation method according to claim 4, it is characterised in that formed the Graphene electrodes it
Before, form contact electrode at the graphene nanobelt two ends.
6. resistance-variable storing device preparation method according to claim 5, it is characterised in that apply at the contact electrode two ends
Voltage, makes the graphene nanobelt disconnect forming space.
7. resistance-variable storing device preparation method according to claim 6, it is characterised in that in the graphene nanobelt for being formed
Space be 20nm.
8. the resistance-variable storing device preparation method according to claim 4 or 5, it is characterised in that the graphene nanobelt line
A width of 40~100nm.
9. the resistance-variable storing device preparation method according to any one of claim 4~6, it is characterised in that former using low temperature
Sublayer deposition technique grows resistive functional layer.
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| CN105895800B (en) * | 2016-04-21 | 2019-03-15 | 中国科学院微电子研究所 | Bipolar resistive random access memory and preparation method thereof |
| CN106206944A (en) * | 2016-09-29 | 2016-12-07 | 南京大学 | A kind of nano-film memristor and preparation method thereof |
| CN109686753B (en) * | 2017-10-18 | 2022-01-11 | 联华电子股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN108364669A (en) * | 2018-02-06 | 2018-08-03 | 常州印刷电子产业研究院有限公司 | Fuse Type printed memory and preparation method thereof |
| CN113594362B (en) * | 2021-07-29 | 2023-01-31 | 西安工业大学 | Low-power consumption nanometer SnS 2 Flexible resistive random access memory and preparation method thereof |
| CN115376634B (en) * | 2022-09-15 | 2024-04-05 | 浙江大学 | Construction and simulation method of compact model of resistive random access memory with graphene as electrode |
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| CN101599530A (en) * | 2009-06-24 | 2009-12-09 | 中国科学院宁波材料技术与工程研究所 | Memory cell of a kind of resistive random access memory (RRAM) and preparation method thereof |
| CN103337859A (en) * | 2013-07-16 | 2013-10-02 | 国家电网公司 | Splitting control method of large-scale regional power grids |
| CN103824938A (en) * | 2014-03-03 | 2014-05-28 | 南京大学 | Resistive random access memory structure and preparation method thereof |
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| GB2516841A (en) * | 2013-07-31 | 2015-02-11 | Ibm | Resistive memory element based on oxygen-doped amorphous carbon |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101599530A (en) * | 2009-06-24 | 2009-12-09 | 中国科学院宁波材料技术与工程研究所 | Memory cell of a kind of resistive random access memory (RRAM) and preparation method thereof |
| CN103337859A (en) * | 2013-07-16 | 2013-10-02 | 国家电网公司 | Splitting control method of large-scale regional power grids |
| CN103824938A (en) * | 2014-03-03 | 2014-05-28 | 南京大学 | Resistive random access memory structure and preparation method thereof |
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