CN105161617A - Resistive random access memory with planar structure and manufacturing method thereof - Google Patents
Resistive random access memory with planar structure and manufacturing method thereof Download PDFInfo
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- CN105161617A CN105161617A CN201510608779.XA CN201510608779A CN105161617A CN 105161617 A CN105161617 A CN 105161617A CN 201510608779 A CN201510608779 A CN 201510608779A CN 105161617 A CN105161617 A CN 105161617A
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Abstract
The invention belongs to the technical field of resistive random access memories, and specifically discloses a resistive random access memory with a planar structure and a manufacturing method thereof. The resistive random access memory is provided with graphene electrodes formed at two ends of a resistive random functional layer, and low power consumption operation of the resistive random access memory is realized by utilizing high mobility of a graphene material. The resistive random access memory with the planar structure is favorable for observing the shape of a conductive filament and researching the mechanism of the resistive random access memory. Gaps with the size of dozens of nanometers are formed close to the middle of a graphene nano belt by adopting an electric joule heat fusing method, and then the graphene electrodes are formed. The resistive random functional layer is formed on the basis of the characteristic of lateral growth thereof in the graphene in an atomic layer deposition process. The method is simple and effective and reduces the cost of raw materials, and the size of the resistive random access memory can be adjusted.
Description
Technical field
The invention belongs to resistance-variable storing device technical field, be specifically related to resistance-variable storing device of a kind of planar structure and preparation method thereof.
Background technology
Along with the further scaled down of feature sizes of semiconductor devices, traditional flash memory technology will reach the limit of size.For improving the performance of device further, technical staff starts to carry out positive exploration to new construction, new material, new technology.In recent years, various novel non-volatility memorizer obtains and develops rapidly.Wherein, resistance-variable storing device (RRAM) is simple by means of its structure, micro ability strong, high density, data hold time long, can three-dimensional integrated and with the advantage such as complementary metal oxide semiconductors (CMOS) (CMOS) process compatible, be subject to industry more and more to pay close attention to, be considered to very likely substitute static RAM (SRAM), dynamic random access memory (DRAM), flash memory (Flash), hard disk drive (HDD), become one of strong candidate of " general " memory of future generation.
Research about the resistive mechanism of resistance-variable storing device is a study hotspot instantly, and group transition storage is designed to planar structure, the formation of conductive filament (filaments) when contributing to observing break-over of device more intuitively.
Summary of the invention
The object of the present invention is to provide resistance-variable storing device of a kind of planar structure and preparation method thereof, to realize the accurate control of RRAM device size and the study mechanism that contributes to RRAM.
The resistance-variable storing device of planar structure provided by the invention, possesses substrate, is formed at the resistive functional layer on described substrate, and is formed at the Graphene electrodes at two ends of described resistive functional layer.
As preferably, outside Graphene electrodes, form contact electrode respectively.
As preferably, the distance between Graphene electrodes is 20nm.
As preferably, the material of resistive functional layer is TiO
2, Ta
2o
5, Al
2o
3, HfO
2, one in ZnO, or wherein several combination.
Resistance-variable storing device preparation method provided by the invention, having step is:
Substrate forms graphene layer;
Patterning is carried out to described graphene layer and forms graphene nanobelt;
Make to form space in described graphene nanobelt, form Graphene electrodes pair;
Resistive functional layer is formed between described Graphene electrodes.
As preferably, before the described Graphene electrodes of formation, form contact electrode at described graphene nanobelt two ends.
As preferably, apply voltage at described contact electrode two ends, described graphene nanobelt is disconnected and forms space.
As preferably, the space in the graphene nanobelt formed is 20nm.
As preferably, the material of described change resistance layer is TiO
2, Ta
2o
5, Al
2o
3, HfO
2, one in ZnO, or wherein several combination.
As preferably, described graphene nanobelt live width is 40 ~ 100nm.
As preferably, adopt low temperature ald technology growth resistive functional layer.
Invention effect
In the present invention, the method that electricity consumption Joule heat is fused obtains the space of tens nano-widths in the centre position of graphene nanobelt, and the method is simple, effectively, save material cost.Based on the lateral growth characteristic of resistive functional layer in ALD technique on Graphene, prepare the resistive functional layer of RRAM device dexterously.Utilize the high mobility characteristic of grapheme material, realize the low power operation of resistance-variable storing device.In addition, the size of RRAM device determined by the width of graphene nanobelt and the electric Joule heat gap length obtained that fuses, therefore by regulating the two accurate control that can realize RRAM device size above.The RRAM device of planar structure can observe eaily and the shape of conductive filament contribute to the study mechanism to RRAM.
Accompanying drawing explanation
Fig. 1 represents the flow chart preparing planar structure resistance-variable storing device of the present invention.
Fig. 2 represents the flow chart of preparation/transfer Graphene.
Fig. 3 represents the flow chart forming graphene nanobelt.
Fig. 4 represents the flow chart forming contact electrode at black alkene nanobelt two ends.
Fig. 5 represents the flow chart forming resistive functional layer.
Fig. 6 represents the structural representation in each stage in the process preparing planar structure resistance-variable storing device of the present invention.
Fig. 7 is planar structure resistance-variable storing device vertical view of the present invention.
Fig. 8 is the profile of planar structure resistance-variable storing device of the present invention along A-A direction.
Embodiment
Describe embodiments of the invention in detail hereinafter with reference to accompanying drawing, in various figures, identical element adopts similar Reference numeral to represent.The following stated embodiment is exemplary, of the present invention open in order to simplify, and is hereinafter described the parts of specific examples and setting.Certainly, these are only examples, are intended to explain the present invention and can not be interpreted as limitation of the present invention.In addition, the invention provides the example of various specific technique and material, but just as the skilled person will understand like that, the present invention can be realized not in accordance with these specific details.Unless particularly pointed out hereinafter, each several part of device all can adopt technique well known in the art and material to realize.In addition, fisrt feature described below second feature it " on " structure can comprise the embodiment that the first and second features are formed as directly contact, the feature that also can comprise other is formed in the embodiment between the first and second features, and such first and second features may not be direct contacts.
Below, the structural representation in each stage in the process of the flow chart with reference to the accompanying drawings shown in 1 ~ 5 and the preparation planar structure resistance-variable storing device shown in accompanying drawing 6, the example for the execution mode of resistance-variable storing device involved in the present invention is described.
As shown in Figure 1, in step S111, preparation/transfer Graphene.The preparation method of Graphene can adopt the main preparation methods of current Graphene, as mechanical stripping method, chemical stripping method, SiC epitaxial growth method, chemical vapor deposition (CVD) method etc.The main method that obtains the controlled Graphene of large-area high-quality, the number of plies at present and chemical gaseous phase depositing process is adopted to prepare Graphene in the present embodiment.Chemical gaseous phase depositing process is prepared in the method for Graphene and the low-carbon (LC) solube metallics such as Ni, Cu, Pt can be adopted as substrate, using Copper Foil as substrate in the present embodiment.As concrete one example, as shown in Figure 2, in step S1111, adopt CVD method growing graphene on Copper Foil.Next, Graphene is transferred in target substrate.The main transfer techniques of Graphene has " matrix etching " method, " volume to volume (roll-to-roll) " transfer techniques, " electrochemistry transfer " technology, " bubbling transfer " technology, " dry method transfer " technology, " mechanical stripping " technology etc.Substrate can commonly use substrate for this area, as glass substrate, Sapphire Substrate, quartz substrate, plastic, silicon substrate or PEN substrate etc.Be preferably silicon substrate.In the present embodiment, adopt conventional " matrix etching " method realize the above-mentioned Graphene grown on Copper Foil to be transferred to comprise silicon base 101 and silicon oxide layer 102 substrate on.As concrete one example, in the step S1112 shown in Fig. 2, polymethyl methacrylate (PMMA) in spin coating on Graphene.In step S1113, after baking, be placed into FeCl
3the Copper Foil below Graphene is dissolved in solution or copper-bath.In step S1114, polymethyl methacrylate/Graphene is transferred to SiO
2/ Si substrate.In step S1115, by PMMA/ Graphene/SiO
2/ Si structure is cleaned through standard cleaning technique and is dried, and puts into acetone, alcohol successively, is dissolved by polymethyl methacrylate, obtains the complex of Graphene 103/ silicon oxide layer 102/ silicon base 101.In step S1116, adopt N
2/ H
2mist 350 DEG C annealing removes residual acetone and organic substance further, obtains structure as shown in Figure 6 (a).But, the present invention is not limited thereto, Graphene well known in the art preparation and transfer method certainly can be adopted in target substrate to form Graphene.
Next, return Fig. 1, in step S112, form graphene nanobelt 105.As concrete one example, as shown in Figure 3, in shown step S1121, spin coating minus electron beam resist on Graphene 103 after the transfer is complete.In step S1122, expose the nanobelt figure 104 of 50nm live width, obtain structure as shown in Figure 6 (b).In step S1123, adopt the Graphene of oxygen plasma lithographic method etching exposed portion.Preferably, in above-mentioned etching technics, power is set to 100W, and the time is 15s, and oxygen flow is 15sccm.In step S1124, obtain the graphene nanobelt 105 of 50nm live width after removing photoresist, as shown in Figure 6 (c).But the present invention is not limited to this, the live width of graphene nanobelt 105 can be 40nm ~ 100nm.In addition, etching technics well known in the art can be adopted to form graphene nanobelt 105, and adjust corresponding process parameters according to actual needs.
Next, return Fig. 1, in step S113, form contact electrode 106 at graphene nanobelt 105 two ends.Contact electrode 106 is mainly used in realizing interconnected between device or carries out electrical measurement, any contact electrode that can realize above-mentioned functions all can use, such as metal electrode, the material of this metal electrode can be various metal, such as Ti, Au, Pt, Ni, Cu etc.As shown in Figure 4, as concrete one example, formed titanium/gold electrode as contact electrode 106, specifically carry out in accordance with the following steps: step S1131 in, spin coating positive photoresist on sample, as AR-P679.04(registered trade mark: ALLRESIST).In step S1132, electron beam alignment exposure method is adopted to expose electrode pad (Pad) figure at Graphene two ends.In step S1133, adopt physical gas-phase deposite method titanium deposition and gold, preferably, the thickness of titanium layer is 10nm, and the thickness of layer gold is 100nm.In step S1134, stripping technology (lift-off) is adopted to obtain titanium/golden contact electrode 106.Preferably, in step S1135, further by above-mentioned device architecture in atmosphere of hydrogen with 400 DEG C of temperature, anneal 30 minutes, optimize contact performance.Obtain the structure shown in Fig. 6 (d) thus.More than form each step and the process conditions of contact electrode, only a conduct preferably example, but, the present invention is not limited thereto, processing step well known in the art and condition certainly can be adopted to form above-mentioned contact electrode.
Next, in the step S114 shown in Fig. 1, form Graphene electrodes 107.As concrete one example, by applying voltage at above-mentioned contact electrode 106 two ends, the Joule heat of generation is by position fusing roughly middle for graphene nanobelt 105.The speed that voltage increases is preferably 1V/s.As shown in Figure 5, roughly middle in graphene nanobelt 105 position forms the space of about 20nm.Thus, form the Graphene electrodes 107 shown in Fig. 6 (e).The method has simply, effectively, the effect of the cost that saves material.In addition, by the adjustment of the gap length obtained that fuses to the width of graphene nanobelt and electric Joule heat, the accurate control to RRAM device size can be realized.But, form space and be not limited to 20nm.
Finally, in step sl 15, resistive functional layer 108 is formed.Resistive functional layer 108 is preferably by TiO
2, Ta
2o
5, Al
2o
3, ZnO, HfO
2formed Deng binary metal compound.Preferred employing low temperature ald (ALD) forms resistive functional layer 108.The thickness of resistive functional layer 108 is preferably 5 ~ 100nm.As a concrete example, the present embodiment adopts low temperature ald method growth Al
2o
3film is as resistive functional layer 108, and concrete reference Fig. 5 carries out in accordance with the following steps: in step S1151, at sample surfaces spin coating negative photoresist AR-N7720.13(registered trade mark: ALLRESIST).In step S1152, carry out electron beam exposure, after this only metal electrode part is covered by photoresist.In step S1153, adopt low temperature ald technique growth Al
2o
3film is as resistive functional layer 108.Such as, with trimethyl aluminium (TMA) and water for precursors, reaction temperature is 130 DEG C, and reaction chamber air pressure is 5Torr.The gas comprised the trimethyl aluminium of liquid state (TMA) volatilizees single reaction time passes into reaction chamber, reaction time is 100ms, the nitrogen passing into 1s again removes unreacted metal organic precursor and accessory substance, steam is passed into reaction chamber, reaction time is 100ms, then the nitrogen passing into 1s removes unreacted steam and accessory substance.50 cycles are carried out in above-mentioned reaction.In step S1154, after removing photoresist, obtain resistance variation memory structure of the present invention, as shown in Fig. 6 (f).In this step S115, based in ALD technique, in the characteristic of Graphene lateral growth, prepare the resistive functional layer of RRAM device dexterously.Utilize the high mobility characteristic of grapheme material, the low power operation of resistance-variable storing device can be realized.In addition, the RRAM device of this planar structure is conducive to the observation of the shape to conductive filament, thus contributes to the study mechanism to RRAM.
Above-described embodiment, be only and realize a preferred example of the present invention, the present invention is not limited to this.Such as, in step S114, also can adopt the high-precision photoetching processes such as electron beam exposure method in graphene nanobelt, form space, thus form Graphene electrodes.Be preferably, in the formation space, position that graphene nanobelt is roughly middle.In addition, to form space can be tens nanometers.So, also can omit step S113, namely be omitted in the step that graphene nanobelt two ends form contact electrode.
According to another embodiment, provide a kind of planar structure resistance-variable storing device, Fig. 7 is planar structure resistance-variable storing device vertical view of the present invention, and Fig. 8 is the profile of planar structure resistance-variable storing device of the present invention along A-A direction.As shown in Figure 7 and Figure 8, planar structure resistance-variable storing device of the present invention possesses substrate, is formed at the alumina layer as resistive functional layer 108 on substrate and is formed at the Graphene electrodes 107 at two ends of alumina layer.Wherein, described substrate comprises silicon base 101 and silicon oxide layer 102.Be preferably, outside Graphene electrodes 107, form contact electrode 106 respectively.Contact electrode 106 can be Ti/Au electrode.Be preferably, the distance between Graphene electrodes 107 is about 20nm.Be preferably, Graphene electrodes 107 width is 40 ~ 100nm.The material of resistive functional layer 108 can TiO
2, Ta
2o
5, Al
2o
3, HfO
2, the combination of one or more in ZnO.Substrate can commonly use substrate for this area, as glass substrate, Sapphire Substrate, quartz substrate, plastic, silicon substrate or PEN substrate etc.Be preferably silicon substrate.
Above, explain for resistance-variable storing device of the present invention and preparation method thereof, but the invention is not restricted to above example, in the scope not departing from main idea of the present invention, can certainly various improvement, distortion be carried out.
Claims (10)
1. a resistance-variable storing device for planar structure, comprises, and substrate, is formed at the resistive functional layer on described substrate and is formed at the electrode at described resistive functional layer two ends, and it is characterized in that, described electrode is Graphene electrodes.
2. resistance-variable storing device according to claim 1, is characterized in that, also comprises: contact electrode, is formed at respectively outside described Graphene electrodes.
3. resistance-variable storing device according to claim 1, is characterized in that, the distance between described Graphene electrodes is 20 nanometers.
4. resistance-variable storing device according to claim 1, is characterized in that, the material of described resistive functional layer is TiO
2, Ta
2o
5, Al
2o
3, HfO
2, one in ZnO, or wherein several combination.
5. a resistance-variable storing device preparation method for planar structure, is characterized in that, concrete steps are:
Substrate forms graphene layer;
Patterning is carried out to described graphene layer and forms graphene nanobelt;
Make to form space in described graphene nanobelt, form Graphene electrodes;
Resistive functional layer is formed between described Graphene electrodes.
6. resistance-variable storing device preparation method according to claim 5, is characterized in that, before the described Graphene electrodes of formation, forms contact electrode at described graphene nanobelt two ends.
7. resistance-variable storing device preparation method according to claim 6, is characterized in that, applies voltage at described contact electrode two ends, described graphene nanobelt is disconnected and forms space.
8. resistance-variable storing device preparation method according to claim 7, is characterized in that, the space in the graphene nanobelt formed is 20nm.
9. the resistance-variable storing device preparation method according to claim 5 or 6, is characterized in that, described graphene nanobelt live width is 40 ~ 100nm.
10. the resistance-variable storing device preparation method according to any one of claim 5 ~ 7, is characterized in that, adopts low temperature ald technology growth resistive functional layer.
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| CN105895800A (en) * | 2016-04-21 | 2016-08-24 | 中国科学院微电子研究所 | Bipolar resistive random access memory and preparation method thereof |
| CN106206944A (en) * | 2016-09-29 | 2016-12-07 | 南京大学 | A kind of nano-film memristor and preparation method thereof |
| CN108364669A (en) * | 2018-02-06 | 2018-08-03 | 常州印刷电子产业研究院有限公司 | Fuse Type printed memory and preparation method thereof |
| CN109686753A (en) * | 2017-10-18 | 2019-04-26 | 联华电子股份有限公司 | Semiconductor structure and preparation method thereof |
| CN113594362A (en) * | 2021-07-29 | 2021-11-02 | 西安工业大学 | Low-power consumption nano SnS2 flexible resistive random access memory and preparation method thereof |
| CN115376634A (en) * | 2022-09-15 | 2022-11-22 | 浙江大学 | Method for constructing and simulating compact model of resistive random access memory by taking graphene as electrode |
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| CN115376634A (en) * | 2022-09-15 | 2022-11-22 | 浙江大学 | Method for constructing and simulating compact model of resistive random access memory by taking graphene as electrode |
| CN115376634B (en) * | 2022-09-15 | 2024-04-05 | 浙江大学 | Construction and simulation method of compact model of resistive random access memory with graphene as electrode |
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