JP2011187509A - Electronic element substrate and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic element substrate, with which a variety of electronic elements are fabricated through simple processes by reducing specific resistance of a partial region or the whole region of an oxide. <P>SOLUTION: There is provided the method of manufacturing the electronic element substrate, including a resistance reduction processing step of reducing the specific resistance of the partial region or the whole region of the oxide in a substrate at least a part of the outermost surface layer of which is made of the oxide having specific resistance of ≤1×10<SP>9</SP>Ωcm by applying a potential higher than the potential of the substrate to the partial region or the whole region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic element substrate and a method for manufacturing the same.

In recent years, electronic devices using oxide conductors and oxide semiconductors have attracted attention.
For example, ITO (indium tin oxide) has been put to practical use as a transparent conductive film, and IGZO (oxide containing indium, gallium, and zinc), ZnO (zinc oxide), etc. are used as oxide semiconductors, and TFT activity. Applications to layers, various sensors, light-emitting devices, etc. are being studied.
Since many oxides have a wide band gap and are transparent to visible light, using oxide conductors / semiconductors is expected to produce new electronic devices that could not be realized with conventional materials. ing.

By the way, electronic devices such as thin film transistors (TFTs) and capacitors (capacitors) generally repeat a series of steps including film formation, resist pattern formation by photolithography, etching, and resist pattern peeling a plurality of times. It is formed by.
For example, in the case of a TFT with a bottom gate structure, it is necessary to perform the above-described series of steps for each of a gate electrode, a gate insulating film, an active layer (semiconductor layer), a source / drain electrode, a passivation layer, and the like. Film formation and etching are required.

As a simple method for manufacturing an electronic device, a transparent conductive oxide layer is used as an anode, and a so-called operation probe microscope (SPM) represented by an atomic force microscope (AFM) or a scanning tunneling microscope (STM) is used. A technique for forming a higher resistance semiconductor region adjacent to a conductor region in a transparent conductive oxide layer by applying a negative bias to the cathode and applying an electric field to the cathode is known. (For example, refer to Patent Document 1).
In addition, in connection with this technology, a research example of so-called AFM lithography in which the probe of an atomic force microscope is brought close to the surface of a La _0.8 Ba _0.2 MnO ₃ (LBMO) thin film, which is an oxide thin film, has been reported. (For example, refer nonpatent literature 1).
In addition to the above, various studies have been made on microfabrication techniques using an atomic force microscope probe (see, for example, Patent Documents 2 to 4).

JP 2005-268724 A JP-A-10-223609 JP 2000-162459 A JP 2004-110926 A

J.App.Phys.95 (2004) 7091

However, in the technique described in Patent Document 1, only the semiconductor region can be produced in the conductor by increasing the electrical resistance of the transparent oxide layer, and the types of electronic elements that can be produced are limited.
Further, in Non-Patent Document 1 described above, when a potential (minus direction) lower than the potential of the thin film is applied to the probe like the normal AFM anodizing polarity on the surface of the LBMO thin film, the controllability of AFM lithography is improved. On the other hand, it has been reported that the controllability becomes higher when applied to a potential higher than the potential of the thin film (positive direction). However, the electrical resistance of the surface layer in the positive direction has increased or decreased. No mention is made of whether or not.
Also, no other technique for reducing the resistance of oxide has been found in other anodizing microfabrication techniques using SPM.
For this reason, there is a demand for the development of a method for manufacturing a wider variety of electronic devices by a simpler process by reducing the resistance of the oxide.

This invention is made | formed in view of the above, and makes it a subject to achieve the following objectives.
That is, an object of the present invention is to provide a method for manufacturing an electronic element substrate that can manufacture various electronic elements by a simple process by reducing the specific resistance of a partial region or the entire region of an oxide.
Another object of the present invention is to have various regions having various specific resistance values adjacent to each other in the same layer of oxide, and not contaminated by impurities at the interface between the regions. An object of the present invention is to provide an electronic element substrate capable of easily realizing an oxide electronic device.

As a result of intensive studies, the present inventors have determined that the specific resistance of the partial region or the entire region can be increased by applying a higher potential to the partial region or the entire region of the oxide than the other portions of the substrate or the oxide. Based on this knowledge, the present invention was completed.
That is, specific means for solving the above-described problems are as follows.

<1> A potential higher than the potential of the substrate is applied to a partial region or the entire region of the oxide in a substrate in which at least a part of the outermost layer is made of an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less. A method for manufacturing an electronic element substrate, comprising: a resistance reduction process for reducing the specific resistance of the partial region or the entire region.

<2> The potential of the oxide other than the first region with respect to the first region of the oxide in the substrate in which at least a part of the outermost layer is made of an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less. Lower resistance treatment step of reducing the specific resistance of the first region by applying a higher potential than
The specific resistance of the second region is increased by applying a potential lower than the potential of the oxide other than the second region to the second region of the oxide other than the first region. A high resistance treatment process,
Have
The manufacturing method of the electronic element substrate which has at least 2 or more types of area | region of a low resistance area | region and a high resistance area | region in the same area | region of the said oxide.

<3> The method for manufacturing an electronic element substrate according to <1> or <2>, wherein there is a region where no potential is applied in the same region of the oxide.

<4> The oxide is an oxide semiconductor containing at least one element of In, Ga, Zn, Sn, Ti, Ge, Sb, V, Nb, W, and Ni. <1> to <3> The manufacturing method of the electronic element board | substrate of any one of these.

<5> The electronic device according to any one of <1> to <4>, wherein the oxide is made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO). A method for manufacturing a substrate.
(Here, a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0, respectively.)

<6> The electronic element substrate according to any one of <1> to <5>, wherein the resistance reduction treatment step is performed by causing the oxide made of a conductive material to face or contact the oxide. Manufacturing method.

<7> The method for manufacturing an electronic element substrate according to <6>, wherein the electrode used in the resistance reduction treatment step has an area of a portion facing or contacting the oxide of 1 × 10 ⁻¹⁵ m ² or more.

<8> The electrode used in the low resistance treatment step is described in <6> or <7>, in which a large number of nanoscale or micrometer scale structures are provided in a portion facing or contacting the oxide. A method for manufacturing an electronic element substrate.

<9> The electronic element substrate according to any one of <2> to <8>, wherein the resistance increasing treatment step is performed by causing the oxide made of a conductive material to face or contact the oxide. Manufacturing method.

<10> The method for producing an electronic element substrate according to <9>, wherein the electrode used in the high resistance treatment process has an area of a portion facing or contacting the oxide of 1 × 10 ⁻¹⁵ m ² or more.

<11> The electrode used in the high resistance treatment step is described in <9> or <10>, in which a large number of nanoscale or micrometer scale structures are provided in a portion facing or contacting the oxide. A method for manufacturing an electronic element substrate.

<12> In the low resistance treatment step, the source electrode of the thin film transistor is formed by reducing the specific resistance of a part of the oxide region, and the specific resistance of another region in the same oxide region is reduced. The method for producing an electronic element substrate according to <1> to <11>, wherein the drain electrode is formed by performing the step.

<13> In the low resistance treatment step, the polygonal source electrode of the thin film transistor is formed by reducing the specific resistance of the partial region of the oxide, and the ratio of another region in the same oxide region The electronic element substrate according to any one of <1> to <12>, wherein a polygonal drain electrode having sides that are parallel to one side of the source electrode and have the same length is provided by reducing resistance. Manufacturing method.

<14> The region between the source electrode and the drain electrode is subjected to the low-resistance treatment process or the high-resistance treatment process so that the region between the source electrode and the drain electrode is processed. <12> or <13> The method for producing an electronic element substrate according to <12>, wherein the electron channel is formed by adjusting the specific resistance of the oxide portion in the region.

<15> In the low resistance treatment step, the specific resistance of the two regions of the oxide is reduced, and if necessary, between the two regions in the same oxide portion in the high resistance treatment step. The method for manufacturing an electronic element substrate according to any one of <1> to <11>, wherein the capacitor is formed by increasing a specific resistance of the region.

<16> The specific resistance of the pair of comb-shaped regions of the oxide is reduced in the low-resistance treatment step, and further, if necessary, The method for manufacturing an electronic element substrate according to any one of <1> to <11>, wherein a pair of comb-shaped electrodes is formed by increasing a specific resistance of a region between the electrodes.

<17> The specific resistance of the plurality of regions of the oxide is reduced in the low resistance treatment step, and the specific resistance of another region in the same oxide portion in the high resistance treatment step as necessary. The method of manufacturing an electronic element substrate according to any one of <1> to <11>, wherein a stripe-shaped electrode is formed by increasing the height of the substrate.

<18> In the same oxide portion of the substrate having at least a part of the outermost layer made of an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less, a low resistance region having a low specific resistance, a high resistance region having a high specific resistance, And an electronic element substrate having at least three types of regions having a specific resistance intermediate between the low resistance region and the high resistance region.

<19> The electron according to <18>, wherein the oxide is an oxide semiconductor containing at least one element of In, Ga, Zn, Sn, Ti, Ge, Sb, V, Nb, W, and Ni. Element substrate.

<20> The electronic element substrate according to <18> or <19>, wherein the oxide is made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO).
(Here, a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0, respectively.)

ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the electronic element board | substrate which can produce a various electronic element with a simple process can be provided by reducing the specific resistance of the partial area | region or all area | region of an oxide.
In addition, according to the present invention, there are adjacent regions having various specific resistance values in the same layer of oxide, and there is no contamination due to impurities at the interface between the regions, and there are various simple configurations. An electronic element substrate capable of easily realizing an oxide electronic device can be provided.

It is a manufacturing process figure which shows an example of the 1st Embodiment of this invention. It is a schematic sectional drawing which shows the AA cross section of FIG. It is a schematic sectional drawing which shows another example of the 1st Embodiment of this invention. It is a schematic plan view which shows an example of the 1st Embodiment of this invention. It is a schematic plan view which shows another example of the 1st Embodiment of this invention. It is a schematic plan view which shows another example of the 1st Embodiment of this invention. It is a schematic plan view which shows another example of the 1st Embodiment of this invention. It is a manufacturing process figure which shows an example of the 2nd Embodiment of this invention. It is a schematic sectional drawing showing the BB cross section of FIG.8 (E). It is a manufacturing process figure which shows an example of the 3rd Embodiment of this invention. It is a schematic plan view which shows an example of the 4th Embodiment of this invention. (A) is a schematic plan view which shows an example of the pattern electrode used for the 5th Embodiment of this invention, (B) is the sectional view on the AA line of (A). In the 5th Embodiment of this invention, it is a schematic sectional drawing which shows an example of a mode that an electric potential is applied to an oxide layer using a pattern electrode. In the 5th Embodiment of this invention, it is a schematic sectional drawing which shows an example of the low resistance pattern area | region and high resistance pattern area | region formed using the pattern electrode. (A) is a schematic sectional drawing which shows the structure of the thin film sample in Experimental example 1, (B) is a schematic sectional drawing which shows the method of the resistance reduction process with respect to this sample, (C) is this sample It is a schematic sectional drawing which shows the method of high resistance processing with respect to (D), (D) is a schematic sectional drawing which shows the method of the current mapping with respect to this sample. 6 is a current mapping image in Experimental Example 1. 6 is a graph showing a relationship between a voltage applied to a needle probe and a resistance value of an IGZO film in Experimental Example 1. (A) is a schematic sectional drawing which shows the structure of the thin film sample in Experimental example 3, (B) is a schematic sectional drawing which shows the method of the high resistance process with respect to this sample, (C) is this sample It is a schematic sectional drawing which shows the method of the current mapping with respect to. (A) is an AFM topo image in Experimental Example 3, (B) is an AFM bird's-eye view in Experimental Example 3, and (C) is a current mapping image in Experimental Example 3. It is a SEM image in Experimental example 3. It is a SEM image (magnification 3000 times) of the structure in Experimental example 4. It is a SEM image (magnification 10,000 times) of the structure in example 4 of an experiment.

In the method for manufacturing an electronic element substrate of the present invention, at least a part of the outermost layer is made of an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less. A lower resistance treatment step of lowering the specific resistance of the partial region or the entire region by applying a potential higher than the potential. Here, a part of the outermost layer (oxide) has a region other than a region in which the resistance reduction treatment process is performed (for example, a region in which a resistance increase treatment process described later is performed or a region in which no potential application is performed). You may do it.
Hereinafter, the above-mentioned process of “reducing the specific resistance of the partial region or the entire region by applying a potential higher than the potential of the substrate to the partial region or the entire region of the oxide”. May simply be referred to as “resistance reduction processing”.

By making the manufacturing method of an electronic element substrate the above-described configuration of the present invention, the specific resistance of a partial region or the entire region of the oxide can be reduced, and a low resistance region can be formed in a part of the outermost layer. A variety of oxide electronic devices can be manufactured by a simple process.
The reason why the specific resistance of the oxide is reduced by the low resistance treatment step is not clear, but it is presumed that the amount of oxygen deficiency in the oxide can be increased by applying the above potential. However, the present invention is not limited by this cause.

In the conventional method of manufacturing an electronic device, it is necessary to perform a photolithography process including film formation, resist pattern formation, etching, and resist pattern peeling for each element such as an electrode, an insulating layer, and a semiconductor layer. Was complicated. Further, since each of the above elements is formed as a separate layer, there are problems of parasitic capacitance and interface contamination between layers due to residual resist pattern peeling.
According to the method for manufacturing an electronic element substrate of the present invention, the high resistance region and the low resistance region can be formed only by applying a potential (including polarity control), so that the manufacturing process is simplified. Further, since the high resistance region and the low resistance region can be formed in the same layer, the problem of interface contamination and the problem of parasitic capacitance are reduced. Furthermore, since the interface of the semiconductor layer / electrode layer is formed with the same metal element composition, it is considered that the manufacturing method is very suitable for forming an ideal ohmic electrode.

As an example of the method for manufacturing an electronic element substrate of the present invention, for example, an electrode layer adjacent to a semiconductor layer can be formed by reducing the specific resistance of a part of an oxide layer that is a semiconductor layer.
In this manner, for example, a source electrode and a drain electrode of a thin film transistor and a semiconductor layer (channel layer) existing between the source electrode and the drain electrode can be formed in the same layer.
In addition to a thin film transistor, a two-terminal electronic element including a pair of electrodes and a semiconductor layer existing between the pair of electrodes in the same layer can be manufactured. Further, by insulating the semiconductor layer by, for example, a high resistance process described later, a capacitor having a pair of electrodes and an insulating layer existing between the pair of electrodes in the same layer is manufactured. You can also.

  In the present invention, the “outermost layer (of the substrate)” refers to a region from the outermost surface (depth 0 nm) to the depth 30 nm in the thickness direction of the substrate. The “outermost layer” in the present invention is a term indicating the above-mentioned region, and is not limited to a form that is an independent layer.

The method for manufacturing an electronic element substrate of the present invention further includes the second region other than the region (hereinafter, also referred to as “first region”) for performing the resistance reduction treatment of the oxide in the outermost layer. It is preferable to have a high resistance treatment step of increasing the specific resistance of the second region by applying a potential lower than the potential of the oxide other than the second region of the substrate.
Specifically, this preferable form is such that at least a part of the outermost layer has a specific resistance of 1 × 10 ⁹ Ω · cm or less and the oxide has a first region of the oxide in the substrate. Applying a potential higher than the potential outside the first region to reduce the specific resistance of the first region, and a second region other than the first region of the oxide On the other hand, a high resistance treatment step of increasing the specific resistance of the second region by applying a potential lower than the potential of the oxide other than the second region, and the oxide The electronic element substrate manufacturing method for manufacturing an electronic element substrate having at least two types of regions of a low resistance region and a high resistance region in the same region.
Hereinafter, the above-mentioned "reducing the specific resistance of the first region by applying a potential higher than the potential of the oxide other than the first region to the first region of the oxide" This process may be simply referred to as “resistance reduction treatment”, and the above “the second region of the oxide other than the first region is more than the potential of the oxide other than the second region. The process of “increasing the specific resistance of the second region by applying a low potential” may be simply referred to as “high resistance process”.
Accordingly, since at least two types of regions of the low resistance region and the high resistance region can be formed in the same region of the oxide, a wider variety of oxide electronic devices can be manufactured.

It is preferable that the method for manufacturing an electronic element substrate of the present invention further includes a region where no potential application is performed, in addition to the region where the resistance reduction process is performed and the region where the resistance increase process is performed. In other words, the region where no potential application is performed is a region where neither high resistance treatment nor low resistance treatment is performed.
As a result, at least 3 of the oxide in the outermost layer is divided into a high resistance region, a low resistance region, and an intermediate specific resistance region (region showing an intermediate specific resistance between the high resistance region and the low resistance region). Since it can be divided into regions having various specific resistances, an electric resistance pattern can be formed with an arbitrary design, and a wider variety of oxide electronic devices can be manufactured.
As a specific form of the electronic element substrate in the present invention,
(1) The form in which the oxide in the outermost layer is composed of a region for performing a resistance reduction treatment, a region for performing a resistance enhancement treatment, and a region for not applying a potential,
(2) The form in which the oxide in the outermost layer is composed of a region where the resistance reduction treatment is performed and a region where no potential application is performed,
Any of these may be used.

  Hereinafter, each process of the manufacturing method of the electronic device of this invention is demonstrated.

(substrate)
The substrate in the present invention is a substrate in which at least a part of the outermost layer is made of an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less.
The substrate is not particularly limited as long as at least a part of the outermost layer is made of the oxide, and may be a substrate made of the oxide (a form in which the substrate itself is the oxide) or a surface. The substrate (form which forms the said oxide layer as a surface layer on a board | substrate) provided with the layer (henceforth an "oxide layer") consisting of the said oxide as a layer may be sufficient.

As a substrate in a form in which the substrate itself is an oxide, a substrate composed of an oxide described later can be used.
Specific examples of the substrate in the form having an oxide layer as the surface layer include a glass substrate, a polyethylene naphthalate (PEN) substrate, a polyethylene terephthalate (PET) substrate, a polycarbonate (PC) substrate, and a polyimide (PI) substrate. A transparent film substrate, a YSZ substrate, a sapphire substrate, a Si substrate, a GaN substrate, an anodized aluminum substrate obtained by subjecting the surface of metal aluminum to wet anodizing treatment, or the like can be used.
In any case, the thickness of the substrate is preferably 0.1 to 10 mm, more preferably 0.15 to 1 mm, from the viewpoint of mechanical strength.

(Oxide)
The specific resistance of an oxide (or oxide layer) having a specific resistance of 1 × 10 ⁹ Ω · cm or less is preferably 1 × 10 ⁴ Ω · cm or less from the viewpoint of local antistaticity during potential application treatment. preferable.

Further, the method for forming the oxide layer on the substrate is not particularly limited, and the oxide layer can be formed by a known method such as sputtering, plasma CVD, PLD, vacuum deposition, or ion plating.
The layer thickness of the oxide layer is preferably 1 to 1000 nm, and more preferably 5 to 200 nm.

The oxide layer may be patterned by a known patterning method.
Known patterning methods include photoetching (a method of patterning by photolithography and etching), lift-off method (a method of performing resist pattern formation, film formation, and resist pattern removal in this order), and mask film formation method (a process through a mask). And a known method such as a membrane method).

Moreover, as a material of the oxide (or oxide layer) having a specific resistance of 1 × 10 ⁹ Ω · cm or less, In, Ga, Zn, Sn, Ti, from the viewpoint of more effectively obtaining the effect of reducing the resistance. , Ge, Sb, V, Nb, W, and an oxide containing at least one element of Ni are preferable.
Examples of the oxide containing at least one element of In, Ga, Zn, Sn, Ti, Ge, Sb, V, Nb, W, and Ni include, for example, ITO (indium tin oxide) and IZO (indium zinc oxide). ZnO (zinc oxide), IGZO (oxide semiconductor containing In, Ga, and Zn), IGMO (oxide semiconductor containing In, Ga, and Mg), TiO ₂ (titanium oxide, or a small amount of Nb) Titanium oxide), NiO (nickel oxide), WO ₃ (tungsten oxide) can be used.
The material of the oxide (or oxide layer) is preferably an oxide semiconductor (or oxide semiconductor layer) from the viewpoint of more effectively obtaining the effect of reducing resistance.
Therefore, the material of the oxide (or oxide layer) is preferably an oxide semiconductor (or oxide semiconductor layer) containing at least one element of In, Ga, and Zn. Specifically, ZnO or IGZO Is more preferable, and IGZO is particularly preferable.

The IGZO is generally a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO) (where a, b and c are a ≧ 0, b ≧ 0 and c ≧ 0, respectively). And a + b ≠ 0, b + c ≠ 0, c + a ≠ 0). The IGZO in the present invention may be a material system in the range of a, b, and c. From the viewpoint of etching characteristics and device characteristics, a is 0.4 to 0.9, and b is 0.1 to 0.1. The range of 0.6 and c is preferably 0.5 to 5.0, the range of a is 0.5 to 0.9, b is 0.1 to 0.5, and c is 0.5 to 1.0. More preferred.
The composition ratio of IGZO can be determined by RBS (Rutherford backscattering) analysis method, XRF (fluorescence X-ray analysis) or the like.

The IGZO film is preferably formed by vapor phase film formation using an IGZO polycrystalline sintered body as a target. Among the vapor phase film forming methods, the sputtering method and the pulse laser deposition method (PLD method) are more preferable, and the sputtering method is particularly preferable from the viewpoint of mass productivity.
Note that the sputtering method may be a co-sputtering method using a combination of an IGZO target, an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target.
Further, the formed IGZO film may be patterned by the patterning method described above.

<Low resistance treatment process>
The low resistance treatment process in the present invention is a process of reducing the specific resistance of the region by applying a potential higher than the potential of the substrate to a partial region or the entire region of the oxide.
Here, it is sufficient that the potential is applied so that the potential of the region where the resistance reduction treatment is performed is relatively higher than the potential other than the region where the resistance reduction processing is performed. It is not limited to a mode in which a positive potential is applied to a region to be processed. For example, a mode in which a ground potential (0 V) is applied to a region where the resistance reduction process is performed and a negative potential is applied in addition to the area where the resistance reduction process is performed is also included.

The difference (potential difference) between the potential of the region where the resistance reduction treatment is performed and the potential other than the region where the resistance reduction treatment is performed is 100 mV or more from the viewpoint of more effectively obtaining the effect of reducing the specific resistance. Preferably, 3000 mV or more is more preferable.
In addition, the potential application time is preferably 0.1 to 1000 seconds and more preferably 5 to 100 seconds per place.

As a method for applying a potential, for example, a potential applying electrode made of a conductive material (for example, a metal such as copper, tungsten, SUS, or a non-conductive material coated with conductive carbon) is used. A method in which the region for performing the resistance reduction treatment is opposed or brought into contact with the region is suitable.
Here, the facing or contacting is not particularly limited, but the closest distance between the potential applying electrode and the region where the resistance reduction treatment is performed is 0 nm to 20 nm (more preferably 0 nm to 10 nm). preferable.
There is no particular limitation on the potential application electrode. Even in the case of a needle-like electrode, an electrode having an area of 1 × 10 ⁻¹⁵ m ² or more facing or contacting the region to be subjected to the resistance reduction treatment (for example, Or a block-like electrode).
As the needle-like electrode, a probe of a scanning probe microscope (atomic force microscope (AFM), scanning tunneling microscope (STM), etc.) can be used. In the case of using a needle-like electrode, a potential is applied while sequentially scanning the needle-like electrode in the region where the resistance reduction process is performed.

On the other hand, the “electrode having an area of 1 × 10 ⁻¹⁵ m ² or more facing or contacting the region to be subjected to the resistance reduction treatment” is simultaneously applied to a wider area than the “needle-shaped electrode”. This is preferable in that a potential can be applied (that is, a potential can be applied without scanning the electrode (and even if scanning is performed with a small scanning distance)). By using such an electrode, it is possible to efficiently apply a potential and improve the throughput of manufacturing an electronic element.
The area of the electrode is preferably 1 × 10 ⁻⁶ m ² or more from the viewpoint of potential application efficiency.
From the viewpoint of potential application efficiency, it is also preferable to set the area of the portion facing or contacting the electrode to be the same as the area of the region where the resistance reduction treatment is performed.

In addition, a large number (for example, a density of 10 ⁴ / mm ² or more and 10 ¹⁰ / mm ² or less) of nanoscale or micrometer scale structures (for example, a diameter of 0.01) 10 μm and a needle-like structure having a length of 0.01 to 10 μm) may be provided (for example, Experimental Example 4 described later).
Furthermore, the region where these structures are provided is not necessarily a circular region as in Experimental Example 4 described later, and may be a polygonal region so as to be adapted to the device to be manufactured.
According to such a form, a potential can be applied more efficiently.
In this mode, for example, a mode in which a voltage is applied by setting the distance between the tip of the needle-like structure and the region to be subjected to the resistance reduction treatment to 0 nm to 20 nm (more preferably 0 nm to 10 nm) is preferable.

As a more preferable form of the potential application method in the low resistance treatment step, one potential application electrode (hereinafter also referred to as "one electrode") is opposed or brought into contact with the region for performing the low resistance treatment, In addition, the other electrode for potential application (hereinafter also referred to as “the other electrode”) is opposed to or in contact with at least one part of the substrate other than the region where the resistance reduction treatment is performed, and the one electrode is provided. On the other hand, a higher potential than that of the other electrode is applied.
As a more specific form of the potential application method,
(1) A positive potential is applied to the one electrode, and a negative potential, a ground potential (0 V), or a positive potential smaller than the potential applied to the one electrode is applied to the other electrode. Form,
(2) A mode in which a ground potential (0 V) is applied to the one electrode and a negative potential is applied to the other electrode,
Is mentioned.

There is no particular limitation on the atmosphere in which the low resistance treatment process is performed, but from the viewpoint of more effectively reducing the specific resistance of the region in which the low resistance treatment is performed, an atmosphere having a low oxygen partial pressure. (An atmosphere lower than 20% of the atmosphere), a reducing gas, and more preferably in an atmosphere containing moisture as required.
Examples of the reducing gas include hydrogen gas, argon gas, nitrogen gas, and foaming gas.

<High resistance treatment process>
In the method for manufacturing an electronic device of the present invention, the oxide in the outermost layer of the substrate may be applied to a second region other than the region where the resistance reduction treatment is performed, from a potential other than the second region of the oxide. Further, a high resistance treatment step for increasing the specific resistance of the second region by applying a low potential may be provided.
Here, it is sufficient that the potential is applied so that the potential of the second region is relatively lower than the potential of the oxide other than the second region, and negative potential is applied to the second region. There is no limitation to the form in which the potential is applied. For example, a form in which a ground potential (0 V) is applied to the second region and a positive potential is applied to other regions than the second region is also included.

  The reason why the specific resistance of the second region increases due to the high resistance treatment process is not clear, but it is assumed that the amount of oxygen deficiency in the oxide can be reduced by applying the potential as described above. Is done. However, the present invention is not limited by this cause.

The difference (potential difference) between the potential of the second region and the potential of the substrate other than the second region is preferably 100 mV or more, and more preferably 500 mV or more, from the viewpoint of the effect of increasing the specific resistance.
In addition, the potential application time is preferably 0.1 to 1000 seconds and more preferably 5 to 100 seconds per place.

As a method for applying a potential, for example, a method in which a potential applying electrode is opposed or brought into contact with the second region is suitable.
As the potential application electrode, an electrode having an area of 1 × 10 ⁻¹⁵ m ² or more is preferably used as a portion facing or in contact with the second region.
The preferred form of facing and contacting, the preferred form of the potential application electrode, the preferred range of the area of the electrode, and the like are the same as those in the low resistance treatment step described above.

As a more preferable form of the potential application method in the high resistance treatment process, one potential application electrode (one electrode) is opposed to or in contact with the second region, and other than the second region of the substrate. In this embodiment, the other potential application electrode (the other electrode) is opposed or brought into contact with at least one of the portions, and a potential lower than that of the other electrode is applied to the one electrode.
As a more specific form of the potential application method,
(1) A negative potential is applied to one electrode, and a positive potential, a ground potential (0V), or a negative potential greater than (i.e., close to 0V) applied to one electrode is applied to the other electrode. The form of potential,
(2) A configuration in which one electrode is set to a ground potential (0 V) and the other electrode is set to a positive potential.
Is mentioned.

In addition, the atmosphere in which the high-resistance treatment process is performed is not particularly limited, but from the viewpoint of more effectively increasing the specific resistance of the second region, the oxidizing gas and, if necessary, More preferably, it is performed in an atmosphere containing moisture.
Examples of the oxidizing gas include oxygen gas, ozone gas, nitrous oxide gas, and water vapor.

<Other processes>
The manufacturing method of the electronic device of the present invention may have other steps other than the above as necessary.
That is, in the electronic device manufacturing method of the present invention, at least a part of the target electronic device manufacturing process includes the low-resistance treatment process (and the high-resistance treatment process as necessary). In addition to these processes, a known electronic element manufacturing process (a film forming process, a patterning process, a cleaning process, a heat treatment process, etc.) may be included.

<Embodiment>
According to the method for manufacturing an electronic element substrate of the present invention, various electronic elements such as a thin film transistor, a capacitor, a high resistance element, and a striped electrode can be manufactured.
Hereinafter, specific embodiments of the method for manufacturing an electronic element substrate of the present invention will be described.

(Formation of source electrode and drain electrode of thin film transistor)
As a first embodiment, a source electrode and a drain electrode of a thin film transistor are formed by reducing the specific resistance of the first region in the resistance reduction treatment step.

Hereinafter, an example of the first embodiment will be described with reference to FIGS. 1A to 1D and FIG.
1A to 1D are manufacturing process diagrams conceptually showing a manufacturing method of a thin film transistor 100 as an example of the first embodiment, and FIG. 2 is a cross-sectional view taken along line AA of the thin film transistor 100 to be manufactured. FIG.

First, as shown in FIGS. 1A and 2, a substrate 10 provided with a patterned gate electrode 12 and a gate insulating film 14 is prepared.
The substrate 10 is as described above, and the preferred range is also the same.
1A to 1D, illustration of the substrate is omitted.

-Gate electrode-
The gate electrode 12 has conductivity and heat resistance (500 ° C. or higher), for example, Al, Mo, Cr, Ta, Ti, Au, Ag or other metals, Al—Nd, Ag—Pd—Cu, etc. And metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO).
As the gate electrode 12, these conductive films can be used as a single layer structure or a stacked structure of two or more layers.
In the formation of the gate electrode 12, first, for example, a wet method such as a printing method, a coating method, a physical method such as a vacuum deposition method, a sputtering method, an ion plating method, a chemical method such as CVD, plasma CVD method, The film is formed on the substrate 10 in accordance with a method appropriately selected in consideration of suitability with the material to be used. The thickness of the gate electrode 12 is preferably 10 nm to 1000 nm (more preferably 50 nm to 200 nm).
For example, a Mo film, an Al film, an Al—Nd film, or a stacked film thereof is formed by means such as sputtering.
After film formation, for example, patterning is performed in a predetermined shape by a patterning process.

−Gate insulation film−
After forming the gate electrode 12 on the substrate 10, the gate insulating film 14 is formed.
The gate insulating film 14 preferably has insulating properties and heat resistance (desirably 500 ° C. or higher). For example, SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , An insulating film such as HfO ₂ or an insulating film containing at least two of these compounds may be used.
The gate insulating film 14 is also used from a wet system such as a printing system and a coating system, a physical system such as a vacuum deposition method, a sputtering method, and an ion plating method, and a chemical system such as CVD and plasma CVD. A film is formed on the substrate 10 according to a method appropriately selected in consideration of suitability for the material. If necessary, patterning is performed in a predetermined shape by the patterning process described above.

The thickness of the gate insulating film 14 is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm from the viewpoints of reducing leakage current, improving voltage resistance, and reducing driving voltage.
As a specific example of the formation of the gate insulating film 14, there is a mode in which an insulating film such as silicon oxide (SiO ₂ or the like) or silicon nitride (SiN _x or the like) having a film thickness of 100 to 400 nm is formed by means such as sputtering or CVD. Is preferred.

-Active layer (semiconductor layer)-
After the gate insulating film 14 is formed, an oxide semiconductor layer 16 patterned into an island pattern is formed as shown in FIG. 1B (FIG. 1B).
The preferred embodiment of the oxide semiconductor layer 16 is as described above, and the preferred range is also the same. As the oxide semiconductor layer 16, for example, an amorphous IGZO layer or a ZnO layer can be used.
The film thickness of the oxide semiconductor layer 16 is, for example, 5 to 100 nm.

-Low resistance treatment process-
The resistance reduction process described above is performed on the formed oxide semiconductor layer 16 using a pair of block-shaped electrodes 30 (potential application electrodes having a flat portion) (FIG. 1C).
Specifically, as shown in FIG. 1C, a block electrode 30 is brought into contact with a first region (a region to be a source electrode 18S and a drain electrode 18D described later) on the surface of the oxide semiconductor layer 16, and The other electrode is brought into contact with one point P1 of the region other than the first region on the surface of the oxide semiconductor layer 16 to prepare for potential application. Each of the pair of block-shaped electrodes 30 is formed of a rectangular parallelepiped conductor (for example, a metal such as copper), and a certain one surface is opposed to or contacted with the object. On the other hand, it is configured so that a potential can be applied.
Next, a potential higher than that of the other electrodes is applied to the pair of block-shaped electrodes 30 (resistance reduction treatment). The pair of block electrodes 30 are at the same potential.
By this low resistance treatment, the specific resistance of the region (first region) in contact with the block electrode 30 on the surface of the oxide semiconductor layer 16 is lowered.

As described above, the oxide semiconductor film formed in the island pattern (that is, in the same oxide semiconductor region) is subjected to the low resistance treatment as the first region (the first region in which the specific resistance is reduced). Then, the source electrode 18S and the drain electrode 18D are formed (FIG. 1D). In the oxide semiconductor layer 16, the specific resistance of the region where the block electrode 30 is not in contact does not change, and the region between the source electrode 18S and the drain electrode 18D forms the channel portion 17 of the thin film transistor. In this manner, the channel portion, the source electrode, and the drain electrode are manufactured by a simple method without going through a photolithography process.
Through the above steps, the thin film transistor 100 is manufactured.

FIG. 2 is a cross-sectional view taken along line AA in FIG.
As shown in FIG. 2, the thin film transistor 100 includes a gate electrode 12, a gate insulating film 14, a source electrode 18 </ b> S, a drain electrode 18 </ b> D, and a channel portion 17 on a substrate 10.
The source electrode 18S, the drain electrode 18D, and the channel portion 17 are formed in the same layer (in the same oxide semiconductor region). Specifically, the oxide semiconductor layer is divided into a source electrode 18S, a drain electrode 18D, and a channel portion 17.
For this reason, the problem of interface contamination and the problem of parasitic capacitance when the channel portion and the source and drain electrodes are provided as separate layers are reduced.

As described above, an example of the first embodiment (formation in which a source electrode and a drain electrode of a thin film transistor are formed) has been described with reference to FIGS. 1 and 2. The first embodiment is illustrated in FIGS. 1 and 2. The examples are not limited.
For example, in the cross-sectional view of FIG. 2, the entire thickness of the oxide semiconductor layer is reduced to form the source electrode 18S and the drain electrode 18D. However, as shown in the cross-sectional view of FIG. 3, a form in which the resistance of the oxide semiconductor layer is partially reduced may be employed.

In addition, after forming the source electrode 18S and the drain electrode 18D in FIG. 1D, a protective film (SiO ₂ , SiN _x , SiON, organic insulating film, or the like) may be formed.
In the case where it is necessary to increase the resistance of the channel portion, a high resistance treatment step is provided before or after the low resistance treatment step in FIG. Also good.
In addition, a known process (a heat treatment process, various cleaning processes, a contact hole forming process, etc.) may be included as a manufacturing process of the thin film transistor.

In FIG. 1, the source electrode and the drain electrode are simultaneously formed by the resistance reduction process using a pair of block electrodes. However, the source electrode and the drain electrode are separately and independently formed by the independent resistance reduction process. (In other words, the timing may be shifted).
That is, the source electrode of the thin film transistor is formed by reducing the specific resistance of a partial region of the oxide, and the specific resistance of another region within the same oxide region (for example, within the same island pattern) is reduced. The drain electrode is not limited to a specific form as shown in FIG.

4 is a schematic plan view of the source electrode 18S, the drain electrode 18D, and the oxide semiconductor layer 16 of the thin film transistor formed in FIG. 1D as viewed from the film surface side.
A preferred form of the shape of the source electrode and the drain electrode is that the source electrode 18S is polygonal (but not limited to a square as shown in FIG. 4), and the drain electrode 18D is parallel to one side L1 of the source electrode 18S. It is a form that is a polygon (not limited to a quadrangle as in FIG. 4) having sides L2 facing each other with the same length.

In addition, by performing the low resistance treatment or the high resistance treatment on the region between the source electrode and the drain electrode, the ratio of the oxide portion in the region between the source electrode and the drain electrode The resistance may be adjusted to be an electron channel (for example, the electron channel 17A, 17B, or 17C shown in the schematic plan views of FIGS. 5, 6, and 7).
In this case, the specific resistance of the oxide (for example, the electron channel 17A, 17B, or 17C shown in FIGS. 5 to 7) in the region between the source electrode and the drain electrode is a place other than the source electrode and the drain electrode (for example, The specific resistance of the oxide semiconductor layer 16) in FIGS.

The first embodiment can be applied to the manufacture of a two-terminal semiconductor element and a capacitor in addition to the manufacture of a thin film transistor.
That is, a two-terminal semiconductor element can be manufactured in the same manner as the above thin film transistor except that no gate electrode is provided (that is, a substrate having no gate electrode is used).
A capacitor can be manufactured in the same manner as the above thin film transistor except that one block electrode is used instead of the pair of (two) block electrodes. In this case, the gate electrode in the thin film transistor constitutes the lower electrode of the capacitor, and the first region subjected to the resistance reduction treatment by one block electrode constitutes the upper electrode of the capacitor.

(Formation of capacitor electrodes)
As a second embodiment of the method for manufacturing an electronic element substrate of the present invention, there is an embodiment in which a capacitor electrode is manufactured by reducing the specific resistance of the first region in the low resistance treatment step.

Hereinafter, an example of the second embodiment will be described with reference to FIGS. 8A to 8E and FIG.
8A to 8E are manufacturing process diagrams conceptually showing a manufacturing method of the capacitor 200 as an example of the second embodiment, and FIG. 9 is a cross-sectional view taken along the line BB of the manufactured capacitor 200. FIG.

First, as shown in FIGS. 8A and 9, a substrate 110 provided with an insulating film 114 is prepared. In FIGS. 8A to 8E, illustration of the substrate is omitted.
Next, as illustrated in FIG. 8B, the oxide semiconductor layer 116 is formed over the insulating film 114.
Here, the substrate 110, the insulating film 114, and the oxide semiconductor layer 116 can have structures similar to those of the substrate 10, the gate insulating film 14, and the oxide semiconductor layer 16 in the thin film transistor 100.

-High resistance process-
The oxide semiconductor layer 116 thus formed is subjected to the above-described high resistance treatment using one block-shaped electrode 120 (potential application electrode having a flat portion) (FIG. 8C).
Specifically, as shown in FIG. 8C, one block electrode 120 is brought into contact with a second region (a region to be an insulating portion 117 to be described later) on the surface of the oxide semiconductor layer 16, and oxidation is performed. The other electrode is brought into contact with one point P2 of the region other than the second region on the surface of the physical semiconductor layer 116 to prepare for potential application. Here, the block electrode 120 is brought into contact with the oxide semiconductor layer 116 so as to be divided into two regions. Note that as the block electrode 120, the same structure as the block electrode 30 used for manufacturing the thin film transistor 100 can be used.
Next, a potential lower than that of the other electrodes is applied to the block electrode 120 (high resistance treatment).
By this high resistance treatment, the specific resistance of the second region (the region where the block electrode 120 is in contact) that divides the oxide semiconductor layer 116 into two regions is increased.

-Low resistance treatment process-
After the high resistance treatment process, the low resistance treatment process is subsequently performed (FIG. 8D).
Specifically, as shown in FIG. 8D, a first region on the surface of the oxide semiconductor layer 116 (each region of the oxide semiconductor layer 116 divided into two regions by the second region). A pair of block electrodes 130 are brought into contact with each other, and other electrodes are brought into contact with a region other than the first region (for example, the second region) on the surface of the oxide semiconductor layer 116 to prepare for potential application. Note that as the block electrode 130, the same structure as that of the block electrode 30 used for manufacturing the thin film transistor 100 can be used.
Next, a higher potential than the other electrodes is applied to the pair of block-shaped electrodes 130 (low resistance treatment). The pair of block electrodes 130 are at the same potential.
By this resistance reduction treatment, the specific resistance of the region (first region) in contact with the block electrode 130 in the surface of the oxide semiconductor layer 116 is decreased.

Through the above steps, the capacitor electrode 118 and the capacitor electrode 119 are formed in the oxide semiconductor film as the first region subjected to the resistance reduction treatment (FIG. 8E). On the other hand, an insulating portion 117 is formed between the capacitor electrode 118 and the capacitor electrode 119 as a second region subjected to the high resistance treatment.
In this manner, a pair of capacitor electrodes and an insulating portion existing between the capacitor electrodes are manufactured by a simple method without passing through a photolithography process.
As described above, the capacitor 200 is manufactured.

FIG. 9 is a cross-sectional view taken along the line BB in FIG.
As shown in FIG. 9, the capacitor 200 includes an insulating film 114, a pair of capacitor electrodes 118 and 119, and an insulating portion 117 existing between the electrodes on the substrate 110.
The pair of capacitor electrodes 118 and 119 and the insulating portion 117 existing between the electrodes are formed in the same layer (oxide semiconductor layer). Specifically, the oxide semiconductor layer is divided into a capacitor electrode 118, a capacitor electrode 119, and an insulating portion 117.
For this reason, the problem of interface contamination caused by the conventional provision of the capacitor electrode and the insulating portion as separate layers is reduced.

As described above, the example of the second embodiment (form for forming the electrode of the capacitor) has been described with reference to FIGS. 8 and 9. However, the second embodiment is limited to the example shown in FIGS. It will never be done.
For example, the high resistance process can be omitted, and the capacitor can be formed only by forming the capacitor electrode 118 and the capacitor electrode 119 in the oxide semiconductor layer 116 by the low resistance process.
That is, the second embodiment reduces the specific resistance of two regions of the oxide in the low resistance treatment process, and further, if necessary, in the same oxide region (for example, the same island) in the high resistance treatment process. There is no particular limitation as long as it is a method for forming a capacitor by increasing the specific resistance of the region between the two regions in the pattern).
In addition, a known process (heat treatment process, various cleaning processes, etc.) may be included as a capacitor manufacturing process.

(Striped electrode formation)
As a third embodiment, there is an embodiment in which a striped electrode is formed by reducing the specific resistance of the first region in the low resistance treatment step.
FIG. 10 is a manufacturing process diagram conceptually showing an example of the third embodiment.

Hereinafter, an example of the third embodiment will be described with reference to FIGS.
FIGS. 10A to 10C are manufacturing process diagrams conceptually showing a method of manufacturing the substrate 300 with stripe electrodes, which is an example of the third embodiment.

First, a substrate 210 is prepared as shown in FIG.
Next, as illustrated in FIG. 10B, the oxide semiconductor layer 216 is formed over the substrate 210.
Here, the substrate 210 and the oxide semiconductor layer 216 can have a structure similar to that of the substrate 10 and the oxide semiconductor layer 16 in the thin film transistor 100 except that the oxide semiconductor layer is not patterned.

-Low resistance treatment process-
The resistance reduction process described above is performed on the formed oxide semiconductor layer 216 using the multi-probe electrode 230 (FIG. 10C).
Here, as shown in FIG. 10C, the multi-probe electrode 230 includes a plurality of needle-like electrodes arranged in a line.
Specifically, in the low resistance treatment process, the surface of the oxide semiconductor layer 216 is brought into contact with the tip of each needle electrode of the multi-probe electrode 230, and a potential is applied while scanning the entire multi-probe electrode 230 in the direction of arrow S. I do. At this time, a potential higher than that of the oxide semiconductor layer 216 is applied to each needle electrode tip.
Thus, a stripe-shaped low resistance region (stripe electrode 218) is formed over the oxide semiconductor layer 216. In this way, a striped electrode is produced by a simple method without going through a photolithography process.

FIG. 10C shows an example in which a positive potential is applied to all needle-like electrodes, but the third embodiment is not limited to this example. For example, by changing the polarity of the potential applied to adjacent needle electrodes (that is, applying a negative potential to the needle electrode adjacent to the needle electrode to which a positive potential is applied), It is also possible to form striped electrodes in which high resistance regions are alternately arranged.
In addition, a striped electrode in which low resistance regions and high resistance regions are alternately arranged can be formed by performing a high resistance processing step using a multi-probe electrode before or after the low resistance processing step. Can do.
That is, in the third embodiment, the specific resistance of the plurality of regions of the oxide is reduced in the low resistance treatment step, and further, in the high resistance treatment step, another plurality of different oxides in the same oxide region are provided as necessary. There is no particular limitation as long as the striped electrode is formed by increasing the specific resistance of the region.

The substrate with striped electrodes formed as described above can be used as a substrate for a passive matrix (simple matrix) display device.
That is, two substrates with stripe electrodes are prepared, the stripe electrodes are bonded so as to be orthogonal to each other (crossed Nicols), and a liquid crystal is interposed therebetween, whereby a passive matrix liquid crystal display device can be obtained.

(Formation of a pair of comb electrodes)
As a fourth embodiment, the specific resistance of the paired comb-shaped region of the oxide is reduced in the low resistance treatment step, and the combs in the same oxide region are further reduced in the high resistance treatment step as necessary. A mode in which a pair of comb-shaped electrodes is formed by increasing the specific resistance of the region between the mold regions is exemplified.
FIG. 11 is a schematic plan view showing a pair of comb-shaped electrodes.
As shown in FIG. 11, the comb-shaped electrode 318 and the comb-shaped electrode 319 formed by the resistance reduction treatment are arranged in the oxide semiconductor layer 316 (in the same oxide semiconductor portion) so as to be engaged with each other. Yes (but they are not in contact).
As necessary, the specific resistance of the region 317 between the comb-shaped regions and the region around the electrode in the oxide semiconductor layer 316 may be increased by high resistance treatment.
The pair of comb-shaped electrodes described above can be used as, for example, an electrode of an electronic element or a capacitor.

(Treatment method using pattern electrode)
As a fifth embodiment, there is a method of forming at least a low resistance pattern (and a high resistance pattern as necessary) in an oxide semiconductor layer by using a pattern electrode.
An example of the fifth embodiment will be described with reference to FIGS.

FIG. 12A is a schematic plan view illustrating an example of a pattern electrode used in the fifth embodiment, and FIG. 12B is a cross-sectional view taken along line AA in FIG.
In the pattern electrode 420 shown in FIG. 12, convex portions 422 having a square pattern are arranged in a lattice pattern.
The convex portion 422 can be a square having a side of 3 μm, for example. Further, the interval S between the convex portions 422 (the closest distance between the convex portions 422) can be set to 6 μm, for example. The height h of the convex portion 422 can be set to 100 nm, for example.
However, the specific dimensions described above are merely examples, and there are no particular limitations as long as they are nano or micrometer scales. Also, the shape of the pattern is not limited to a square, and can be any shape such as a polygon, a circle, an ellipse, and an indefinite shape.

FIG. 13 is a schematic cross-sectional view showing an example of applying a potential to an oxide layer using a pattern electrode, and FIG. 14 shows a low resistance pattern region and a high resistance pattern region formed using the pattern electrode. It is a schematic sectional drawing which shows an example.
As shown in FIG. 13, the lower electrode 430 provided with the oxide semiconductor layer 440 is prepared, the convex portion of the pattern electrode 420 is pressed against the oxide semiconductor layer 440, and a partial region of the oxide semiconductor layer 440 is formed. By applying a potential higher than that of the lower electrode 430, the low resistance pattern region 442 illustrated in FIG. 14 can be formed in the oxide semiconductor layer (low resistance treatment).
Further, the convex portion 422 of the pattern electrode 420 is pressed against the oxide semiconductor layer 440, and a potential lower than that of the lower electrode 430 is applied to a partial region of the oxide semiconductor layer 440, whereby the oxide semiconductor layer is subjected to FIG. It is also possible to form a high resistance pattern region 446 shown in FIG.
As illustrated in FIG. 14, the oxide semiconductor layer 440 may include a region 444 having a resistance between the low resistance pattern region and the high resistance pattern region as a region where no potential application is performed. .
In the low resistance treatment (and the high resistance treatment used as necessary), an operation of pressing the pattern electrode 420 against the oxide semiconductor layer while moving the pattern electrode 420 in the XY direction in a plane parallel to the oxide semiconductor layer; By repeating the operation of applying a potential, a periodic low resistance pattern region (and a high resistance pattern region as necessary) can be formed in a wide region of the oxide semiconductor layer.

  EXAMPLES Hereinafter, although an Example demonstrates this invention further more concretely, this invention is not limited to a following example.

[Experimental Example 1]
As Experimental Example 1, experiments related to the low resistance treatment process and the high resistance treatment process were performed.
<Preparation of thin film sample>
A thin film sample having the structure shown in FIG. 15A was produced as follows.
That is, an Au film having a thickness of 200 nm was formed on a quartz glass substrate by vacuum deposition. The formed Au film is a film for applying a potential to the following IGZO film.
A 100 nm thick IGZO (In: Ga: Zn = 1.5: 0.5: 1) film is exposed on this Au film by sputtering using a metal mask so that a part of the underlying Au film is exposed. A thin film sample was formed in a pattern.
When the specific resistance of the IGZO film was measured using Resitest8300 manufactured by Toyo Technica, it was 2.78 × 10 ⁻³ Ω · cm.

<Low resistance treatment>
Next, as shown in FIG. 15B, a needle probe was brought into contact with the Au film portion of the thin film sample, and an atomic force microscope probe (conductive diamond coat) was brought into contact with the IGZO film.
Next, the probe was grounded (0 V), and the surface was scanned in a line with the probe while applying a negative bias (-4000 mV) to the Au portion with the needle probe (resistance reduction treatment).

<High resistance treatment>
Next, as shown in FIG. 15C, a needle probe is brought into contact with the Au film portion of the thin film sample, and the atomic force microscope is placed at a location different from the location where the resistance reduction treatment of the IGZO film is performed. The probe was brought into contact.
Next, the probe was grounded (0 V), and the surface was scanned in a line with the probe while applying a positive bias (+1000 mV) to the Au portion with the needle probe (high resistance treatment).

<Current mapping>
Next, as shown in FIG. 15D, the needle probe was brought into contact with the Au film portion of the thin film sample, and the probe of the atomic force microscope was brought into contact with the IGZO film.
The probe was grounded (0 V), and current mapping was performed while applying a positive bias (+50 mV) to the Au portion with the needle probe.
Here, current mapping was performed using Nano-R manufactured by Pacific Nanotechnology.

FIG. 16 shows a current mapping image.
In FIG. 16, the bright line portion on the left side (in the region (B)) is a trace of scanning the surface with a probe in the resistance reduction process, and the dark line portion on the right side (in the region (C)) This is a trace of scanning the surface in a line shape with a probe in the high resistance treatment.
In FIG. 16, the bright line indicates a region where the specific resistance is lower than the background, and the dark line indicates a region where the specific resistance is higher than the background.
As shown in FIG. 16, by setting the potential of the first region (the bright line portion in FIG. 16) on the surface of the IGZO film higher than the potential other than the first region, It was confirmed that the specific resistance can be reduced.
Furthermore, the specific resistance of the second region is increased by lowering the potential of the second region (dark line portion in FIG. 16) of the IGZO film surface lower than the potential other than the second region. It was confirmed that

<Confirmation of resistance value change>
Next, the relationship between the applied voltage (applied potential) to the needle probe and the resistance value of the IGZO film was investigated using Nano-R manufactured by Pacific Nanotechnology.
FIG. 17 is a graph showing the relationship between the applied voltage (applied potential) to the needle probe and the resistance value of the IGZO film.
In FIG. 17, regarding the value of the resistance value [Ω], the symbol “E” indicates that the following value is a “power index” with 10 as the base, and “E” and “power index” ”. The numerical value represented by “E” is multiplied by the numerical value before “E”. For example, the notation “1.0E + 08” indicates “1.0 × 10 ⁸ ”.
As shown in FIG. 17, when the applied potential is set to −4000 mV (that is, the resistance reduction treatment is performed), the resistance of the IGZO film is actually compared with the applied potential of 0 mV (that is, untreated). The value was decreasing.
On the other hand, the resistance value of the IGZO film actually increased when the applied potential was +1000 mV (i.e., the high resistance treatment was performed) compared to the applied potential of 0 mV (i.e., untreated). .

[Experimental example 2]
Experiments for resistance reduction and resistance increase were performed in the same manner as in Experiment 1 except that the IGZO film in Experiment 1 was changed to various films shown in Table 1 below.
The evaluation results of the IGZO film of Experimental Example 1 are also shown, and the evaluation results are shown in Table 1 below.

In Table 1, “conductor” refers to a state of less than 1.0 × 10 ⁻³ Ω · cm, and “semiconductor” refers to a specific resistance of 1.0 × 10 ⁻³ Ω · cm to 1 × 10 ⁹ Ω · cm. The following states are indicated, and “insulator” indicates a state where the specific resistance is greater than 1.0 × 10 ⁹ Ω · cm.

As shown in Table 1, in an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less, a potential (0 V) higher than a potential (−4000 mV) other than the first region is applied to the first region. It was confirmed that the specific resistance of the first region can be reduced by the processing (resistance reduction processing).
Further, in the case of an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less, a treatment (high resistance treatment) in which a potential (0 V) lower than a potential (+1000 mV) other than the second region is applied to the second region. ), It was also confirmed that the specific resistance of the second region can be increased.
Therefore, at least two types of specific resistance regions (for example, a high resistance region, a low resistance region, and an intermediate resistance) are formed on the oxide film by at least a low resistance treatment (and a high resistance treatment if necessary). It was confirmed that a variety of electronic devices can be manufactured by forming an electric resistance pattern with an arbitrary design.

[Experimental Example 3]
As Experimental Example 3 (reference experiment), an experiment was performed in which a larger area than Experimental Example 1 was subjected to high resistance treatment.
First, a thin film sample having the structure shown in FIG.
That is, an IGZO film having a thickness of 100 nm similar to that of Experimental Example 1 was formed on a quartz glass substrate to obtain a thin film sample.

Next, as shown in FIG. 18B, a needle probe was brought into contact with one part of the IGZO film, and a probe (conductive diamond coat) of an atomic force microscope was brought into contact with another part.
Next, the probe was grounded (0 V), and a 5 μm square region on the surface was scanned with the probe while applying a positive bias (+5000 mV) to the needle probe (high resistance treatment).

Next, the bias of the needle probe was set to +500 mV, and a 10 μm square region (a region including a 5 μm square region subjected to high resistance treatment) was scanned with a probe while measuring the current value (current mapping).
Further, the surface of the IGZO film subjected to the high resistance treatment was observed with an atomic force microscope (AFM) and a scanning electron microscope (SEM).

19A is an AFM toppo image, FIG. 19B is an AFM bird's eye view, and FIG. 19C is a current mapping image.
FIG. 20 is an SEM image.

As shown in FIG. 19C, in the 5 μm square region scanned by the probe, the specific resistance increased uniformly over the entire region.
From this result, for example, by making the flat part of the block-like electrode having a flat part of 5 μm square face or contact an oxide surface such as IGZO, a region of 5 μm square can be efficiently obtained (without scanning the electrode). It is considered that the specific resistance can be increased.
Furthermore, as in the case of the high resistance treatment, even in the low resistance treatment, the flat portion of the block-like electrode having a flat portion can be efficiently (electrode) by facing or contacting an oxide surface such as IGZO. It is believed that the specific resistance can be reduced (without scanning the

[Experimental Example 4]
As an example of an electrode used for the low resistance treatment or the high resistance treatment, an electrode having a large number of nanoscale or micrometer scale structures on the surface opposed to the oxide surface to be subjected to these treatments was manufactured. .
The structure of the fabricated electrode is a structure in which ZnO nanorods (structures) are densely grown in a pattern on the GaN substrate surface (electrode surface). By using such an electrode, the resistance reduction process or the resistance increase process can be performed more efficiently.
FIG. 21 is an SEM photograph obtained by photographing the produced electrode at a magnification of 3000 times, and FIG. 22 is an SEM photograph obtained by photographing the same electrode at a magnification of 10,000 times.
As shown in FIGS. 21 and 22, ZnO nanorods having a diameter of about several tens of nanometers and a length of about 2 μm are densely grown in a plurality of circular patterns (circular patterns having a diameter of 6.5 μm) on the surface of the GaN substrate. .

The electrode having the ZnO nanorods on the GaN substrate was produced as follows.
First, a plurality of circular patterns with a diameter of 6.5 μm (portions where the resist was removed) were formed on a GaN substrate coated with a resist by photolithography. Next, Au was deposited in a thickness of 3 nm by vacuum deposition, and then lifted off to form a plurality of Au circular patterns having a diameter of 6.5 μm and a thickness of 3 nm on the GaN substrate.
Next, after the GaN substrate provided with the Au pattern was baked at 1000 ° C. for 10 minutes in a nitrogen atmosphere, ZnO nanorods were grown on the Au pattern portion by a chemical vapor transport method. The experimental procedure for chemical vapor transport is as follows.
First, a mixed powder of ZnO and C (molar ratio 1: 1) as a material was placed on an alumina boat and installed at one end of a quartz glass tube open at both ends, and the above-mentioned position was about 30 cm away from the alumina boat. A GaN substrate was installed. Next, this quartz glass tube was inserted into a horizontal CVD apparatus (manufactured by Flap Technology Co., Ltd.), and argon and oxygen (1%) were allowed to flow, and a vacuum was drawn with a rotary pump (total pressure 0.3 kPa). For 1 hour. Then, after naturally cooling, the GaN substrate was taken out.
When the nanorod forming surface side of the extracted GaN substrate was observed with an SEM, ZnO nanorods shown in FIGS. 21 and 22 were confirmed.

10, 110, 210 Substrate 12 Gate electrode 14 Gate insulating films 16, 116, 216 Oxide semiconductor layer 17 Channel portion 18S Source electrode 18D Drain electrodes 30, 120, 130 Block electrode 100 Thin film transistor 114 Insulating film 117 Insulating portion 118 For capacitor Electrode 119 Capacitor electrode 200 Capacitor 218 Striped electrode 230 Multi-probe electrode 300 Substrate with striped electrode

Claims (20)

By applying a potential higher than the potential of the substrate to a partial region or the entire region of the oxide in a substrate in which at least a part of the outermost layer is made of an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less. A method for manufacturing an electronic element substrate, comprising a resistance reduction process for reducing the specific resistance of the partial region or the entire region. At least a part of the outermost layer is higher than the potential of the oxide other than the first region with respect to the first region of the oxide in the substrate made of an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less. A resistance reduction treatment step of reducing the specific resistance of the first region by applying a potential;
The specific resistance of the second region is increased by applying a potential lower than the potential of the oxide other than the second region to the second region of the oxide other than the first region. A high resistance treatment process,
Have
The manufacturing method of the electronic element substrate which has at least 2 types of area | regions, a low resistance area | region and a high resistance area | region, in the same area | region of the said oxide.   The method for manufacturing an electronic element substrate according to claim 1, wherein there is a region where no potential is applied in the same region of the oxide.   The oxide is an oxide semiconductor containing at least one element of In, Ga, Zn, Sn, Ti, Ge, Sb, V, Nb, W, and Ni. The manufacturing method of the electronic element board | substrate of 1 item | term. The oxide _{is, a (In 2 O 3)} · b (Ga 2 O 3) · c production of electronic device substrate according to any one of claims 1 to 4 is made of a (ZnO) Method.
(Here, a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0, respectively.)   The electronic device according to any one of claims 1 to 5, wherein the application of the potential in the resistance reduction treatment step is performed by causing an electrode made of a conductive material to face or contact the oxide. A method for manufacturing a substrate. The method of manufacturing an electronic element substrate according to claim 6, wherein the electrode used in the low resistance treatment step has an area of a portion facing or contacting the oxide of 1 × 10 ⁻¹⁵ m ² or more.   8. The electronic device substrate according to claim 6 or 7, wherein the electrode used in the low resistance treatment step is provided with a number of nanoscale or micrometer scale structures in a portion facing the oxide. Method.   The electronic device according to any one of claims 2 to 8, wherein the application of the potential in the high resistance treatment process is performed by causing the electrode made of a conductive material to face or contact the oxide. A method for manufacturing a substrate. 10. The method of manufacturing an electronic element substrate according to claim 9, wherein the electrode used in the high resistance treatment step has an area of a portion facing or contacting the oxide of 1 × 10 ⁻¹⁵ m ² or more.   11. The electronic device substrate according to claim 9, wherein the electrode used in the high resistance treatment process is provided with a large number of nanoscale or micrometer scale structures in a portion facing or contacting the oxide. Manufacturing method.   In the low resistance treatment step, by forming a source electrode of the thin film transistor by reducing a specific resistance of a partial region of the oxide, and by reducing a specific resistance of another region in the same oxide region The method for manufacturing an electronic element substrate according to claim 1, wherein a drain electrode is formed.   In the low resistance treatment step, the polygonal source electrode of the thin film transistor is formed by lowering the specific resistance of the partial region of the oxide, and the specific resistance of another region within the same oxide portion is lowered. The method of manufacturing an electronic element substrate according to claim 1, wherein a polygonal drain electrode having sides that are parallel to and have the same length as one side of the source electrode is formed. .   The region between the source electrode and the drain electrode is oxidized by subjecting the region between the source electrode and the drain electrode to the low resistance treatment step or the high resistance treatment step. The method for manufacturing an electronic element substrate according to claim 12 or 13, wherein a specific resistance of an object part is adjusted to form an electronic channel.   In the low resistance treatment step, the specific resistance of the two regions of the oxide is reduced, and if necessary, the region between the two regions in the same oxide region in the high resistance treatment step. The method for manufacturing an electronic element substrate according to claim 1, wherein a capacitor is formed by increasing a specific resistance.   The specific resistance of the pair of comb-shaped regions of the oxide is reduced in the low-resistance treatment step, and further, if necessary, between the comb-shaped regions in the same oxide portion in the high-resistance treatment step. The method for manufacturing an electronic element substrate according to claim 1, wherein a pair of comb-shaped electrodes is formed by increasing a specific resistance of the region.   In the low resistance treatment step, the specific resistance of the plurality of regions of the oxide is reduced, and further, in the high resistance treatment step, the specific resistance of another plurality of regions in the same oxide region is increased as necessary. The manufacturing method of the electronic element board | substrate of any one of Claims 1-11 which forms a striped electrode by this. At least a part of the outermost layer has a low resistance region having a low specific resistance, a high resistance region having a high specific resistance, and the low resistance in the same oxide portion of the substrate having an oxide having a specific resistance of 1 × 10 ⁹ Ω · cm or less. An electronic element substrate having at least three types of regions having a specific resistance intermediate between a resistance region and the high resistance region.   The electronic device substrate according to claim 18, wherein the oxide is an oxide semiconductor containing at least one element of In, Ga, Zn, Sn, Ti, Ge, Sb, V, Nb, W, and Ni. The electronic element substrate according to claim 18 or 19, wherein the oxide is made of a (In ₂ O ₃ ) · b (Ga ₂ O ₃ ) · c (ZnO).
(Here, a, b, and c are a ≧ 0, b ≧ 0, c ≧ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0, respectively.)