JP5353009B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP5353009B2
JP5353009B2 JP2008001670A JP2008001670A JP5353009B2 JP 5353009 B2 JP5353009 B2 JP 5353009B2 JP 2008001670 A JP2008001670 A JP 2008001670A JP 2008001670 A JP2008001670 A JP 2008001670A JP 5353009 B2 JP5353009 B2 JP 5353009B2
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graphene sheet
semiconductor device
film pattern
catalyst film
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JP2009164432A (en
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祐二 粟野
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富士通株式会社
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<P>PROBLEM TO BE SOLVED: To improve properties while advancing ultra-fine characteristics in a method of manufacturing a semiconductor apparatus, a semiconductor apparatus and a wiring structure. <P>SOLUTION: A graphene sheet 13 is grown on the surface (111) of a catalyst film pattern 12, thereby forming the catalyst film pattern 12 in a desired location, in a desired shape and with a desired crystal orientation. Thus, the graphene sheet 13 is obtained in the desired location, in the desired shape and with desired electrical conductivity. Therefore, as the catalyst film pattern 12 is formed in the channel portion of a semiconductor apparatus 10, the graphene sheet 13 is formed in the channel portion. While achieving the ultra-fine characteristics of the semiconductor apparatus 10, speed acceleration is attained, and the semiconductor apparatus 10 with improved properties is obtained. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

The present invention relates to a manufacturing method and a semiconductor equipment of a semiconductor device, particularly relates to the manufacturing method and a semiconductor equipment of a semiconductor device using a carbon structure.

  Semiconductor technology has been miniaturized according to Moore's law, and performance has been improved. However, this law also shows the limit of miniaturization of silicon (Si) and copper (Cu) instead of wiring in the transistor. In addition, research and research on alternative materials are being actively conducted.

  Attention has been focused on carbon nanotubes (CNT) as an alternative material. The CNT has a planar structure in which carbon (C) atoms are connected in a hexagonal shape, and is composed of a chemically stable graphene sheet wound in a cylindrical shape. Since this CNT has characteristics such as ballistic conduction characteristics and resistance to large current density, it has been expected to be applied to transistor channels and wiring structures (see, for example, Patent Document 1). However, there is a problem that it is difficult to form a large number of CNTs at a desired position in a desired direction.

Therefore, in place of CNT, similar to CNT, it has been proposed to apply a graphene sheet having excellent characteristics such as ballistic conduction characteristics and resistance to large current density and constituting CNT. For example, conventionally known graphite in which graphene sheets are laminated in multiple layers has an electrical metallic property. Recently, there has been a report that a transistor having a channel of several layers of graphene sheets of five or less layers is manufactured (see Non-Patent Document 1). According to this, even though graphite is a metal, when the number of layers is small, it has been confirmed that the conductivity can be modulated by applying an electric field, that is, the transistor operates. In addition, theoretical calculations predict that graphene sheet carriers have a long mean free path and that high mobility, ballistic conduction, and high-speed carrier transport can be obtained.
JP 2004-71654 A KS Novoselov, AK Geim, SV Morozov, D. Jiang, MI Katsnelson, IV Grigorieva, SV Dubonos, and AA Firsov, "Two-dimensional gas of massless Dirac fermions in graphene", Nature, 438, 2005, p.197.

However, it is difficult to form a graphene sheet in a desired size at a desired location, and it has not been realized yet.
The present invention has been made in view of these points, and an object thereof is to provide a manufacturing method and a semiconductor equipment of the semiconductor device while miniaturized, improving the properties.

In the present invention, in order to solve the above problem, as shown in FIG. 1, a catalyst film pattern 12 having a (111) surface of a transition metal is formed on a substrate 11, and a graphene sheet 13 is grown from the catalyst film pattern 12. The manufacturing of the semiconductor device 10, comprising: a step, a step of forming source / drain electrode portions 15 and 14 on both ends of the graphene sheet 13, and a step of forming the gate electrode portion 16 on the graphene sheet 13. A method is provided.

According to such a method for manufacturing a semiconductor device, the catalyst film pattern of the (111) plane of the transition metal whose shape and crystal orientation are controlled is formed at a desired location, and in the channel portion of the semiconductor device, By forming this catalyst film pattern, a graphene sheet having a desired shape and conductivity can be formed.

In the present invention, in order to solve the above-described problem, an imprint mask is imprinted on another graphene sheet grown from a catalyst film pattern on the (111) surface of a transition metal, and the another graphene is formed along the imprint mask. Forming a graphene sheet cut out from the sheet on a substrate, forming a source / drain electrode part on both ends of the graphene sheet, and forming a gate electrode part on the graphene sheet. A method for manufacturing a semiconductor device is provided.

According to such a method of manufacturing a semiconductor device, a graphene sheet is cut out in a desired shape from another graphene sheet grown from the catalyst film pattern on the (111) plane of the transition metal whose crystal orientation is controlled. A graphene sheet can be formed in a channel portion of a semiconductor device.

In the present invention, in order to solve the above problems, a channel portion on a substrate, source / drain electrode portions formed on the substrate on both sides of the channel portion, and a gate electrode portion formed on the channel portion. The channel part has a graphene sheet grown on the (111) plane of the catalyst film pattern separated by the insulating separation film .

According to such a semiconductor device, the graphene sheet grown on the (111) plane of the catalyst film pattern surface separated by the insulating separation film is formed in the channel portion of the semiconductor device, and the characteristics are improved. An improved semiconductor device can be obtained.

In the present invention, the shape, since the catalyst layer pattern (111) plane of the transition metal crystal orientation is controlled has to be formed at a desired location, the channel portion of the semiconductor device, the transition metal (111) A graphene sheet having a desired shape and electrical conductivity was formed using the catalyst film pattern on the surface . As a result, it is possible to obtain a semiconductor device that can be speeded up while improving the miniaturization of the semiconductor device and has improved characteristics.

  Hereinafter, as an embodiment of the present invention, an outline of the present invention will be described with reference to the drawings, followed by an embodiment based on the outline of the present invention. However, the technical scope of the present invention is not limited to these embodiments.

The outline of the present invention will be described below with reference to FIG.
1A and 1B show an outline of a semiconductor device according to the present invention, in which FIG. 1A is a schematic cross-sectional view, and FIG. 1B is an enlarged schematic plan view of a main part of a channel portion.

  As shown in FIG. 1A, the semiconductor device 10 forms a catalyst film (not shown) on a substrate 11 to form a catalyst film pattern 12, and a graphene sheet 13 is formed on the catalyst film pattern 12. Growing up. Instead of the catalyst film pattern 12, a laminated film of a catalyst film pattern and a metal base film pattern may be used. Further, a drain electrode portion 14 and a source electrode portion 15 are formed on the substrate 11 on both sides of the graphene sheet 13, and a gate insulating film (not shown) and a gate electrode (not shown) are formed on the graphene sheet 13. An electrode portion 16 is formed. In this case, for example, when the source electrode unit 15 is n-type and the drain electrode unit 14 is p-type, the semiconductor device 10 applies a voltage to the source electrode unit 15, the drain electrode unit 14, and the gate electrode unit 16. Electrons flow from the source electrode portion 15 to the drain electrode portion 14 through the graphene sheet 13.

  Next, a film forming method of the graphene sheet 13 will be described with reference to an enlarged schematic diagram 10a of FIG. Regarding the growth of the graphene sheet 13, molecular dynamics calculation was performed to analyze the behavior of atoms contributing to the growth. Below, it demonstrates based on the molecular dynamics calculation result. Further, in the enlarged schematic diagram 10a, a triangular lattice having a nickel (Ni) atom constituting the catalyst film pattern 12 as a vertex is represented by a broken line, and a hexagon having a C atom constituting the graphene sheet 13 as a vertex is schematically represented by a solid line. Show. In addition, Ni atoms and C atoms actually exist at the apexes of the triangular lattice and the hexagon, but the illustration is omitted in the enlarged schematic diagram 10a.

First, a catalyst film pattern 12 is formed by forming a crystal film of a transition metal element, for example, a Ni (001) plane as a catalyst film. Then, C atoms were supplied to the Ni (001) surface by a mixed gas of acetylene (C 2 H 2 ) and argon (Ar) at a temperature of 600 ° C. and a pressure of 1 kPa. Then, the Ni surface is rearranged from the (001) plane to the (111) plane. As shown in FIG. 1B, a triangular lattice having Ni atoms as vertices is formed on the Ni (111) plane. And the supplied C atom is arrange | positioned just above the gravity center of each triangle comprised from Ni atom. By arranging the C atom directly above the center of gravity of the triangle, a hexagon having the C atom as a vertex is formed, and these are combined with each other, whereby the hexagonal structure of the graphene sheet 13 is formed.

  Based on the growth principle of the graphene sheet 13, the graphene sheet 13 can be deposited and formed in a similar pattern shape from the catalyst film pattern 12 on the (111) plane of the transition metal. Further, it is known that the electrical conductivity of the graphene sheet 13 changes depending on the direction of the hexagonal current. Therefore, according to the pattern direction of the catalyst film pattern 12, the direction of the graphene sheet 13 can be controlled to determine the direction of the current, and as described in Non-Patent Document 1, the number of layers of the graphene sheet 13 is controlled. As a result, the electronic state (metallic or semiconducting) of the graphene sheet 13 can be controlled. Note that the direction of the pattern of the catalyst film pattern 12 can also be controlled by a fine lithography technique such as an electron beam or AFM (Atomic Force Microscope), and further, a line shape formed on the surface of the substrate 11 by using an off-substrate. It is also possible to control by using the crystal structure step.

  As described above, since the graphene sheet can be grown on the (111) plane of the catalyst film pattern, the catalyst film pattern is formed in a desired place by controlling the shape and crystal orientation, thereby obtaining a desired shape and a desired shape. A graphene sheet having a crystal orientation and desired electrical conductivity can be obtained at a desired location. Therefore, when the catalyst film pattern is formed in the channel portion of the semiconductor device, a graphene sheet can be formed in the channel portion, the semiconductor device can be increased in speed while being miniaturized, and a semiconductor device with improved characteristics can be obtained. . It is conceivable to apply such a catalyst film pattern to a wiring structure of a semiconductor device or other electronic devices in addition to the channel portion of the semiconductor device. In this case, it is possible to increase the speed of signals and the like. .

  Next, embodiments will be described. In the embodiment, a semiconductor device based on the outline of the present invention will be described as a first embodiment, and then a wiring structure using the present invention will be described as a second embodiment.

First, a first embodiment will be described with reference to the drawings. In the first embodiment, the case of a semiconductor device based on the outline of the present invention is taken as an example, and two examples will be described.
(Example 1-1)
In Example 1-1, the case of a semiconductor device in which a catalyst film pattern is left is described as an example.

  2A and 2B show the semiconductor device according to the first embodiment. FIG. 2A is a schematic cross-sectional view, and FIG. 2B is a schematic plan view. In FIG. 2B, part of the gate insulating film 36a and the gate electrode 36 is intentionally removed and displayed so that the graphene sheet 33 and the channel portion of the catalyst film pattern 32 can be seen.

  In the semiconductor device 30, the catalyst film pattern 32 separated by the insulating separation film 32 a is formed on the insulating substrate 31, and the graphene sheet 33 is grown on the catalyst film pattern 32. Further, the drain electrode 34 and the source electrode 35 are formed on the substrate 31 on both sides of the graphene sheet 33, and the gate electrode 36 is formed on the graphene sheet 33 via the gate insulating film 36a. In this case, for example, when the source electrode 35 is n-type and the drain electrode 34 is p-type, the semiconductor device 30 applies a voltage to the source electrode 35, the drain electrode 34, and the gate electrode 36, so that electrons are From 35, it flows to the drain electrode 34 through the graphene sheet 33.

Below, the manufacturing method of the semiconductor device 30 is demonstrated, referring drawings.
FIG. 3 is a schematic plan view showing the manufacturing process of the graphene sheet of the semiconductor device in the first embodiment, and FIG. 4 is a schematic plan view showing the manufacturing process of the source / drain electrodes of the semiconductor device in the first embodiment. FIG.

First, a description will be given with reference to FIG. A substrate 31 having an insulating property is prepared. Subsequently, a catalyst film is formed on the substrate 31 with a thickness of 1 nm to 10 nm and a plane orientation (111) using a transition metal such as cobalt (Co), iron (Fe), or Ni. The catalyst film pattern 32 having a width of 1 nm to 10 nm is formed by performing, for example, vapor deposition, lithography and etching. The direction of the catalyst film pattern 32 is such that the graphene sheet 33 grown later from the catalyst film pattern 32 develops semiconductor properties in the direction from the source electrode to the drain electrode. In addition, “width” refers to the length in the vertical direction of the drawing sheet as “width” in the drawings, and is expressed in the same manner below. Further, an insulating separation film 32a having a length of about 2 nm or more is formed in the center of the catalyst film pattern 32 by a normal semiconductor process. The graphene sheet 33 grown later functions as a channel through which electrons pass when the semiconductor device 30 is operated. At this time, if only the catalyst film pattern 32 is used, electrons may leak through the layer, leading to an increase in leakage current. Therefore, by forming the insulating separation film 32a on the catalyst film pattern 32, such a leakage current can be prevented. Subsequently, C atoms are supplied to the catalyst film pattern 32, and heated to a temperature of about 350 ° C. or higher, for example, about 600 ° C. by a hot filament CVD (Chemical Vapor Deposition) method using C 2 H 2 as a raw material. Grow. When the graphene sheet 33 is grown from the catalyst film pattern 32 having the insulating separation film 32a in the center, the graphene sheet 33 grows so as to protrude outside the catalyst film pattern 32. This is a phenomenon similar to the lateral overgrowth normally observed in semiconductor crystals. Thus, since the graphene sheet 33 extends in the lateral direction at the end of the catalyst film pattern 32, as shown in FIG. 3, it extends from the catalyst film pattern 32 on both sides of the insulating film 32a on the insulating film 32a. A structure in which the graphene sheets 33 are connected is obtained. As described above, the configuration shown in FIG. 3 is formed.

  Next, a description will be given with reference to FIG. After the growth of the graphene sheet 33, the drain electrode 34 and the source electrode 35 exhibiting ohmic resistance are connected to the graphene sheet 33 and formed on the substrates 31 on both sides of the catalyst film pattern 32. As a constituent material of the drain electrode 34 and the source electrode 35, for example, titanium (Ti), Fe, palladium (Pd), platinum (Pt), vanadium (V), or the like can be applied. As described above, the configuration shown in FIG. 4 is formed.

Finally, a description will be given with reference to FIG. After the formation of the drain electrode 34 and the source electrode 35, on the graphene sheet 33, for example, with a normal semiconductor process using silicon dioxide (SiO 2 ), titanium oxide (TiO 2 ), hafnium oxide (HfO 2 ), or the like, A gate insulating film 36a is formed. Further, a doped polysilicon (Poly-Si) or metal gate is formed as the gate electrode 36 on the gate insulating film 36a to form a MIS (Metal-Insulator-Semiconductor) gate structure.

Through the above manufacturing process, the catalyst film pattern 32 separated by the insulating separation film 32 a is formed on the insulating substrate 31 as shown in FIG. 2, and the graphene sheet 33 is grown on the catalyst film pattern 32. Thus, the semiconductor device 30 in which the drain electrode 34 and the source electrode 35 are formed on the substrate 31 on both sides of the graphene sheet 33 and the gate electrode 36 is formed on the graphene sheet 33 via the gate insulating film 36a can be manufactured. it can.
(Example 1-2)
In Example 1-2, the case of a semiconductor device from which the catalyst film pattern has been removed will be described as an example.

  5A and 5B show the semiconductor device according to the first embodiment, in which FIG. 5A is another schematic cross-sectional view, and FIG. 5B is another schematic plan view. In FIG. 5B, part of the gate insulating film 36a and the gate electrode 36 are intentionally removed so that the channel portion of the graphene sheet 33 can be seen.

  In the semiconductor device 30 a, unlike the semiconductor device 30, the graphene sheet 33 is directly disposed on the insulating substrate 31. In the remaining configuration, the drain electrode 34 and the source electrode 35 are formed on the substrate 31 on both sides of the graphene sheet 33, and the gate electrode 36 is formed on the graphene sheet 33 via the gate insulating film 36a, similarly to the semiconductor device 30. ing. In this case, also in the semiconductor device 30a, for example, by applying a voltage to the source electrode 35, the drain electrode 34, and the gate electrode 36, electrons flow from the source electrode 35 to the drain electrode 34 through the graphene sheet 33.

Hereinafter, a method for manufacturing the semiconductor device 30a will be described with reference to the drawings.
FIG. 6 is another schematic plan view showing the manufacturing process of the graphene sheet of the semiconductor device according to the first embodiment, and FIG. 7 shows the manufacturing process of the source / drain electrodes of the semiconductor device according to the first embodiment. It is another plane schematic diagram.

  First, a description will be given with reference to FIG. A substrate 31 having an insulating property is prepared. Subsequently, a laminated film pattern 32b made of a metal base film and a catalyst film whose direction is controlled in the same manner as in Example 1 is formed on the substrate 31. However, in this case, it is not necessary to form the insulating separation film 32a in the laminated film pattern 32b. Subsequently, the graphene sheet 33 is grown from the laminated film pattern 32b in the same manner as in Example 1. Subsequently, in Example 2, for example, the source electrode 35 is formed as a pinned film on one of the multilayer film pattern 32 b and the graphene sheet 33. The graphene sheet 33 is fixed to the substrate 31 by forming a pinned film on one side of the graphene sheet 33. The pinned film may be the drain electrode 34 instead of the source electrode 35. In addition, any of the drain electrode 34 and the source electrode 35 can be formed in the same manner as in the first embodiment. Thus, the configuration shown in FIG. 6 is formed.

  Next, a description will be given with reference to FIG. After the graphene sheet 33 is fixed to the substrate 31 by the pinned film, the metal base film and the catalyst are formed by, for example, performing selective etching with a hydrofluoric acid (HF) solution without cutting the graphene sheet 33, the source electrode 35, and the substrate 31. Only the laminated film pattern 32b of the film is etched. Subsequently, the remaining drain electrode 34 is formed on the substrate 31 of the graphene sheet 33. Thus, the configuration shown in FIG. 7 is formed.

  Finally, a description will be given with reference to FIG. After the formation of the drain electrode 34 and the source electrode 35, the gate insulating film 36a is formed on the graphene sheet 33 in the same manner as in Example 1, and the gate electrode 36 is formed on the gate insulating film 36a.

  Through the above steps, as shown in FIG. 5, the graphene sheet 33 is placed on the insulating substrate 31, and the drain electrode 34 and the source electrode 35 are formed on the substrates 31 on both sides of the graphene sheet 33. The semiconductor device 30a in which the gate electrode 36 is formed on the graphene sheet 33 through the gate insulating film 36a can be manufactured.

Next, a second embodiment will be described with reference to the drawings. In the second embodiment, the case of a wiring structure using the outline of the present invention will be described as an example.
FIG. 8 is a wiring structure according to the second embodiment, where (A) is a schematic plan view when a catalyst film pattern is present, and (B) is a schematic plan view when there is no catalyst film pattern.

  As shown in FIG. 8A, the wiring structure 40 has a laminated film pattern 42 of a metal base film and a catalyst film formed on a substrate 41, and a graphene sheet 43 is formed along the laminated film pattern 42. Growing.

  It is already possible to obtain a graphene sheet of a desired shape, a desired crystal orientation and a desired electrical conductivity at a desired location by forming the catalyst film pattern in a desired location by controlling the shape and crystal direction. As stated. Based on this, the second embodiment is configured by using a laminated film pattern 42 of a metal base film and a catalyst film. Further, in order to show the metallicity of the graphene sheet 43 and use it as wiring, the laminated film pattern 42 is formed so that the graphene sheet 43 forms an angle of about 120 degrees, and the graphene sheet 43 having one or more layers is formed. Need to grow.

  In the wiring structure 40a, the graphene sheet 43 is directly disposed on the substrate 41 as shown in FIG. In order to manufacture the wiring structure 40a, it is necessary to grow the one or more graphene sheets 43 by forming the laminated film pattern 42 so as to form an angle of about 120 degrees as in the case of the wiring structure 40. Further, in the wiring structure 40a, after the formation of the laminated film pattern 42 in the same manner as in Example 1-2 of the first embodiment, the graphene sheet 43 is fixed with a pinned film (not shown), and selective etching is performed. Thus, the laminated film pattern 42 of the metal base film and the catalyst film may be etched.

  In addition, as a manufacturing method of said wiring structure 40,40a, the case where the graphene sheet 43 grown from the laminated film pattern 42 formed in the desired shape was used as wiring was demonstrated. On the other hand, a graphene sheet having a desired shape can be obtained by using another method as described below.

  FIG. 9 shows a manufacturing process of the wiring structure according to the second embodiment, where (A) is a graphene sheet, (B) is a schematic plan view of an imprint mask, and FIG. 10 is the second embodiment. It is a manufacturing process of the wiring structure in a form, and (A) is after a removal of a graphene sheet, and (B) is a plane schematic diagram of wiring of a graphene sheet.

  First, a description will be given with reference to FIG. A catalyst film (not shown) is formed on the insulating substrate 51. Subsequently, one or more graphene sheets 53 are grown from the catalyst film in the same manner as in the first embodiment. Alternatively, a separately grown graphene sheet 53 may be disposed on the substrate 51. Subsequently, the direction of the graphene sheet 53 is measured by AFM or the like, and based on the result, the substrate 51 is rotated to a desired angle so that the graphene sheet 53 exhibits metallic properties. Thus, the structure shown in FIG. 9A is formed.

  Next, description will be made with reference to FIG. An imprint mask 57 having a desired shape is pressed onto the graphene sheet 53 disposed on the substrate 51. Thus, the structure shown in FIG. 9B is formed.

Next, description will be made with reference to FIG. The imprint mask 57 is pressed onto the graphene sheet 53, and the unnecessary graphene sheet 53 is removed by etching. For the etching, plasma etching using oxygen (O) or ozone (O 3 ) can be used. Thus, the structure shown in FIG. 10A is formed.

  Finally, description will be made with reference to FIG. When the imprint mask 57 is peeled off after the unnecessary graphene sheet 53 is removed, the graphene sheet 53 having a desired shape can be obtained.

Through the above steps, as shown in FIG. 10B, a graphene sheet 53 having a desired shape and desired electrical conductivity can be obtained.
Note that a graphene sheet obtained by such a method can be applied not only to wiring of a semiconductor device but also to wiring of a channel portion or other electronic devices.

  As described above, in the present invention, since the graphene sheet can be grown on the (111) plane of the catalyst film pattern, when the catalyst film pattern is formed in a desired shape with a desired crystal orientation, a desired shape, A graphene sheet having a desired electrical conductivity and a desired crystal orientation can be obtained at a desired location. Therefore, when the catalyst film pattern is formed on the channel portion of the semiconductor device, a graphene sheet can be formed on the channel portion, and the speed can be increased while the semiconductor device is miniaturized, and a semiconductor device with improved characteristics can be obtained. it can. In addition to the channel portion of the semiconductor device, such a catalyst film pattern can be applied to a wiring structure of a semiconductor device or other electronic device. In this case, it is possible to increase the speed of signals and the like. .

  The above merely illustrates the principle of the present invention. In addition, many modifications and changes can be made by those skilled in the art, and the present invention is not limited to the precise configuration and application shown and described above, and all corresponding modifications and equivalents may be And the equivalents thereof are considered to be within the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS The outline | summary of the semiconductor device of this invention is shown, (A) is a cross-sectional schematic diagram, (B) is a principal part enlarged plan schematic diagram of a channel part. 1A is a schematic cross-sectional view of a semiconductor device according to a first embodiment, and FIG. It is a plane schematic diagram which shows the manufacturing process of the graphene sheet of the semiconductor device in 1st Embodiment. It is a plane schematic diagram which shows the manufacturing process of the source / drain electrode of the semiconductor device in 1st Embodiment. It is a semiconductor device in a 1st embodiment, and (A) is another section schematic diagram, and (B) is another plane schematic diagram. It is another plane schematic diagram which shows the manufacturing process of the graphene sheet of the semiconductor device in 1st Embodiment. It is another plane schematic diagram which shows the manufacturing process of the source / drain electrode of the semiconductor device in 1st Embodiment. It is a wiring structure in 2nd Embodiment, Comprising: (A) is a plane schematic diagram when there is a catalyst film pattern, (B) is a plane schematic diagram when there is no catalyst film pattern. It is a manufacturing process of the wiring structure in a 2nd embodiment, and (A) is a plane schematic diagram of a graphene sheet and (B) is an imprint mask. It is a manufacturing process of the wiring structure in 2nd Embodiment, (A) is after the removal of a graphene sheet, (B) is a plane schematic diagram of the wiring of a graphene sheet.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 10a Expansion schematic diagram 11 Substrate 12 Catalyst film pattern 13 Graphene sheet 14 Drain electrode part 15 Source electrode part 16 Gate electrode part

Claims (7)

  1. Forming a (111) face catalyst film pattern of a transition metal on a substrate and growing a graphene sheet from the catalyst film pattern;
    Forming source / drain electrode portions on both ends of the graphene sheet;
    Forming a gate electrode portion on the graphene sheet;
    A method for manufacturing a semiconductor device, comprising:
  2.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the catalyst film pattern.
  3. An imprint mask is imprinted on another graphene sheet grown from the catalyst film pattern on the (111) surface of the transition metal, and the graphene sheet cut out from the another graphene sheet along the imprint mask is placed on the substrate. Forming, and
    Forming source / drain electrode portions on both ends of the graphene sheet;
    Forming a gate electrode portion on the graphene sheet;
    A method for manufacturing a semiconductor device, comprising:
  4.   4. The semiconductor device according to claim 1, wherein an orientation of the catalyst film pattern is a direction in which the graphene sheet is directed from the source electrode to the drain electrode and exhibits semiconductor properties. 5. Production method.
  5.   The method for manufacturing a semiconductor device according to claim 1, wherein the graphene sheet has five or less layers.
  6. In a semiconductor device comprising a channel part on a substrate, source / drain electrode parts formed on the substrate on both sides of the channel part, and a gate electrode part formed on the channel part,
    The channel device includes a graphene sheet grown on a (111) plane of a catalyst film pattern separated by an insulating separation film.
  7.   The semiconductor device according to claim 6, wherein the graphene sheet has five or less layers.
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