CN105140273A - Gate structure of semiconductor device and fabrication method of gate structure - Google Patents
Gate structure of semiconductor device and fabrication method of gate structure Download PDFInfo
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- CN105140273A CN105140273A CN201510486078.3A CN201510486078A CN105140273A CN 105140273 A CN105140273 A CN 105140273A CN 201510486078 A CN201510486078 A CN 201510486078A CN 105140273 A CN105140273 A CN 105140273A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000001259 photo etching Methods 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001947 vapour-phase growth Methods 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 230000001413 cellular effect Effects 0.000 description 4
- 229940090044 injection Drugs 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000035755 proliferation Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000012271 agricultural production Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
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- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
The invention relates to a gate structure of a semiconductor device. The gate structure comprises a gate oxide layer, a field oxide structure and a poly-silicon split gate, wherein the gate oxide layer is arranged on a substrate, the field oxide structure is arranged on the gate oxide layer, the poly-silicon split gate is arranged on the gate oxide layer and the field oxide structure, the width of the field oxide structure is smaller than the distance of two surfaces, deviating from each other, between a first gate structure and a second gate structure, and greater than the distance between the first gate structure and the second gate structure, and the orthographic projection of an interval region between the first gate structure and the second gate structure on the field oxide structure is not beyond the edge of the field oxide structure. The invention also relates to a fabrication method for the gate structure of the semiconductor device. The fabrication method is compatible and consistent with the traditional fabrication methods of a power vertical double-diffusion metal oxide semiconductor field effect transistor (VDMOS) and an insulated gate bipolar transistor (IGBT) chip, the process difficulty and the photoetching frequency are not increased, the specific turn-on resistance, the gate charge Qg and the leakage current Idss are low, the reliability is high, the chip area is small, the production cost can be greatly reduced, and the fabrication method can be used for manufacturing the power VDMOS and the IGBT chip at a large scale, low cost and high reliability.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of grid structure of semiconductor device, also relate to a kind of manufacture method of grid structure of semiconductor device.
Background technology
Power VDMOSFET (vertical DMOS field-effect transistor) and power IGBT (insulated gate bipolar transistor) device huge in the demand in power drive market, be seen everywhere in daily life, industrial and agricultural production, national defence and Space Science and Technology, but increasingly competitive and more and more pay attention to today of production cost, power device manufacturer is faced with the immense pressure making high performance device and reduce production cost.The polysilicon gate of existing power device VDMOS and IGBT, due to wider, make the grid area of whole device large, thus grid charge Q g is very large, has had a strong impact on the high frequency characteristics of device.Particularly for super-current power unit, these restraining factors are more obvious.How to reduce grid charge Q g, the switch operating frequency improving power device becomes in power device manufacture needs the urgent problem solved.Further, existing power device VDMOS and IGBT is owing to will meet certain current characteristics and certain conducting resistance, and when adopting conventional grid width, chip area will do larger ability meets corresponding current characteristics.
A kind of method reducing grid charge Q g is, the centre below active area polysilicon gate and grid oxygen retains certain field oxygen, and its width is less than the width of polysilicon gate.The method Problems existing of this minimizing Qg is to reduction Qg limited use, though device frequency characteristic makes moderate progress, but still can not meet the needs of HF switch operating characteristic.
Summary of the invention
Based on this, be necessary to provide a kind of grid structure that can reduce the semiconductor device of grid charge Q g.
A grid structure for semiconductor device, comprises the gate oxide be positioned on substrate, is positioned at the field oxide structure on gate oxide, and is positioned at the split polysilicon grid on gate oxide and field oxide structure; Described split polysilicon grid comprise the first grid structure and second grid structure that are separated from each other, the width of described field oxide structure is less than the distance on the two sides mutually deviated between described first grid structure and second grid structure and the interval be greater than between first grid structure and second grid structure, and the orthographic projection on the interval region oxide structure on the scene between described first grid structure and second grid structure should not exceed the edge of an oxide structure.
Wherein in an embodiment, the distance on the two sides that described first grid structure and second grid structure deviate from mutually is 9 microns ~ 15 microns, and the width of described interval region is 1 micron ~ 5 microns, and the width of described field oxide structure is 3 microns ~ 7 microns.
Wherein in an embodiment, described field oxide structure in the direction of the width more each than the both sides of described interval region wide go out 1 ~ 3 micron.
Wherein in an embodiment, also comprising well region in described substrate, there is interval in the horizontal to ensure that well region can not extend to an oxide structure in described well region and field oxide structure.
Wherein in an embodiment, the thickness of described field oxide structure is 1 micron ~ 2 microns, and the thickness of the gate oxide of oxide structure both sides, field is 0.05 micron ~ 0.12 micron.
There is a need to the manufacture method of the grid structure that a kind of semiconductor device is provided.
A manufacture method for the grid structure of semiconductor device, comprises the following steps: to provide substrate; Thermal oxide growth field oxide over the substrate; Photoetching also etches described field oxide, forms the field oxide structure belonging to grid structure; At oxide structure both sides, described field thermal oxide growth gate oxide; Depositing polysilicon on described field oxide structure and gate oxide; Carry out polysilicon photoetching and etching, first grid structure and second grid structure that one piece of formation is separated from each other will be dug up in the middle of polysilicon, as split polysilicon grid; Orthographic projection on the oxide structure on the scene of the region of diging up should not exceed the edge of an oxide structure, and the width of described field oxide structure is less than the distance on the two sides mutually deviated between described first grid structure and second grid structure and the width in the region of diging up described in being greater than.
Wherein in an embodiment, described in carry out the step of polysilicon photoetching and etching after, also comprise step: in described substrate, form P trap; N-type region is formed in described P trap.
Wherein in an embodiment, described in P trap, form the step of N-type region before, also comprise carry out N+ photoetching, N+ injects the step of removing photoresist with N+, the photoresist that described N+ photoetching is formed is by the described region overlay dug up thus stop ion when N+ injects.
Wherein in an embodiment, in the step of described thermal oxide growth field oxide on substrate, oxidate temperature is 1000 DEG C-1100 DEG C, and field oxide thickness is 1 micron ~ 2 microns; In the step of described oxide structure both sides on the scene thermal oxide growth gate oxide, oxidate temperature is 850 DEG C-1000 DEG C, and gate oxide thickness is 0.05 micron ~ 0.12 micron.
Wherein in an embodiment, on described oxide structure on the scene and gate oxide, the step of depositing polysilicon adopts low-pressure chemical vapor phase deposition technique, and the polysilicon thickness of deposit is 0.6 micron ~ 1 micron, and reaction temperature is 550 DEG C-650 DEG C.
The grid structure of above-mentioned semiconductor device, due to the middle part of polysilicon gate has been dug up one piece, thus makes grid charge Q g significantly reduce.Meanwhile, above gate oxide, be provided with part field oxide structure, minimizing grid charge Q g is also had certain effect.Due to these two kinds of factor actings in conjunction, grid charge Q g can be reduced significantly.On the other hand, because grid charge Q g significantly reduces, therefore can grid width be done larger, JFET resistance is reduced greatly, On current increases greatly, and the conducting resistance of unit are reduces greatly, thus can obtain larger On current and less conducting resistance with less chip area, the power VDMOSFET produced than traditional handicraft and the chip area of IGBT reduce more, greatly can reduce production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of splitting bar;
Fig. 2 is the generalized section of the grid structure of semiconductor device in an embodiment;
Fig. 3 is the field oxide structure of grid structure in an embodiment and the wide association schematic diagram of other parts;
Fig. 4 is the flow chart of the manufacture method of the grid structure of semiconductor device in an embodiment.
Embodiment
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.First-selected embodiment of the present invention is given in accompanying drawing.But the present invention can realize in many different forms, is not limited to embodiment described herein.On the contrary, the object of these embodiments is provided to be make to disclosure of the present invention more thoroughly comprehensively.
Unless otherwise defined, all technology used herein and scientific terminology are identical with belonging to the implication that those skilled in the art of the present invention understand usually.The object of term used in the description of the invention herein just in order to describe specific embodiment, is not intended to be restriction the present invention.Term as used herein " and/or " comprise arbitrary and all combinations of one or more relevant Listed Items.
In order to reduce grid charge Q g, the present invention adopts the structure of splitting bar, specifically see Fig. 1, splitting bar is dug up by etching technics at the middle part of polysilicon gate on traditional grid structure basis in one piece (region 103 namely in Fig. 1), thus obtain the split polysilicon grid that are made up of the remaining first grid structure 102 in both sides and second grid structure 104.Because polysilicon gate, field oxygen, grid oxygen and substrate form a capacitor jointly, the polar plate area (i.e. the area of polysilicon gate bottom surface) of this capacitor is larger, and input capacitance Ciss is also larger.What grid charge Q g described is the size that this capacitor stores the ability of electric charge, and input capacitance Ciss is larger, and grid charge Q g is also larger, then the switching speed of device is also slower.Dug up by the polysilicon in region 103, the floor space of polysilicon gate reduces, and just can reduce the grid charge Q g of device.
Fig. 2 is the generalized section of the grid structure of semiconductor device in an embodiment.Grid structure comprises the gate oxide 24 be positioned on substrate 10, is positioned at the field oxide structure 22 on gate oxide 24, and is positioned at the split polysilicon grid 26 on gate oxide 24 and field oxide structure 22.Due to the stop of thick field oxygen, during heat growth gate oxide 24, oxygen is difficult to through field oxide structure 22 and contacts with the substrate 10 of below, and the gate oxide thickness below field oxide structure 22 can be ignored, therefore does not draw the grid oxygen below an oxide structure 22 in Fig. 2.Split polysilicon grid comprise the first grid structure and 262 second grid structures 264 that are separated from each other.The width of oxide structure 22 is less than the distance on the two sides mutually deviated between first grid structure 262 and second grid structure 264 and the interval be greater than between first grid structure 262 and second grid structure 264.As aforementioned, the interval region 25 between first grid structure 262 and second grid structure 264 can by cutting out one piece of formation when etching by the middle of polysilicon gate.Interval region 25 is positioned at directly over an oxide structure 22 to ensure that the orthographic projection on interval region 25 oxide structure 22 on the scene can not exceed the edge of an oxide structure 22, as long as in other words ensure in the scope of interval region 25 oxide structure 22 on the scene, so some are also fine a little partially in position, do not need strict placed in the middle.
When field oxide structure 22 below interval region 25 can inject at well region, N+ injects and P+ injects, stop that injecting ion is injected into source region from interval region 25, avoids conducting resistance Rdon and leakage current Idss to increase.
The grid structure of above-mentioned semiconductor device, due to the middle part of polysilicon gate has been dug up one piece, thus makes grid charge Q g significantly reduce.Meanwhile, field oxide structure 22 also has certain effect to minimizing grid charge Q g.Due to these two kinds of factor actings in conjunction, grid charge Q g can be reduced significantly.
On the other hand, because grid charge Q g significantly reduces, therefore can grid width be done larger, JFET resistance (neck region resistance) is reduced greatly, On current increases greatly, and the conducting resistance of unit are (i.e. conduction resistance) is reduced greatly, thus can obtain larger On current and less conducting resistance with less chip area, the power VDMOSFET produced than common process and the chip area of IGBT reduce more, greatly can reduce production cost.
Please composition graphs 3 (eliminating the label of each structure of device in Fig. 3) in the lump, in one embodiment, the distance a of the left side on the right of second grid structure 264 of first grid structure 262 is 9 microns ~ 15 microns, the width c of interval region 25 is 1 micron ~ 5 microns, and the width b of field oxide structure 22 is 3 microns ~ 7 microns.So, field oxide structure 22 in the direction of the width more each than the both sides of interval region 25 wide go out 1 ~ 3 micron.Understandable, below first grid structure 262 and second grid structure 264, (instead of below interval region 25) retains the field oxide structure 22 of enough width, is conducive to reducing grid charge Q g.
As shown in Figure 2, well region 12 is also comprised in substrate 10.In the present embodiment, substrate 10 is N-type substrate, and well region 12 is P trap.N-type region 14 is also formed in well region 12.Well region 12 inside forms conducting channel under the effect of cut-in voltage, and the electronics in N-type region 14 arrives the drain region of device bottom through conducting channel, JFET district and tagma, forms drain current.The horizontal proliferation of well region 12 to be controlled during manufacture, make well region 12 and field oxide structure 22 there is a bit of interval d in the horizontal, to ensure that well region 12 can not extend to an oxide structure 22, avoid conducting channel to extend below an oxide structure 22 and device cannot be opened.
The grid structure of above-mentioned semiconductor device mainly for the invention that vertical DMOS field-effect transistor (VDMOS) and insulated gate bipolar transistor (IGBT) carry out, but also can be applied to the semiconductor device of other type.
Wherein in an embodiment, the thickness of field oxide structure 22 is 1 micron ~ 2 microns, and the thickness of the gate oxide 24 of field oxide structure 22 both sides is 0.05 micron ~ 0.12 micron.
Fig. 4 is the flow chart of the manufacture method of the grid structure of semiconductor device in an embodiment, comprises the following steps:
S310, provides substrate.
Adopt N-type silicon substrate in the present embodiment.Also P-type substrate can be adopted in other embodiments.
S320, thermal oxide growth field oxide on substrate.
Long field oxide can be given birth to by known thermal oxidation technology.In the present embodiment, oxidate temperature is 1000 DEG C-1100 DEG C, and the field oxide thickness of growth is 1 micron ~ 2 microns.
S330, photoetching also etches field oxide, forms the field oxide structure belonging to grid structure.
The place that should be noted that is except the circular hand-hole etched needed for terminal injection (P+ injection), also need to retain the field oxide structure (barrier layer) of division needed for gate hole, inject ion during to stop that P trap injects, N+ injects and P+ injects from the active area being injected into substrate by the interval region dug up.
S340, oxide structure both sides on the scene thermal oxide growth gate oxide.
Due to the stop of thick field oxygen, during heat growth gate oxide oxygen be difficult to through field oxide structure and with the substrate contact of below, the gate oxide thickness below the oxide structure of field can be ignored, and mainly oxide structure both sides on the scene form gate oxide.In the present embodiment, oxidate temperature is 850 DEG C-1000 DEG C, and the gate oxide thickness of growth is 0.05 micron ~ 0.12 micron.
S350, depositing polysilicon on the gate oxide on whole region and field oxide and field oxide both sides.
In the present embodiment, adopt low-pressure chemical vapor phase deposition technique, the polysilicon thickness of deposit is 0.6 micron ~ 1 micron, and reaction temperature is 550 DEG C-650 DEG C.The diffusion of the foreign ion (such as phosphonium ion) mixed in polysilicon can also be carried out after depositing polysilicon.In one embodiment, the temperature of diffusion is 900 DEG C-1000 DEG C.
S360, carries out polysilicon photoetching and etching, forms split polysilicon grid.
Etching polysilicon can using plasma lithographic technique, such as, use P5000 plasma etch apparatus to etch.By designing suitable polysilicon gate reticle pattern, dig up one piece by the middle of each polysilicon cellular, a cellular is become first grid structure that shape is separated from each other and second grid structure.The region of diging up is positioned at directly over an oxide structure to ensure that the orthographic projection on the oxide structure on the scene of this region can not exceed the edge of an oxide structure.The distance (i.e. the width of polysilicon gate cellular) on the two sides that be less than the width of oxide structure first grid structure and second grid structure deviate from mutually and be greater than the width in the region of diging up.
The manufacture method of the grid structure of above-mentioned semiconductor device, the etching of the technique and cellular polycrystalline of diging up polycrystalline gate hole is carried out simultaneously, do not need to increase photoetching number of times in addition, the photolithography edition territory of power VDMOSFET and IGBT is only needed suitably to change on the basis of conventional domain, do not increase process costs (comprising processing step and photoetching number of times), greatly can reduce manufacturing cost like this.
Also comprise after step S360 and form well region and in well region, inject the step that ion forms PN junction.According to aforementioned, in the present embodiment, substrate is N-type substrate, therefore well region is P trap, and forms N-type region by being infused in P trap.
Need to control well the horizontal proliferation of P trap during fabrication, make P trap and field oxide structure there is interval in the horizontal, to ensure that P trap can not extend to an oxide structure, avoid conducting channel to extend below an oxide structure and device cannot be opened.
Inject the step of N-type ion in well region before, also comprise and carry out the step that N+ injects photoetching.Wherein in an embodiment, the interval region dug up covers to stop when N+ injects by the photoresist that photoetching is formed.The object of such process is, through experiment, inventor finds that field oxide structure in the fabrication process because lateral encroaching is excessive, and may all can not block injection ion when N+ injects.And can make do not have N+ to inject in the substrate between splitting bar after processing like this, thus Idss leakage current is reduced, so just make the leakage current characteristic of device particularly reliability greatly improve.Can be removed clean when follow-up N+ removes photoresist by the photoresist diging up region between splitting bar.
Wherein in an embodiment, the distance on the two sides that first grid structure and second grid structure deviate from mutually is 9 microns ~ 15 microns, it is 1 micron ~ 5 microns by the width of the interval region dug up, the width of field oxide structure is 3 microns ~ 7 microns, covers the photoresist on interval region and go out 1.5 microns ~ 2 microns than every hem width of interval region when N+ injects photoetching.
In a word, the manufacture method of the grid structure of above-mentioned semiconductor device has that technique is simple, the advantage of superior performance, compatible and consistent with the manufacturing process of existing power VDMOSFET and igbt chip, does not increase technology difficulty, do not increase photoetching number of times, conduction resistance is little, and grid charge Q g is less, and leakage current Idss is little, reliability is high, chip area is less, greatly can reduce production cost, can be used for extensive, the low cost of power VDMOSFET and igbt chip, high reliability manufacture.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a grid structure for semiconductor device, is characterized in that, comprises the gate oxide be positioned on substrate, is positioned at the field oxide structure on gate oxide, and is positioned at the split polysilicon grid on gate oxide and field oxide structure; Described split polysilicon grid comprise the first grid structure and second grid structure that are separated from each other, the width of described field oxide structure is less than the distance on the two sides mutually deviated between described first grid structure and second grid structure and the interval be greater than between first grid structure and second grid structure, and the orthographic projection on the interval region oxide structure on the scene between described first grid structure and second grid structure should not exceed the edge of an oxide structure.
2. the grid structure of semiconductor device according to claim 1, it is characterized in that, the distance on the two sides that described first grid structure and second grid structure deviate from mutually is 9 microns ~ 15 microns, the width of described interval region is 1 micron ~ 5 microns, and the width of described field oxide structure is 3 microns ~ 7 microns.
3. the grid structure of semiconductor device according to claim 1, is characterized in that, described field oxide structure in the direction of the width more each than the both sides of described interval region wide go out 1 micron ~ 3 microns.
4. the grid structure of semiconductor device according to claim 1, is characterized in that, also comprises well region in described substrate, and described well region and field oxide structure exist interval in the horizontal to ensure that well region can not extend to an oxide structure.
5. the grid structure of semiconductor device according to claim 1, is characterized in that, the thickness of described field oxide structure is 1 micron ~ 2 microns, and the thickness of the gate oxide of oxide structure both sides, field is 0.05 micron ~ 0.12 micron.
6. a manufacture method for the grid structure of semiconductor device, comprises the following steps:
Substrate is provided;
Thermal oxide growth field oxide over the substrate;
Photoetching also etches described field oxide, forms the field oxide structure belonging to grid structure;
At oxide structure both sides, described field thermal oxide growth gate oxide;
Depositing polysilicon on described field oxide structure and gate oxide;
Carry out polysilicon photoetching and etching, first grid structure and second grid structure that one piece of formation is separated from each other will be dug up in the middle of polysilicon, as split polysilicon grid; Orthographic projection on the oxide structure on the scene of the region of diging up should not exceed the edge of an oxide structure, and the width of described field oxide structure is less than the distance on the two sides mutually deviated between described first grid structure and second grid structure and the width in the region of diging up described in being greater than.
7. the manufacture method of the grid structure of semiconductor device according to claim 6, is characterized in that, described in carry out the step of polysilicon photoetching and etching after, also comprise step:
P trap is formed in described substrate;
N-type region is formed in described P trap.
8. the manufacture method of the grid structure of semiconductor device according to claim 7, it is characterized in that, described in P trap, form the step of N-type region before, also comprise carry out N+ photoetching, N+ injects the step of removing photoresist with N+, the photoresist that described N+ photoetching is formed is by the described region overlay dug up thus stop ion when N+ injects.
9. the manufacture method of the grid structure of semiconductor device according to claim 7, is characterized in that, in the step of described thermal oxide growth field oxide on substrate, oxidate temperature is 1000 DEG C-1100 DEG C, and field oxide thickness is 1 micron ~ 2 microns; In the step of described oxide structure both sides on the scene thermal oxide growth gate oxide, oxidate temperature is 850 DEG C-1000 DEG C, and gate oxide thickness is 0.05 micron of rice ~ 0.12 micron.
10. the manufacture method of the grid structure of semiconductor device according to claim 7, it is characterized in that, on described oxide structure on the scene and gate oxide, the step of depositing polysilicon adopts low-pressure chemical vapor phase deposition technique, the polysilicon thickness of deposit is 0.6 micron ~ 1 micron, and reaction temperature is 550 DEG C-650 DEG C.
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| CN114373676A (en) * | 2022-01-17 | 2022-04-19 | 捷捷微电(上海)科技有限公司 | Manufacturing method of planar VDMOS device double-gate structure |
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| US6246101B1 (en) * | 1998-07-07 | 2001-06-12 | Mitsubishi Denki Kabushiki Kaisha | Isolation structure and semiconductor device including the isolation structure |
| CN103390645A (en) * | 2012-05-08 | 2013-11-13 | 上海韦尔半导体股份有限公司 | LDMOS transistor and manufacturing method thereof |
| CN103855152A (en) * | 2012-12-07 | 2014-06-11 | 旺宏电子股份有限公司 | Two-way double-pole junction transistor used for high-voltage electrostatic discharge protection |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114373676A (en) * | 2022-01-17 | 2022-04-19 | 捷捷微电(上海)科技有限公司 | Manufacturing method of planar VDMOS device double-gate structure |
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