CN105489638A - Back surface structure of insulated gate bipolar transistor and manufacturing method therefor - Google Patents
Back surface structure of insulated gate bipolar transistor and manufacturing method therefor Download PDFInfo
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- CN105489638A CN105489638A CN201510961999.0A CN201510961999A CN105489638A CN 105489638 A CN105489638 A CN 105489638A CN 201510961999 A CN201510961999 A CN 201510961999A CN 105489638 A CN105489638 A CN 105489638A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 31
- 238000000137 annealing Methods 0.000 claims description 5
- 210000002421 cell wall Anatomy 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 10
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 11
- 239000012634 fragment Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- -1 phosphonium ion Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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Abstract
The invention relates to a back surface structure of an insulated gate bipolar transistor. Back surface trenches are formed on the back surface of a silicon wafer at intervals; an inclined angle alpha between the trench wall of each back surface trench and the horizontal plane is 60-88 degrees; a trench-shaped N+ type field cut-off layer and a trench-shaped P+ type collector layer are formed at the bottom and the side wall of each back surface trench through an injection manner; the trench-shaped N+ type field cut-off layer is connected with an N type substrate; the trench-shaped P+ type collector layer is connected with the trench bottom and the side wall of the trench-shaped N+ type field cut-off layer; the trench top surface of the N+ type field cut-off layer and the trench top surface of the P+ type collector layer are connected with an N+ type collector layer; and a collector is formed by a metal layer 5 connected with the back surface of the N+ type collector layer 6 and a protruding part 5-1 of the metal layer 5 in the corresponding back surface trench 4. According to the back surface structure of the insulated gate bipolar transistor, the manufacturing cost and the debris rate can be reduced; and the cut-off type insulated gate bipolar transistor can be realized without requiring a slice-preparing process.
Description
Technical field
The present invention relates to structure of a kind of igbt and preparation method thereof, belong to igbt technical field.
Background technology
Igbt (IGBT) is by by double pole triode and insulating gate type field effect tube and the compound full-control type voltage driven type power semiconductor become, there is the high input impedance of insulating gate type field effect tube and the low conduction voltage drop of double pole triode, and drive circuit is simple, the advantages such as safety operation area is wide, no matter in the technological transformation of conventional industries, as electric machine speed regulation, various high frequency switch powers etc., or in the exploitation of new forms of energy, as solar power generation, wind power generation and new-energy automobile etc., and new industry aspect, as intelligent grid, track traffic etc., IGBT as power electronic system core switching device serves the effect of the key do not replaced.
IGBT is optimized, Facad structure has been upgraded to trench gate structure from planar gate structure, structure has been upgraded to thin slice electric field cut-off (FS) technology from break-through (PT), non-break-through (NPT), make device property more and more close to technology initial point, low pressure drop, low-loss, thus reduce energy consumption, improve power consumption efficiency.Conventional field blocking-up type (FS) structure for back side of IGBT as shown in Figure 1, is made up of N+ type barrier layer, P+ type emission layer and collector layer.But the domestic foundries that can stably produce back side FS structure few now, becomes one technology barrier that domestic IGBT substitutes import IGBT.Because blocking-up type (FS) structure for back side of IGBT needs to adopt thin slice processes, and thin slice processing systems and technique all need special customization, cause chip manufacture costly, and the easy fragment of wafer.
Summary of the invention
The object of this invention is to provide structure of a kind of igbt and preparation method thereof, manufacturing cost and fragment rate can be reduced, do not need can realize a cut-off type igbt by thin slice technique.
The present invention is the technical scheme achieved the above object: a kind of structure of igbt, it is characterized in that: be interval with backside trench at the back side of silicon chip, angle α between the cell wall of backside trench and horizontal plane is at 60 ~ 88 °, the channel bottom of groove and sidewall form the N+ type field cutoff layer of channel form and the P+ type collector layer of channel form by injecting overleaf, the N+ type field cutoff layer of channel form is connected with N-type substrate, the P+ type collector layer of channel form is connected with the bottom land of N+ type field cutoff layer and sidewall, the groove end face of N+ type field cutoff layer is connected with N+ type collector layer with the groove end face of P+ type collector layer, the metal level 5 being connected to the back side on N+ type collector layer 6 and the protruding 5-1 being arranged on corresponding backside trench 4 inner metal layer 5 form collector electrode.
Wherein: the groove on the backside trench on described silicon chip, N+ type field cutoff layer and the groove on P+ type collector layer are trapezoidal.
The degree of depth h of described backside trench is at 10 ~ 100um, and groove width b is at 5 ~ 50um, and two backside trench centre-to-centre spacing H are at 50 ~ 150um.
The thickness δ of described N+ type collector layer is at 0.1 ~ 0.5um.
The thickness δ 2 of described N+ type field cutoff layer is at 0.5 ~ 5um.
The thickness δ 1 of described P+ type collector layer is at 0.1 ~ 0.5um.
The manufacture method of the structure of igbt of the present invention, is characterized in that: after igbt front side of silicon wafer technique being carried out, carry out according to the following steps:
(1), silicon chip back side is thinned to 150 ~ 250um;
(2), overleaf inject N-type ion, implantation dosage is 5E14 ~ 5E15/cm
2, Implantation Energy is 30 ~ 400KeV, forms the N+ type collector layer of thickness δ at 0.1 ~ 0.5um;
(3), chemical wet etching groove forms backside trench, and backside trench sidewall and plane included angle α are at 60 ~ 88 °, and the degree of depth h of backside trench is at 10 ~ 100um, and groove width b is at 5 ~ 50um;
, overleaf the trench bottom of groove and sidewall implanted dopant be N-type ion, implantation dosage is 5E11 ~ 5E14/cm
2, Implantation Energy is 30KeV ~ 11MeV, form the N+ type field cutoff layer of channel form, and the thickness δ 2 of N+ type field cutoff layer is at 0.5 ~ 5um;
(5), again at channel bottom and the sidewall implanting p-type ion of N+ type field cutoff layer, implantation dosage is 5E14 ~ 5E15/cm
2, Implantation Energy is 30 ~ 170KeV, and form the P+ type collector layer of channel form, the thickness δ 1 of P+ type collector layer is at 0.1 ~ 0.5um;
(6), after annealing, deposited metal overleaf, makes the projection on metal level be filled in corresponding backside trench and forms collector electrode.
The present invention defines backside trench structure at the igbt back side, backside trench sidewall is not vertical, the trench bottom of groove and side are by injecting N+ type field cutoff layer and the P+ type collector layer that can form channel form overleaf, therefore do not need thin slice technique can realize back side FS structure.The present invention effectively can end electric field by the N+ type field cutoff layer of channel form, improve puncture voltage, and forming N+ type collector layer without the back side, trench area, be conducive to shortening the turn-off time, ensure to realize pressure drop while puncture voltage meets the demands and turn-off speed is better traded off.Igbt of the present invention is provided with backside trench, and the metal level at the back side has projection and can increase and silicon chip contact area, and reduce rear-face contact resistance, add the toughness of wafer, not easily fragment, thermal resistance reduces greatly than sheet.
The present invention improves structure for back side of IGBT, after front MOS structure completes, chip back surface thickness thinning is only needed with NPT back process required thickness close, do not need chip back surface to be thinned to FS back process required thickness, silicon wafer thickness is made to be thinned to 150 ~ 250um, and the fragment rate of wafer can be reduced, the unified N-type ion that injects is to form N+ type collector layer, and go out backside trench by chemical wet etching, and the groove sidewall making backside trench not with plane orthogonal, rearwardly the trench bottom of groove and groove side are injected N-type ion and are formed field cutoff layer again, effectively can end electric field, improve puncture voltage, simultaneously because vertical structure resistor coupled in parallel, the silicon wafer thickness forming FS structure place is thinner, pressure drop is little, can ensure that overall device pressure drop is still less.And FS structure is in turn off process, because wafer is thinner, itself turns off just than comparatively fast, keep N+ doping without trench area back portion, to form N+ type collector layer, in turn off process, be conducive to the quick derivation in hole, be conducive to equally accelerating turn-off speed.The present invention has only been partially formed thin slice technique, compared to NPT technique, because the existence of backside trench, add the contact area of back metal and silicon, reduce rear-face contact resistance, too increase the toughness of wafer simultaneously, the present invention can realize FS back process by means of thin slice technique, and the optimization of parameter can be realized, have great importance.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, embodiments of the invention are described in further detail.
Fig. 1 is the schematic diagram of former structure for back side of IGBT.
Fig. 2 is the schematic diagram of structure for back side of IGBT of the present invention.
Fig. 3 is the contrast schematic diagram of igbt characteristic of the present invention and FS technique and NPT operational characteristic.
Wherein: 1-silicon chip, 2-N+ type field cutoff layer, 3-P+ type collector layer, 4-backside trench, 5-metal level, 5-1-projection, 6-N+ type collector layer.
Embodiment
As shown in Figure 2, the structure of igbt of the present invention, backside trench 4 is interval with at the back side of silicon chip 1, angle α between the cell wall of backside trench 4 of the present invention and horizontal plane is between 60 ~ 88 °, the channel bottom of groove 4 and sidewall form the N+ type field cutoff layer 2 of channel form and the P+ type collector layer 3 of channel form by injecting overleaf, effectively electric field can be ended by N+ type field cutoff layer 2, improve puncture voltage, while ensureing that puncture voltage meets the demands, realize the relation of good pressure drop and turn-off speed.
As shown in Figure 2, the N+ type field cutoff layer 2 of channel form of the present invention is connected with N-type substrate, the P+ type collector layer 3 of channel form is connected with the bottom land of N+ type field cutoff layer 2 and sidewall, the groove end face of N+ type field cutoff layer 2 is connected with N+ type collector layer 6 with the groove end face of P+ type collector layer 3, because N+ type collector layer is without groove structure, be conducive to shortening the turn-off time.The present invention is connected to the metal level 5 at the back side on N+ type collector layer 6 and is arranged on the protruding 5-1 formation collector electrode of corresponding backside trench 4 inner metal layer 5, because the protruding 5-1 on metal level 5 is arranged in corresponding backside trench 4, the contact area of back metal and silicon can be increased, reduce rear-face contact resistance, reduce and manufacture fragment rate.
As shown in Figure 2, groove on backside trench 4 on silicon chip 1 of the present invention, N+ type field cutoff layer 2 and the groove on P+ type collector layer 3 are dovetail groove, this dovetail groove can be antiparallelogram groove or inequilateral dovetail groove, the degree of depth h of backside trench 4 of the present invention is at 10 ~ 100um, groove width b is at 5 ~ 50um, and two groove center distance H are 50 ~ 150um, by controlling the accounting in backside trench region, while making device pressure drop less, also reduce turn-off power loss, and silicon chip technique easily controls, realize affect trading off of device technology and characteristic.As shown in Figure 2, the thickness δ of N+ type collector layer 6 of the present invention at the thickness δ 2 of 0.1 ~ 0.5um, N+ type field cutoff layer 2 at the thickness δ 1 of 0.5 ~ 5um, P+ type collector layer 3 at 0.1 ~ 0.5um.
The structure of igbt of the present invention, angle α between the cell wall of its backside trench 4 and horizontal plane is between 62 ~ 80 °, the degree of depth h of backside trench 4 is at 30 ~ 80um, groove width b is at 10 ~ 40um, two groove center distance H are 60 ~ 100um, the thickness δ of N+ type collector layer 6 at 0.2 ~ 0.4um, and the thickness δ 2 of N+ type field cutoff layer 2 at the thickness δ 1 of 1 ~ 4um, P+ type collector layer 3 at 0.2 ~ 0.4um.
The structure of igbt of the present invention can also be that angle α between the cell wall of backside trench 4 and horizontal plane is between 65 ~ 75 °, the degree of depth h of backside trench 4 at 40 ~ 60um, groove width b between 25 ~ 30um, two groove center distance H are 70 ~ 120um, the thickness δ of N+ type collector layer 6 is at 0.2 ~ 0.5um, and the thickness δ 2 of N+ type field cutoff layer 2 is at 1.5 ~ 4um, the thickness δ 1 of P+ type collector layer 3 is at 0.2 ~ 0.5um, by Optimal Parameters, ensure to realize pressure drop while puncture voltage meets the demands and turn-off speed is better traded off.
The manufacture method of the structure of igbt of the present invention, after igbt front side of silicon wafer technique is carried out, carry out according to the following steps:
(1), by silicon chip 1 thinning back side to 150 ~ 250um, mill can be adopted to disappear carry out thinning, silicon chip 1 thinning back side is to the thickness of NPT back process, thickness is determined according to product voltage request, and thinning rear deionized water rinsing, to keep the clearly clean of the back side, also can destressing process be carried out if desired.
(2), overleaf inject N-type ion, implantation dosage is 5E14 ~ 5E15/cm
2, Implantation Energy is 30 ~ 400KeV, and form the N+ type collector layer 6 of thickness δ at 0.1 ~ 0.5um, N-type ion can adopt phosphonium ion or arsenic ion, and N-type Implantation Energy of the present invention is 150-310KeV, and implantation dosage is 8E14 ~ 3E15/cm
2time, N+ type collector layer 6 thickness of formation is at 0.2 ~ 0.4um; When N-type Implantation Energy be 160-400KeV, implantation dosage is 8E14 ~ 3E15/cm
2time, the thickness δ of N+ type collector layer 6, at 0.2 ~ 0.5um, facilitates control N+ type collector layer 6 thickness according to Implantation Energy and dosage.
(3), chemical wet etching groove forms backside trench 4, at silicon chip 1 backside coating photoresist, carry out exposing, develop and etching forming backside trench 4, and backside trench 4 sidewall and plane included angle α are at 60 ~ 88 °, the degree of depth h of backside trench 4 is at 10 ~ 100um, groove width b is at 5 ~ 50um, and two groove center distance H are 50 ~ 150um; As etched this angle of backside trench 4 α of formation between 62 ~ 80 °, the degree of depth h of backside trench 4 is at 30 ~ 80um, and groove width b is at 10 ~ 40um, and two groove center distance H are 60 ~ 100um; Or angle α is between 65 ~ 75 °, the degree of depth h of backside trench 4 is at 40 ~ 60um, groove width b between 25 ~ 30um, and two groove center distance H are 70 ~ 120um, and the accounting in backside trench region can adjust accordingly according to application.
, overleaf the trench bottom of groove 4 and sidewall implanted dopant be N-type ion, implantation dosage is 5E11 ~ 5E14/cm
2, Implantation Energy is 30KeV ~ 5MeV, and form the N+ type field cutoff layer 2 of channel form, and the thickness δ 2 of N+ type field cutoff layer 2 is at 0.5 ~ 5um, N-type ion can adopt phosphonium ion or arsenic ion.The present invention is when N-type Implantation Energy is at 900KeV-7.5MeV, and implantation dosage is at 5E12 ~ 5E13/cm
2time, the thickness δ 2 of the N+ type field cutoff layer 2 of formation is at 1 ~ 4um, and when N-type Implantation Energy is 2KeV-8MeV, implantation dosage is 5E12 ~ 5E13/cm
2time, the thickness δ 2 of the N+ type field cutoff layer 2 of formation, at 1.5 ~ 4um, can be able to adjust accordingly according to application.
(5), again at channel bottom and the sidewall implanting p-type ion of N+ type field cutoff layer 2, implantation dosage is 5E14 ~ 5E15/cm
2, Implantation Energy is 30 ~ 160KeV, and P+ type collector layer 3, the P type ion forming channel form can adopt boron ion or boron difluoride ion, and the thickness δ 1 of P+ type collector layer 3 is at 0.1 ~ 0.5um.It is 60-130KeV that the present invention works as P type Implantation Energy, and implantation dosage is 8E14 ~ 3E15/cm
2time, the thickness δ 1 of the P+ type collector layer 3 of formation is at 0.2 ~ 0.4um; When corresponding P type Implantation Energy is 60-170KeV, implantation dosage is 8E14 ~ 3E15/cm
2time, the thickness δ 1 of P+ type collector layer 3, at 0.2 ~ 0.5um, can be able to adjust accordingly according to application.The present invention can form N+ type field cutoff layer 2 and P+ type collector layer 3 by injection bottom groove 4 overleaf, does not need thin slice technique can realize back side FS structure.
(6), silicon chip 1 is put into annealing furnace to anneal, conventional annealing process can be adopted, after annealing, deposited metal 5 overleaf, can sputter overleaf or evaporate Ti-Ni-Ag, protruding 5-1 on metal level 5 is filled in corresponding backside trench 4 and forms collector electrode, to increase and silicon chip contact area, reduce rear-face contact resistance, add the toughness of wafer, and not easily fragment, thermal resistance reduces greatly than sheet.
The igbt characteristic made according to the present invention and the Character Comparison of thin slice FS technique and NPT technique, as can be seen from Figure 3, device property is better than NPT processing performance, pressure drop and turn-off power loss reduce all to some extent, cutting technique that technique is only many, do not need to use thin slice technique, manufacturing cost is without large increase, and fragment rate can not increase, the adverse effect that thin slice technique is brought can be avoided.
Claims (7)
1. the structure of an igbt, it is characterized in that: be interval with backside trench (4) at the back side of silicon chip (1), angle α between the cell wall of backside trench (4) and horizontal plane is at 60 ~ 88 °, the channel bottom of groove (4) and sidewall form N+ type field cutoff layer (2) of channel form and the P+ type collector layer (3) of channel form by injecting overleaf, N+ type field cutoff layer (2) of channel form is connected with N-type substrate, the P+ type collector layer (3) of channel form is connected with the bottom land of N+ type field cutoff layer (2) and sidewall, the groove end face of N+ type field cutoff layer (2) is connected with N+ type collector layer (6) with the groove end face of P+ type collector layer (3), the metal level (5) being connected to the back side on N+ type collector layer (6) and the projection (5-1) being arranged on corresponding backside trench (4) inner metal layer (5) form collector electrode.
2. the structure of igbt according to claim 1, is characterized in that: the groove on the backside trench (4) on described silicon chip (1), the groove on N+ type field cutoff layer (2) and P+ type collector layer (3) is trapezoidal.
3. the structure of igbt according to claim 1 and 2, it is characterized in that: the degree of depth h of described backside trench (4) is at 10 ~ 100um, groove width b is at 5 ~ 50um, and two backside trench (4) centre-to-centre spacing H is at 50 ~ 150um.
4. the structure of igbt according to claim 1 and 2, is characterized in that: the thickness δ of described N+ type collector layer (6) is at 0.1 ~ 0.5um.
5. the structure of igbt according to claim 1 and 2, is characterized in that: the thickness δ 2 of described N+ type field cutoff layer (2) is at 0.5 ~ 5um.
6. the structure of igbt according to claim 1 and 2, is characterized in that: the thickness δ 1 of described P+ type collector layer (3) is at 0.1 ~ 0.5um.
7. the manufacture method of the structure of igbt according to claim 1, is characterized in that: after igbt front side of silicon wafer technique being carried out, carry out according to the following steps:
(1), by silicon chip (1) thinning back side to 150 ~ 250um;
(2), overleaf inject N-type ion, implantation dosage is 5E14 ~ 5E15/cm
2, Implantation Energy is 30 ~ 400KeV, forms the N+ type collector layer (6) of thickness δ at 0.1 ~ 0.5um;
(3), chemical wet etching groove forms backside trench (4), and backside trench (4) sidewall and plane included angle α are at 60 ~ 88 °, and the degree of depth h of backside trench (4) is at 10 ~ 100um, and groove width b is at 5 ~ 50um;
, overleaf the trench bottom of groove (4) and sidewall implanted dopant be N-type ion, implantation dosage is 5E11 ~ 5E14/cm
2, Implantation Energy is 30KeV ~ 11MeV, form N+ type field cutoff layer (2) of channel form, and the thickness δ 2 of N+ type field cutoff layer (2) is at 0.5 ~ 5um;
(5) the channel bottom, again in N+ type field cutoff layer (2) and sidewall implanting p-type ion, implantation dosage is 5E14 ~ 5E15/cm
2, Implantation Energy is 30 ~ 170KeV, and form the P+ type collector layer (3) of channel form, the thickness δ 1 of P+ type collector layer (3) is at 0.1 ~ 0.5um;
(6), after annealing, deposited metal (5) overleaf, makes the projection (5-1) on metal level (5) be filled in corresponding backside trench (4) and forms collector electrode.
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| CN107464842A (en) * | 2017-08-03 | 2017-12-12 | 电子科技大学 | A kind of superjunction with colelctor electrode groove is against conductivity type IGBT |
| CN110676314A (en) * | 2019-10-23 | 2020-01-10 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor, power module and domestic electrical appliance |
| CN112670338A (en) * | 2020-12-23 | 2021-04-16 | 西安理工大学 | SiC insulated gate bipolar transistor with low threshold voltage and manufacturing method thereof |
| CN117766575A (en) * | 2023-12-29 | 2024-03-26 | 江苏易矽科技有限公司 | RC-IGBT structure capable of inhibiting Snapback phenomenon |
| CN118099199A (en) * | 2024-04-23 | 2024-05-28 | 洛阳鸿泰半导体有限公司 | Three-dimensional semiconductor substrate wafer and method suitable for IGBT device manufacturing |
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