CN102790080B - Self-aligning lifting base region silicon germanium heterojunction bipolar transistor and manufacturing method thereof - Google Patents

Abstract

The invention discloses a germanium-silicon heterojunction bipolar transistor with a self-aligned raised outer base region, which is designed to solve the defects of existing products such as large base resistance _RB . The self-aligned raised outer base germanium-silicon heterojunction bipolar transistor of the present invention mainly includes a Si collector region, a local dielectric region, a base region, a low-resistance metal silicide layer in the base region, a heavily doped polysilicon raised outer base region, a heavy Doped polysilicon emitter region, emitter-base isolation dielectric region, heavily doped single crystal emitter region, contact hole dielectric layer, emitter metal electrode and base metal electrode. The low-resistance metal silicide layer in the base region extends to the outside of the emitter-base isolation dielectric region. The invention discloses a method for preparing a germanium-silicon heterojunction bipolar transistor in a self-aligned raised outer base region, which is used for preparing the above-mentioned bipolar transistor. The self-alignment raised outer base region germanium-silicon heterojunction bipolar transistor and the preparation method of the present invention effectively reduce the base resistance _RB , and the process steps are simple and the cost is low.

Description

Self-aligned raised outer base germanium silicon heterojunction bipolar transistor and preparation method thereof

technical field

The invention relates to a germanium-silicon heterojunction bipolar transistor in a self-aligned raised outer base region and a preparation method thereof.

Background technique

Planar silicon bipolar transistors are traditional devices for building analog integrated circuits. However, due to the inherent disadvantages of silicon materials in terms of speed, high-frequency and high-speed applications have historically been dominated by III-V compound semiconductor devices such as gallium arsenide. The germanium-silicon heterojunction bipolar transistor obtained by introducing the narrow-bandgap germanium-silicon alloy as the base material into the silicon bipolar transistor has greatly improved the high-frequency performance, while maintaining the advantage of lower cost of silicon-based technology Therefore, it has been widely used in the field of radio frequency, microwave and high-speed semiconductor device base integrated circuits, and has partially replaced compound semiconductor technologies such as gallium arsenide.

The base resistance _RB and collector-base capacitance C _BC of bipolar transistors have always been the main parasitic parameters that restrict the further improvement of the high-frequency performance of the device, and their influence on the high-frequency performance of the device can be described by the following simplified expression.

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; max</span>}}<span\; class="notranslate">\; =</span>\sqrt{\frac{{\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}{\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; BC</span>}}}}$

Among them, f _T and f _max represent the cut-off frequency and the highest oscillation frequency of the device, respectively.

In addition, _RB is also a major source of thermal noise in bipolar transistors. Therefore, in order to improve the high-frequency performance of the device and improve the noise performance of the device, reducing _RB has always been one of the important tasks in the optimization of bipolar transistor devices and processes.

The self-alignment structure of the emitter region-external base region ensures that the distance between the heavily doped extrinsic base region and the emitter region does not depend on and is generally much smaller than the minimum line width or minimum overlay spacing allowed by lithography. One of the effective ways of small _RB .

For heterojunction bipolar transistors with a germanium-silicon base region grown by epitaxy, the device structure of the self-aligned raised extrinsic base region meets the self-alignment requirements for the relative position of the thicker heavily doped extrinsic base region and the emitter region, so It has become the standard device structure of today's high-performance self-aligned silicon-germanium heterojunction bipolar transistor process. The process schemes for realizing this self-aligned raised extrinsic base device structure can be roughly divided into two categories. One type is characterized in that the self-aligned raised extrinsic base region is formed after the epitaxy of the base region, and the self-aligned structure is mainly realized by means of a planarization process. The other type first deposits heavily doped polycrystalline raised extrinsic base regions, and uses photolithography and etching processes to form emission region windows, and then uses selective epitaxy to grow base epitaxial layers in the formed emission region windows And it is docked with the polycrystalline cantilever in the heavily doped outer base region formed in advance.

The common disadvantage of the above two types of technical solutions is that the process is relatively complicated. The former requires expensive special planarization equipment and processes, and the latter requires a selective epitaxy method that is difficult to control because of its base area that plays a decisive role in device performance. To grow, which may cause related process quality control problems, such as the problem that defects such as voids may appear in the connecting base region grown by selective epitaxy between the base region and the preformed extrinsic base region. Therefore, so far, the device structure and process implementation scheme of the self-aligned raised extrinsic base germanium silicon heterojunction bipolar transistor still needs to be improved.

Contents of the invention

In order to overcome the above-mentioned defects, the present invention proposes a self-aligned raised extrinsic germanium-silicon heterojunction bipolar transistor with simple process and smaller base resistance _RB .

In order to achieve the above object, on the one hand, the present invention proposes a self-aligned raised outer base germanium-silicon heterojunction bipolar transistor, which mainly includes a Si collector region, a local dielectric region, a Si collector region and a local dielectric The base region above the base region, the heavily doped polysilicon emitter region above the base region and the emitter-base isolation dielectric region, the heavily doped single crystal emitter region under the emitter window surrounded by the emitter-base isolation dielectric region, The base low-resistance metal silicide layer on the surface of the base area, the heavily doped polysilicon above the base low-resistance metal silicide layer lifts the outer base area, the contact hole dielectric layer, the emitter metal electrode and the base metal electrode; wherein, the The base area is composed of a single-crystal germanium-silicon base area and a polycrystalline germanium-silicon base area; the emitter-base isolation dielectric area is composed of an L-shaped silicon oxide layer and a silicon nitride sidewall; The silicide layer extends all the way to the outside of the emitter-base isolation dielectric region.

In another aspect, the present invention provides a method for preparing a self-aligned raised extrinsic base germanium-silicon heterojunction bipolar transistor, the method at least including the following steps:

2.1 Prepare the Si epitaxial layer of the first conductivity type, form a local dielectric region in the obtained Si epitaxial layer, and the part of the Si epitaxial layer where the local dielectric region is not formed is the Si collector region;

2.2 Prepare a silicon germanium base region of the second conductivity type above the obtained structure, form a single crystal silicon germanium base region at the position corresponding to the Si collector region, and form a polycrystalline silicon germanium base region at the position corresponding to the local dielectric region;

2.3 Deposit or sputter metal layer;

2.4 Depositing a first polysilicon layer to form a heavily doped first polysilicon layer of the second conductivity type; depositing a first silicon oxide layer on the first polysilicon layer;

2.5 Selectively remove the middle part of the first silicon oxide layer, the first polysilicon layer and the metal layer successively to form the first window, exposing the middle part of the surface of the single crystal germanium silicon base region; the remaining first polysilicon layer forming polysilicon to lift the extrinsic base region;

2.6 depositing the second silicon oxide layer;

2.7 Deposit a silicon nitride layer, and then use an anisotropic etching method to form a silicon nitride sidewall on the inner edge of the first window;

2.8 removing the second silicon oxide layer not covered by the silicon nitride sidewall, forming an L-shaped silicon oxide layer and an emitter-base isolation dielectric region composed of an L-shaped silicon oxide layer and a silicon nitride sidewall, and opening the The emission region window surrounded by the emission region-base isolation dielectric region exposes the middle part of the surface of the single crystal germanium silicon base region;

2.9 Depositing a second polysilicon layer, and heavily doping the second polysilicon layer into a polysilicon layer of the first conductivity type;

2.10 Etching away part of the second polysilicon layer and part of the first silicon oxide layer to form a heavily doped polysilicon emitter region of the first conductivity type;

2.11 The metal layer is silicided with the polycrystalline silicon germanium base region, part of the single crystal germanium silicon base region, and the polycrystalline silicon raised outer base region to obtain a low-resistance metal silicide layer in the base region; the heavily doped first layer formed in step 2.10 Impurities in the polysilicon emitter region of a conductivity type are diffused downward through the emitter region window to form a heavily doped single crystal emitter region of the first conductivity type;

2.12 Deposit a hole dielectric layer, prepare a contact hole, and lead out an emitter metal electrode and a base metal electrode.

In particular, the method for preparing a local dielectric region in the Si epitaxial layer in step 2.1 is digging a groove and filling it with a dielectric material or local oxidation.

In particular, the material of the metal layer in step 2.3 is one of titanium, cobalt or nickel.

In particular, the thickness of the second silicon oxide layer in step 2.6 is between 5nm and 50nm.

In particular, the method for forming the silicon nitride sidewall in step 2.7 is to deposit silicon nitride first and then perform anisotropic etching, and the width of the sidewall is between 10nm and 500nm.

In particular, the method of heavily doping the polysilicon layer into the polysilicon layer of the first conductivity type in step 2.9 is to use in-situ doping during the deposition of the polysilicon layer, or to use a dose greater than 10 ¹⁴ / The method of ion implantation of cm ² ;

In particular, the method of forming the low-resistance metal silicide layer in the base region in step 2.11 is to use one or more rapid thermal annealing processes.

In particular, in step 2.11, impurities in the heavily doped polysilicon emitter region of the first conductivity type diffuse downward through the emitter region window to form a heavily doped single crystal emitter region of the first conductivity type by using the above-mentioned formation of the base region One or more rapid thermal annealing processes of the low resistance metal silicide layer, either using a rapid thermal annealing or other thermal diffusion boosting process before or after this.

The low-resistance metal silicide layer in the base area of the self-aligned raised outer base germanium-silicon heterojunction bipolar transistor completely covers the surface of the polycrystalline germanium-silicon base area and partially covers the surface of the single-crystal germanium-silicon base area and extends all the way to the emitter. The region-base region is isolated from the outside of the dielectric region, so that the distance between the low-resistance metal silicide layer in the base region and the heavily doped single crystal emitter region is (considering that impurities in the heavily doped polysilicon emitter region diffuse through the emitter region window to form heavy doping The lateral diffusion of impurities in the process of heterogeneous single crystal emission region, this distance should be slightly smaller than) the width of the emission region-base isolation dielectric region composed of L-shaped silicon oxide layer and silicon nitride sidewall, that is, the thickness of L-shaped silicon oxide layer and the sum of the silicon nitride spacer widths. It can be seen that the distance is not limited by the minimum registration pitch size of lithography, and this distance can be fully reduced by optimizing the process, that is, the self-aligned silicon-germanium heterojunction bipolar transistor device structure is realized, which can effectively reduce The base resistance of the device.

Even if the doping of the polysilicon raised outer base region 20 of the device of the present invention adopts the mode of ion implantation, the damage region caused by the ion implantation can also be guaranteed to be away from the middle part of the single crystal germanium silicon base region 14 (the implantation is controlled by limiting the energy of the ion implantation depth), and the polysilicon raised extrinsic base region can also be doped in situ without introducing implant damage at all, so this device structure is conducive to suppressing TED (Transient Enhanced Diffusion) of impurities and minimizing the The impurity doped in-situ by epitaxy in the region 14 is redistributed due to impurity redistribution caused by subsequent thermal overhead, thereby ensuring excellent device performance.

Since the sheet resistance of the low-resistance metal silicide layer in the base region extending to the outside of the emitter-base isolation dielectric region and having a sufficiently small distance from the heavily doped single crystal emitter region is very small, usually much smaller than that of the heavily doped silicon-germanium-based The sheet resistance of the region, so compared with the usual self-aligned germanium-silicon heterojunction bipolar transistor, the device of the present invention can obtain a smaller base resistance _RB , thereby further improving the noise and radio frequency microwave power performance of the device .

The method for preparing the self-aligned silicon-germanium-silicon heterojunction bipolar transistor in the outer base region of the present invention realizes the self-aligned device structure by using the metal silicide process, so there is no need to use the usual self-aligned silicon-germanium heterojunction bipolar transistor The complex process steps necessary in the preparation process can effectively reduce the process complexity and manufacturing cost.

Description of drawings

1 to 12 are schematic diagrams of the process flow of the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

As shown in FIG. 12 , the self-aligned raised outer base germanium-silicon heterojunction bipolar transistor of the present invention mainly includes a Si collector region 10, a partial dielectric region 12, and a base on the Si collector region 10 and the partial dielectric region 12. The heavily doped polysilicon emitter region 29 on the region and the base region and the emitter region-base isolation dielectric region, the heavily doped single crystal emitter region 38 and the base region under the emission region window surrounded by the emitter region-base isolation dielectric region The low-resistance metal silicide layer 32 of the base region on the surface, the raised outer base region 20 of heavily doped polysilicon, the dielectric layer 40 of the contact hole, the emitter metal electrode 42 and the base metal electrode 44 . Wherein, the base area is composed of a single crystal silicon germanium base area 14 and a polycrystalline silicon germanium base area 16 ; The low-resistance metal silicide layer 32 in the base region extends all the way to the outside of the emitter-base isolation dielectric region. In a preferred structure, the base low-resistance metal silicide layer 32 completely covers the polycrystalline silicon germanium base region 16 and partially covers the single crystal silicon germanium base region 14 .

In the conventional non-self-aligned device structure involved in the background technology, since the low-resistance metal silicide layer 32 in the base region does not extend to the outside of the emitter-base isolation dielectric region, the low-resistance metal silicide layer 32 in the base region and the heavily doped The pitch of the single crystal emitter region 38 is at least equal to (considering the lateral diffusion effect of impurities in the process of forming the heavily doped single crystal emitter region 38, it should be slightly smaller) the thickness of the L-shaped silicon oxide layer 25 and the width of the silicon nitride sidewall 26 and the width of the first silicon oxide layer 22 . Due to limited photolithography conditions, the width of the first silicon oxide layer 20 cannot be smaller than the minimum photolithography alignment spacing, so the distance between the base low-resistance metal silicide layer 32 and the heavily doped single crystal emitter region 38 is limited to the minimum Therefore, the lithographic registration pitch cannot be very small, so the base resistance _RB of the common non-self-aligned device involved in the background art cannot be small, so that the optimization of device performance is limited to a certain extent.

The device structure of the present invention extends to the emitter-base isolation dielectric region formed by the L-shaped silicon oxide layer 25 and the silicon nitride sidewall 26 because the low-resistance metal silicide 32 in the base region formed by the silicidation reaction of the metal layer 18 extends all the way. , so that the distance between the base low-resistance metal silicide layer 32 and the heavily doped single crystal emitter region 38 is only equal to (considering the lateral diffusion effect of impurities in the process of forming the heavily doped single crystal emitter region 38, it should be slightly less than ) the sum of the thickness of the L-shaped silicon oxide layer 25 and the width of the silicon nitride sidewall 26. Neither the thickness of the L-shaped silicon oxide layer 25 nor the width of the silicon nitride sidewall 26 has anything to do with the photolithography process, so they are not limited and can be much smaller than the minimum photolithography registration pitch. Therefore, the distance between the low-resistance metal silicide layer 32 in the base region and the heavily doped single crystal emitter region 38 is not limited and can be much smaller than the minimum photolithography alignment distance. Therefore, the device structure of the metal silicide self-aligned raised outer base region germanium-silicon heterojunction bipolar transistor proposed by the present invention belongs to the self-aligned structure, so compared with the ordinary non-self-aligned device structure involved in the background art, it can A smaller base resistance _RB is obtained. Moreover, even the self-aligned devices involved in the background technology often can only ensure the self-alignment between the heavily doped germanium silicon base region and the heavily doped single crystal emitter region, but cannot guarantee the low-resistance metal silicide of the base region. The distance between the material layer and the heavily doped single crystal emitter region is minimized, while the device structure proposed by the present invention directly ensures the self-alignment and the distance between the base low-resistance metal silicide layer 32 and the heavily doped single crystal emitter region 38 Since the sheet resistance of the low-resistance metal silicide layer is usually much smaller than that of the heavily doped germanium-silicon base region, even compared to the self-aligned device involved in the background art, the device proposed by the present invention Still, the base resistance _RB can be further reduced, so that the speed, noise and radio frequency microwave power performance of the device can be further optimized.

The steps of preparing the self-aligned raised outer base germanium silicon heterojunction bipolar transistor of the present invention are as follows:

As shown in FIG. 1 , a Si epitaxial layer of the first conductivity type is prepared on a semiconductor substrate (not shown in the figure). In order to reduce the capacitance C _BC between the base region and the collector region, a local dielectric region 12 can be formed in a part of the Si epitaxial layer by digging a shallow trench and filling it with a dielectric material or by local oxidation. The local dielectric region 12 is generally silicon oxide, but not limited thereto. The remaining Si epitaxial layer region of the first conductivity type after the local dielectric region 12 is formed becomes the Si collector region 10 .

As shown in FIG. 2 , the silicon germanium base region of the second conductivity type is formed by means of epitaxial growth and in-situ doping, that is, a single crystal silicon germanium of the second conductivity type (generally containing silicon) is obtained on the Si collector region 10. and silicon germanium (multilayer epitaxial material) base region 14, and a polycrystalline silicon germanium (generally multilayer polycrystalline material including silicon and silicon germanium) base region 16 of the second conductivity type is obtained on the local dielectric region 12.

As shown in FIG. 3 , a metal layer 18 is deposited or sputtered, the metal can be but not limited to titanium, cobalt or nickel, with a thickness between 5nm and 500nm.

As shown in FIG. 4, the first polysilicon layer 20 is deposited, and it is heavily doped into the first polysilicon layer 20 by subsequent ion implantation with a dose greater than 10 ¹⁴ /cm ² or by in-situ doping during the deposition process. A first polysilicon layer 20 of two conductivity types; depositing a first silicon oxide layer 22 on the first polysilicon layer 20;

As shown in FIG. 5, the first silicon oxide layer 22, the first polysilicon layer 20 and the middle part of the metal 18 are selectively removed successively through a photolithography process to form a first window 21, exposing the underlying single-crystal silicon germanium. The middle part of the base region 14 . The remaining first polysilicon layer forms a polysilicon raised extrinsic base region.

As shown in FIG. 6, a second silicon oxide layer 24 is deposited with a thickness between 5nm and 50nm.

As shown in FIG. 7, a silicon nitride sidewall 26 is formed on the edge of the first window 21 by first depositing a layer of silicon nitride, and then using anisotropic etching. The width of the silicon nitride sidewall 26 is Between 10nm and 500nm.

As shown in FIG. 8 , under the cover of the silicon nitride sidewall 26, wet etching is used to remove the part of the second silicon oxide layer 24 not covered by the silicon nitride sidewall 26 to form an L-shaped silicon oxide layer 25 and the L-shaped silicon oxide layer 25. Silicon oxide layer 25 and silicon nitride sidewall 26 constitute the emitter-base isolation dielectric region, open the emitter window 27 surrounded by the emitter-base isolation dielectric region, and expose the single-crystal germanium silicon base region 14 again middle part.

As shown in FIG. 9, the second polysilicon layer 28 is deposited, and it is heavily doped by subsequent ion implantation with a dose greater than 10 ¹⁴ /cm ² or by in-situ doping during the above-mentioned deposition process. It is the second polysilicon layer 28 of the first conductivity type.

As shown in FIG. 10 , a part of the polysilicon layer 28 and a part of the first silicon oxide layer 22 are sequentially etched away by a photolithography process to form a heavily doped polysilicon emission region 29 of the first conductivity type.

As shown in FIG. 11 , one or more rapid thermal annealing processes are used to lift the outer base region of the metal layer 18 to the part of the single-crystal germanium-silicon base region 14 and the polycrystalline silicon-germanium base region 16 in contact with the bottom and the polysilicon base region in contact with the top. 20 undergoes a silicide reaction, and finally forms a low-resistance metal silicide layer 32 in the base region. The low-resistance metal silicide layer 32 in the base region may be but not limited to titanium silicide, cobalt silicide or nickel silicide.

At the same time, or prior to, or after the above-mentioned metal silicide process, the impurities in the heavily doped polysilicon emitter region 29 of the first conductivity type can pass through the emitter window to the outside by using a thermal annealing process or a thermal diffusion advancement process. Diffusion forms a heavily doped single crystal emitter region 38 of the first conductivity type.

As shown in Figure 12, the conventional semiconductor device and its integrated circuit back-end process can be used, including contact hole dielectric layer deposition, contact hole photolithography and etching, and metal layer sputtering, photolithography and etching, etc. The process flow of device preparation is finally completed, wherein 40 is the contact hole dielectric layer, 42 and 44 are the emitter metal electrode and the base metal electrode respectively.

Considering that the present invention has no limitation on the extraction method of the collector electrode, the extraction electrode of the collector area is not demonstrated in the process flow chart of the above specific embodiment. In fact, if the substrate (not shown in the figure) is a heavily doped Si wafer of the first conductivity type, the collector can be drawn from the back of the heavily doped substrate; if the substrate is a Si wafer of the second conductivity type In the case of wafers, the collector can be drawn out from the front of the wafer through metal wiring through conventional processes such as forming a heavily doped buried layer of the first conductivity type and a heavily doped collector sinker on the second conductivity type substrate.

The device preparation process proposed by the invention is very simple, so it has the advantages of low complexity and low cost in device manufacturing process.

Preferred embodiment: as shown in Figures 1 to 12, in the Si epitaxial layer formed by the semiconductor substrate, a local dielectric region 12 is formed on the surface by digging shallow grooves and filling the dielectric material, and the part where the local dielectric region is not formed forms a Si cluster. Electric Zone 10. The material of the partial dielectric region 12 is silicon oxide. A second-conductivity type single-crystal germanium-silicon base region 14 of a multilayer epitaxial material comprising silicon and germanium silicon is obtained above the Si collector region, and a multilayer polycrystalline material comprising silicon and germanium silicon is obtained above the local dielectric region 12 The polycrystalline silicon germanium base region 16 of the second conductivity type.

Sputtering a titanium metal layer 18; depositing and in-situ doping to obtain a heavily doped first polysilicon layer 20 of the second conductivity type; depositing a first silicon oxide layer 22 on the obtained structure. The middle part of the first silicon oxide layer 22, the first polysilicon layer 20 and the metal layer 18 is selectively removed successively by a photolithography process to form the first window 21, exposing the middle of the monocrystalline silicon germanium base region 14 below. part. The remaining first polysilicon layer is called the polysilicon raised extrinsic base region. A second silicon oxide layer 24 is deposited to a thickness of 10 nm. A silicon nitride side wall 26 is formed on the edge of the window by first depositing a layer of silicon nitride and then anisotropic etching, and the width of the side wall is 100 nm.

Under the cover of the silicon nitride sidewall 26, wet etching is used to remove the part of the second silicon oxide layer 24 not covered by the silicon nitride sidewall 26, thereby opening the window of the emission region and exposing the single crystal germanium silicon base region 14 again. middle part. The second polysilicon layer 28 is deposited, and is heavily doped into the second polysilicon layer 28 of the first conductivity type by subsequent ion implantation with a dose of 5×10 ¹⁵ /cm ² . A part of the second polysilicon layer 28 and a part of the first silicon oxide layer 22 are sequentially etched away by a photolithography process to form a heavily doped polysilicon emission region 29 of the first conductivity type.

Using multiple rapid thermal annealing processes, the silicide reaction occurs between the metal layer and the part of the single-crystal germanium-silicon base region 14 and the polycrystalline germanium-silicon base region 16 in contact with the lower part and the raised outer base region 20 of polysilicon in contact with the upper part, forming low-resistance titanium silicide layer 32. At the same time, impurities in the heavily doped polysilicon emitter region 29 of the first conductivity type are diffused downward and outward through the emitter window by thermal annealing process to form a heavily doped single crystal emitter region 38 of the first conductivity type. The hole dielectric layer 40 is deposited, and the photolithography and etching of the contact hole are completed; the sputtering, photolithography and etching of the interconnection metal layer are completed, and the emitter metal electrode 42 and the base metal electrode 44 are formed. Finally, the process flow of device preparation is completed.

The above are only preferred embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention are all Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be defined by the claims.

Claims (9)

1. A self-aligned raised outer base germanium-silicon heterojunction bipolar transistor, the transistor mainly includes a Si collector region, a local dielectric region, a base region above the Si collector region and a local dielectric region, and a base region above the base region The heavily doped polysilicon emitter region and the emitter-base isolation dielectric region, the emitter-base isolation dielectric region surrounded by the heavily doped single crystal emitter region under the emitter window, the base region low-resistance metal on the surface of the base region The silicide layer, the heavily doped polysilicon above the low-resistance metal silicide layer in the base area raise the outer base area, the contact hole dielectric layer, the emitter metal electrode and the base metal electrode; wherein, the base area is made of single crystal germanium silicon base region and a polycrystalline silicon germanium base region; the emitter-base isolation dielectric region is composed of an L-shaped silicon oxide layer and a silicon nitride sidewall, and is characterized in that the low-resistance metal silicide layer in the base region extends all the way To the outside of the emitter-base isolation dielectric region, the lower surface of the base low-resistance metal silicide layer is lower than the lower surface of the heavily doped polysilicon emitter region. 2. A method for preparing a self-aligned raised outer base germanium-silicon heterojunction bipolar transistor, characterized in that the method at least comprises the following steps: 2.1 Prepare the Si epitaxial layer of the first conductivity type, form a local dielectric region in the obtained Si epitaxial layer, and the part of the Si epitaxial layer where the local dielectric region is not formed is the Si collector region; 2.2 Prepare a silicon germanium base region of the second conductivity type above the obtained structure, form a single crystal silicon germanium base region at the position corresponding to the Si collector region, and form a polycrystalline silicon germanium base region at the position corresponding to the local dielectric region; 2.3 Deposit or sputter metal layer; 2.4 Depositing a first polysilicon layer to form a heavily doped first polysilicon layer of the second conductivity type; depositing a first silicon oxide layer on the first polysilicon layer; 2.5 Selectively remove the middle part of the first silicon oxide layer, the first polysilicon layer and the metal layer successively to form the first window, exposing the middle part of the surface of the single crystal germanium silicon base region; the remaining first polysilicon layer forming polysilicon to lift the extrinsic base region; 2.6 depositing the second silicon oxide layer; 2.7 Deposit a silicon nitride layer, and then use an anisotropic etching method to form a silicon nitride sidewall on the inner edge of the first window; 2.8 Remove the second silicon oxide layer not covered by the silicon nitride sidewall, form an L-shaped silicon oxide layer and an emitter-base isolation dielectric region composed of an L-shaped silicon oxide layer and a silicon nitride sidewall, and open the The emitter region-the base region isolating the emitter region window surrounded by the dielectric region, exposing the middle part of the surface of the single crystal germanium silicon base region; 2.9 Depositing a second polysilicon layer, and heavily doping the second polysilicon layer into a polysilicon layer of the first conductivity type; 2.10 Etching away part of the second polysilicon layer and part of the first silicon oxide layer to form a heavily doped polysilicon emitter region of the first conductivity type; 2.11 The metal layer is silicided with the polycrystalline silicon germanium base region, part of the single crystal germanium silicon base region, and the polycrystalline silicon raised outer base region to obtain a low-resistance metal silicide layer in the base region; the heavily doped first layer formed in step 2.10 Impurities in the polysilicon emitter region of a conductivity type are diffused downward through the emitter region window to form a heavily doped single crystal emitter region of the first conductivity type; 2.12 Deposit a hole dielectric layer, prepare a contact hole, and lead out an emitter metal electrode and a base metal electrode. 3. The method for preparing a self-aligned raised outer base germanium-silicon heterojunction bipolar transistor according to claim 2, characterized in that the method for preparing a local dielectric region in the Si epitaxial layer in step 2.1 is digging and refilling Dielectric material or localized oxidation. 4 . The method for preparing a self-aligned raised outer base germanium-silicon heterojunction bipolar transistor according to claim 2 , wherein the material of the metal layer in step 2.3 is one of titanium, cobalt or nickel. 5 . The method for manufacturing a self-aligned raised extrinsic base germanium-silicon heterojunction bipolar transistor according to claim 2 , wherein the thickness of the second silicon oxide layer in step 2.6 is between 5 nm and 50 nm. 6. The method for preparing a self-aligned raised outer base germanium-silicon heterojunction bipolar transistor according to claim 2, characterized in that the formation method of the silicon nitride sidewall in step 2.7 is to deposit silicon nitride first and then Anisotropic etching is performed, and the width of the sidewall is between 10nm and 500nm. 7. The method for preparing a self-aligned raised outer base germanium-silicon heterojunction bipolar transistor according to claim 2, characterized in that in step 2.9, the polysilicon layer is heavily doped with the polysilicon layer of the first conductivity type The method is to adopt the method of in-situ doping during the deposition of the polysilicon layer, or adopt the method of ion implantation with a dose greater than 10 ¹⁴ /cm ² after the deposition. 8. The method for preparing a self-aligned raised outer base germanium-silicon heterojunction bipolar transistor according to claim 2, characterized in that the method of forming the base low-resistance metal silicide layer in step 2.11 is to use one or more Secondary rapid thermal annealing process. 9. The method for preparing a self-aligned raised outer base germanium-silicon heterojunction bipolar transistor according to claim 2, characterized in that, in step 2.11, impurities in the heavily doped polysilicon emitter region of the first conductivity type pass through The emitter window is diffused downward and outward to form a heavily doped single crystal emitter of the first conductivity type by using one or more rapid thermal annealing processes to form a low-resistance metal silicide layer in the base region, either before or after rapid thermal annealing or other thermal diffusion advancement processes.