CN102790080B - Self-aligning lifting base region silicon germanium heterojunction bipolar transistor and manufacturing method thereof - Google Patents
Self-aligning lifting base region silicon germanium heterojunction bipolar transistor and manufacturing method thereof Download PDFInfo
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 47
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title abstract description 11
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 68
- 229920005591 polysilicon Polymers 0.000 claims abstract description 68
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 63
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 36
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 43
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 39
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 30
- 238000002360 preparation method Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 12
- 238000011065 in-situ storage Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 239000010953 base metal Substances 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000004064 recycling Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000005457 optimization Methods 0.000 description 3
- 230000035755 proliferation Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 206010010356 Congenital anomaly Diseases 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000012995 silicone-based technology Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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Abstract
The invention discloses a self-aligning lifting base region silicon germanium heterojunction bipolar transistor and is designed for overcoming the defects of high base resistance RB and the like in traditional products. The self-aligning lifting base region silicon germanium heterojunction bipolar transistor mainly comprises an Si collector region, a local medium region, a base region, a base region low-resistance metal silicide layer, a heavy-doping polysilicon lifting outer base region, a heavy-doping polysilicon emitting region, an emitting region-base region isolating medium region, a heavy-doping single crystal emitting region, a contact hole medium layer, an emitting electrode metal electrode and a base electrode metal electrode, wherein the base region low-resistance metal silicide layer extends to the outer side of the emitting region-base region isolating medium region. The invention discloses a manufacturing method for the self-aligning lifting base region silicon germanium heterojunction bipolar transistor. The manufacturing method is used for manufacturing the bipolar transistor. According to the self-aligning lifting base region silicon germanium heterojunction bipolar transistor and the manufacturing method thereof disclosed by the invention, the base resistance RB is effectively reduced, process steps are simple and the cost is low.
Description
Technical field
The present invention relates to a kind of autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor and preparation method thereof.
Background technology
Planar silicon bipolar transistor is the traditional devices building analog integrated circuit, but due to the congenital inferior position of silicon materials in speed, high-frequency high-speed application is dominated by Group III-V compound semiconductor devices such as GaAs always in history.The Ge-Si heterojunction bipolar transistor that low energy gap germanium-silicon alloy obtains as base material introducing silicon bipolar transistor, high frequency performance is greatly improved, also maintain the lower-cost advantage of silicon-based technologies simultaneously, therefore radio frequency, microwave and high-speed semiconductor device base integrated circuit fields has been widely used in, and the Some substitute compound semiconductor technology such as GaAs.
The base resistance R of bipolar transistor
bwith collector-base capacitor C
bCbe the main parasitic parameter that constraint device high frequency performance improves further, its expression formula on the available following simplification of the impact of device high frequency performance index describes always.
Wherein, f
tand f
maxrepresent cut-off frequency and the maximum frequency of oscillation of device respectively.
In addition, R
bor the main source of bipolar transistor thermal noise.Therefore, in order to improve the high frequency performance of device and improve the noiseproof feature of device, R is reduced
bit is one of vital task of bipolar transistor and process optimization always.
Adopt emitter region-outer base area self-alignment structure, namely ensureing that the spacing of device heavy doping outer base area and emitter region does not depend on and the minimum feature that in general allows much smaller than photoetching or minimum alignment spacing, is reduction R
bone of effective way.
For the heterojunction bipolar transistor by epitaxial growth SiGe base, the device architecture of autoregistration lifting outer base area meets thicker heavy doping outer base area and the autoregistration requirement of emitter region relative position, thus becomes the normal component structure of current high-performance autoregistration Ge-Si heterojunction bipolar transistor technique.The process program realizing this autoregistration lifting outer base area device architecture is broadly divided into two classes.The feature of one class, after autoregistration lifting outer base area is formed at base extension, mainly realizes self-alignment structure by flatening process.Another kind of first deposit heavily doped polycrystalline lifting outer base area, and utilize photoetching and etching technics to form emitter window, and then utilize selective epitaxial process to grow base epitaxial layer in established emitter window and dock with the heavy doping outer base area polycrystalline cantilever formed in advance.
The common drawback of above two class technical schemes is technique all more complicated, the former needs expensive special planarization instrument and supplies, the latter needs to adopt the method for technique selective epitaxial more rambunctious to grow to the base that device performance plays a decisive role due to it, thus relevant Process Quality Control problem may be caused, such as between base and preform outer base area by likely there is the problems of defects such as cavity in the connection base of selective epitaxial growth.Therefore, up to the present, the device architecture of autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor and process implementation thereof still have much room for improvement.
Summary of the invention
In order to overcome above-mentioned defect, the present invention proposes the simple and base resistance R of a kind of technique
bless autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor.
For achieving the above object, on the one hand, the present invention proposes a kind of autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor, described transistor mainly comprises Si collector region, local medium district, base above Si collector region and locally dielectric area, heavily doped polysilicon emitter region above base and emitter region-spacer medium district, base, heavy doping mono-crystalline emitter under the emitter window that emitter region-spacer medium district, base surrounds, the base region low-resistance metal silicide layer of base region surface, heavily doped polysilicon lifting outer base area above base region low-resistance metal silicide layer, contact hole dielectric layer, emitter metal electrode and base metal electrode, wherein, described base is made up of monocrystalline SiGe base and poly-SiGe base, described emitter region-spacer medium district, base is made up of L conformal silicon oxide floor and silicon nitride spacer, and described base region low-resistance metal silicide layer extends to outside emitter region-spacer medium district, base always.
On the other hand, the invention provides a kind of autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method, described method at least comprises the steps:
The Si epitaxial loayer of 2.1 preparation the first conduction types, in gained Si epitaxial loayer, form local medium district, the part not forming local medium district in Si epitaxial loayer is Si collector region;
2.2 SiGe base of preparing the second conduction type above resulting structures, form monocrystalline SiGe base in the position of corresponding Si collector region, form poly-SiGe base in the position in corresponding local medium district;
2.3 deposits or splash-proofing sputtering metal layer;
2.4 deposit first polysilicon layers, form the first polysilicon layer of heavily doped second conduction type; Deposit first silicon oxide layer on described first polysilicon layer;
2.5 mid portions successively removing the first silicon oxide layer, the first polysilicon layer and metal level selectively, form first window, expose the mid portion on surface, monocrystalline SiGe base; Remaining first polysilicon layer forms polysilicon lifting outer base area;
2.6 deposit second silicon oxide layers;
2.7 deposit silicon nitride layers, recycling anisotropic etching method forms silicon nitride spacer at first window inward flange;
2.8 remove not by the second silicon oxide layer that silicon nitride spacer covers, emitter region-spacer medium the district, base forming L conformal silicon oxide floor and be made up of L conformal silicon oxide floor and silicon nitride spacer, open the emitter window that described emitter region-spacer medium district, base surrounds, expose the mid portion on surface, monocrystalline SiGe base;
2.9 deposit second polysilicon layers, and the polysilicon layer by described second polysilicon layer heavy doping being the first conduction type;
Part second polysilicon layer and part first silicon oxide layer etch away by 2.10, form the polysilicon emissioning area of heavily doped first conduction type;
There is silicification reaction and obtain base region low-resistance metal silicide layer in the poly-SiGe base that 2.11 metal levels contact with it respectively, portion of monocrystalline SiGe base and polysilicon lifting outer base area; Impurity in the polysilicon emissioning area of heavily doped first conduction type that step 2.10 is formed forms the heavy doping mono-crystalline emitter of the first conduction type by the downward outdiffusion of emitter window;
2.12 deposit hole dielectric layers, prepare contact hole, draw emitter metal electrode and base metal electrode.
Particularly, the method preparing local medium district in step 2.1 in Si epitaxial loayer is that grooving recharges dielectric material or selective oxidation.
Particularly, in step 2.3, the material of metal level is the one in titanium, cobalt or nickel.
Particularly, in step 2.6, the thickness of the second silicon oxide layer is between 5nm to 50nm.
Particularly, in step 2.7, the formation method of silicon nitride spacer is that first deposit silicon nitride carries out anisotropic etching again, and the width of described side wall is between 10nm to 500nm.
Particularly, be that the method for the first conductivity type polysilicon layer is adopt in-situ doped method in depositing polysilicon layer process by described polysilicon layer heavy doping in step 2.9, or adopt dosage to be greater than 10 after the deposition
14/ cm
2the method of ion implantation;
Particularly, the method forming base region low-resistance metal silicide layer in step 2.11 is for utilizing once or repeatedly rapid thermal anneal process.
Particularly, in step 2.11 heavily doped first conduction type polysilicon emissioning area in the impurity method that formed the heavy doping mono-crystalline emitter of the first conduction type by the downward outdiffusion of emitter window be the one or many rapid thermal anneal process utilizing above-mentioned formation base region low-resistance metal silicide layer, or utilize rapid thermal annealing before this or afterwards or other thermal diffusions to advance technique.
The base region low-resistance metal silicide layer of autoregistration lifting outer base area of the present invention Ge-Si heterojunction bipolar transistor covers poly-SiGe base region surface completely and part covers surface, monocrystalline SiGe base and extends to outside emitter region-spacer medium district, base always, thus make the distance of base region low-resistance metal silicide layer and heavy doping mono-crystalline emitter be (consider that in heavily doped polysilicon emitter region, impurity forms the impurity horizontal proliferation in the process of heavy doping mono-crystalline emitter by emitter window outdiffusion, this distance should be less than slightly) width in emitter region-spacer medium district, base that is made up of L conformal silicon oxide floor and silicon nitride spacer, i.e. L conformal silicon oxide layer thickness and silicon nitride spacer width sum.Visible, described distance not by the restriction of the minimum alignment spacing dimension of photoetching, and can fully reduce this distance by Optimization Technology, namely achieves autoregistration Ge-Si heterojunction bipolar transistor device architecture, can effectively reduce the base resistance of device.
Even if the doping of the polysilicon lifting outer base area 20 of device of the present invention adopts the mode of ion implantation, the damage field that ion implantation causes also can ensure the mid portion (controlling to inject the degree of depth by the energy limiting ion implantation) away from monocrystalline SiGe base 14, moreover this polysilicon lifting outer base area can also adopt does not introduce the in-situ doped of implant damage completely, so this device architecture is conducive to the TED (transient enhanced diffusion) of inhibition of impurities, reduce the dopant redistribution caused due to its after heat expense by the impurity that extension is in-situ doped in monocrystalline SiGe base 14 as far as possible, thus ensure excellent device performance.
Owing to above-mentionedly to extend to outside emitter region-spacer medium district, base, the sheet resistance of the base region low-resistance metal silicide layer enough little with heavy doping mono-emitter Interval Distance is very little, usually much smaller than the sheet resistance of heavy doping SiGe base, so compared with common autoregistration Ge-Si heterojunction bipolar transistor, device of the present invention can obtain less base resistance R
b, thus noise and the frequency microwave power-performance of device can be improved further.
Autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method of the present invention is owing to being utilize metal silicide technology to realize autoregistration device architecture, thus without the need to adopting complex process steps required in common autoregistration Ge-Si heterojunction bipolar transistor preparation process, process complexity and manufacturing cost can effectively be reduced.
Accompanying drawing explanation
Fig. 1 ~ Figure 12 is process flow diagram of the present invention.
Embodiment
Below in conjunction with Figure of description and embodiment, the present invention is described in detail.
As shown in figure 12, autoregistration lifting outer base area of the present invention Ge-Si heterojunction bipolar transistor mainly comprises Si collector region 10, local medium district 12, base on Si collector region 10 and locally dielectric area 12, heavily doped polysilicon emitter region 29 on base and emitter region-spacer medium district, base, heavy doping mono-crystalline emitter 38 under the emitter window that emitter region-spacer medium district, base surrounds, the base region low-resistance metal silicide layer 32 of base region surface, heavily doped polysilicon lifting outer base area 20, contact hole dielectric layer 40, emitter metal electrode 42 and base metal electrode 44.Wherein, base is made up of monocrystalline SiGe base 14 and poly-SiGe base 16; Emitter region-spacer medium district, base is made up of L conformal silicon oxide floor 25 and silicon nitride spacer 26.Base region low-resistance metal silicide layer 32 extends to outside emitter region-spacer medium district, base always.In preferred structure, base region low-resistance metal silicide layer 32 covers poly-SiGe base 16 completely, local complexity monocrystalline SiGe base 14.
Because base region low-resistance metal silicide layer 32 does not extend to outside emitter region-spacer medium district, base in common non-self-aligned device architecture involved by background technology, so base region low-resistance metal silicide layer 32 at least equals the width sum of (consider the horizontal proliferation effect forming impurity in the process of heavy doping mono-crystalline emitter 38, should be slightly less than) thickness of L conformal silicon oxide layer 25, the width of silicon nitride spacer 26 and the first silicon oxide layer 22 with the spacing of heavy doping mono-crystalline emitter 38.Because be limited to etching condition, the width of the first silicon oxide layer 20 can not be less than minimum lithographic alignment spacing, so base region low-resistance metal silicide layer 32 thus can not be very little in minimum lithographic alignment spacing with the pitch-limited of heavy doping mono-crystalline emitter 38, the base resistance R of the common non-self-aligned device therefore involved by background technology
balso just can not be very little, thus make the optimization of device performance be subject to a definite limitation.
Device architecture of the present invention is because being extended to the outside in the emitter region-spacer medium district, base be made up of L conformal silicon oxide floor 25 and silicon nitride spacer 26 through the base region low-resistance metal silicide 32 that silicification reaction generates by metal level 18, thus make base region low-resistance metal silicide layer 32 only equal (consider the horizontal proliferation effect forming impurity in the process of heavy doping mono-crystalline emitter 38, should the be slightly less than) thickness of L conformal silicon oxide layer 25 and the width sum of silicon nitride spacer 26 with the spacing of heavy doping mono-crystalline emitter 38.Be that the thickness of L conformal silicon oxide layer 25 or the width of silicon nitride spacer 26 all have nothing to do with photoetching process, thus can not be limited to and can much smaller than minimum lithographic alignment spacing.So base region low-resistance metal silicide layer 32 just can not be limited to the spacing of heavy doping mono-crystalline emitter 38 and can much smaller than minimum lithographic alignment spacing.Therefore, the device architecture of metal silicide autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor proposed by the invention belongs to self-alignment structure, and the common non-self-aligned device architecture thus compared involved by background technology can obtain less base resistance R
b.And, even the autoregistration device that background technology relates to, often also can only ensure the autoregistration between heavy doping SiGe base and heavy doping mono-crystalline emitter, and minimizing of base region low-resistance metal silicide layer and heavy doping mono-emitter Interval Distance can not be ensured, and the device architecture that the present invention proposes directly ensure that base region low-resistance metal silicide layer 32 and the autoregistration of heavy doping mono-crystalline emitter 38 and minimizing of its spacing, because the sheet resistance of low resistive metal silicide layer is usually much smaller than the sheet resistance of heavy doping SiGe base, even if therefore compared to the autoregistration device involved by background technology, the device that the present invention proposes still can reduce base resistance R further
b, and then can the speed of optimised devices, noise and frequency microwave power-performance further.
The step preparing autoregistration lifting outer base area of the present invention Ge-Si heterojunction bipolar transistor is as follows:
As shown in Figure 1, on Semiconductor substrate (not drawing in figure), prepare the Si epitaxial loayer of the first conduction type.In order to reduce the electric capacity C between base and collector region
bC, recharge in the way of dielectric material or the subregion of the method for selective oxidation in Si epitaxial loayer form local medium district 12 by digging shallow slot.Local medium district 12 is generally silica, but is not limited to this.The Si epitaxial layer region forming remaining first conduction type after local medium district 12 becomes Si collector region 10.
As shown in Figure 2, the SiGe base of the second conduction type is formed by epitaxial growth and in-situ doped method, namely on Si collector region 10, obtain monocrystalline germanium silicon (being generally the multilayer epitaxial material comprising silicon and the germanium silicon) base 14 of the second conduction type, on local medium district 12, obtain poly-SiGe (being generally the multilayer polycrystalline material comprising silicon and the germanium silicon) base 16 of the second conduction type.
As shown in Figure 3, deposit or splash-proofing sputtering metal layer 18, this metal can be but be not limited to be titanium, cobalt or nickel, and thickness is between 5nm to 500nm.
As shown in Figure 4, deposit first polysilicon layer 20, is greater than 10 by its post dose
14/ cm
2ion implantation or in above-mentioned deposition process, adopt in-situ doped method to be the first polysilicon layer 20 of the second conduction type by its heavy doping; Deposit first silicon oxide layer 22 on this first polysilicon layer 20;
As shown in Figure 5, successively removed the mid portion of the first silicon oxide layer 22, first polysilicon layer 20 and metal 18 selectively by photoetching process, form first window 21, expose the mid portion of monocrystalline SiGe base 14 below.Remaining first polysilicon layer forms polysilicon lifting outer base area.
As shown in Figure 6, deposit second silicon oxide layer 24, thickness is between 5nm to 50nm.
As shown in Figure 7, by first deposit one deck silicon nitride and then utilize the method for anisotropic etching the edge of first window 21 formed silicon nitride spacer 26, this silicon nitride spacer 26 width is between 10nm to 500nm.
As shown in Figure 8, under the sheltering of silicon nitride spacer 26, wet etching is utilized to remove the second silicon oxide layer 24 not by part that silicon nitride spacer 26 covers, emitter region-spacer medium the district, base forming L conformal silicon oxide floor 25 and be made up of L conformal silicon oxide floor 25 and silicon nitride spacer 26, open the emitter window 27 surrounded by emitter region-spacer medium district, base, again expose the mid portion of monocrystalline SiGe base 14.
As shown in Figure 9, deposit second polysilicon layer 28, and be greater than 10 by dosage thereafter
14/ cm
2ion implantation or in above-mentioned deposition process, adopt in-situ doped method to be the second polysilicon layer 28 of the first conduction type by its heavy doping.
As shown in Figure 10, successively partial polysilicon layer 28 and part first silicon oxide layer 22 are etched away by photoetching process, form the polysilicon emissioning area 29 of heavily doped first conduction type.
As shown in figure 11, utilize one or many rapid thermal anneal process, metal level 18 is made with poly-SiGe base 16 and with the polysilicon lifting outer base area 20 contacted, silicification reaction to occur with the portion of monocrystalline SiGe base 14 contacted above below, final formation base region low-resistance metal silicide layer 32, this base region low-resistance metal silicide layer 32 can be but be not limited to Titanium silicide, cobalt silicide or nickel silicide.
Meanwhile or prior to or after in above-mentioned metal silicide technology, utilize thermal anneal process or thermal diffusion to advance technique to make the impurity in the polysilicon emissioning area 29 of heavily doped first conduction type form the heavy doping mono-crystalline emitter 38 of the first conduction type by the downward outdiffusion of emitter window.
As shown in figure 12, conventional semiconductor device and integrated circuit postchannel process thereof can be adopted, comprise contact hole dielectric layer deposit, contact hole photoetching and etching and metal level sputtering, photoetching and etching etc., finally complete technological process prepared by device, wherein 40 be respectively emitter metal electrode and base metal electrode for contact hole dielectric layer, 42 and 44.
Consider the present invention to collector electrode lead-out mode without any restriction, in above specific embodiments process chart, therefore all do not demonstrate the extraction electrode of collector region.In fact, if substrate (not shown in FIG.) is the Si wafer of heavily doped first conduction type, collector electrode can be drawn from heavily doped substrate back; If substrate is the Si wafer of the second conduction type, then collector electrode by forming the common process such as heavy doping buried regions and heavy doping collector electrode Sinker of the first conduction type on the second conductivity type substrate, finally utilizes metal connecting line to draw from wafer frontside.
The device preparation technology that the present invention proposes is very simple, therefore possesses the advantage that device fabrication manufacturing process complexity is low, with low cost.
Preferred embodiment: as shown in Fig. 1 to 12, the way recharging dielectric material in the Si epitaxial loayer that Semiconductor substrate is formed by digging shallow slot forms local medium district 12 on surface, and the part not forming local medium district defines Si collector region 10.The material in local medium district 12 is silica.On Si collector region, obtain the monocrystalline SiGe base 14 of the second conduction type of the multilayer epitaxial material comprising silicon and germanium silicon, on local medium district 12, obtain the poly-SiGe base 16 of the second conduction type of the multilayer polycrystalline material comprising silicon and germanium silicon.
Sputtered titanium metal level 18; Deposit in-situ doped the first polysilicon layer 20 obtaining heavily doped second conduction type; Deposit first silicon oxide layer 22 on resulting structures.Successively removed the mid portion of the first silicon oxide layer 22, first polysilicon layer 20 and metal level 18 by photoetching process selectively, form first window 21, expose the mid portion of monocrystalline SiGe base 14 below.Remaining first polysilicon layer is referred to as polysilicon lifting outer base area.The second silicon oxide layer 24 that deposit 10nm is thick.By first deposit one deck silicon nitride and then utilize the method for anisotropic etching the edge of window formed silicon nitride spacer 26, this lateral wall width is 100nm.
Under the sheltering of silicon nitride spacer 26, utilize wet etching to remove the second silicon oxide layer 24 not by the part that silicon nitride spacer 26 covers, thus open emitter window, again expose the mid portion of monocrystalline SiGe base 14.Deposit second polysilicon layer 28, and be 5 × 10 by dosage thereafter
15/ cm
2ion implantation be the second polysilicon layer 28 of the first conduction type by its heavy doping.Successively part second polysilicon layer 28 and part first silicon oxide layer 22 are etched away by photoetching process, form the polysilicon emissioning area 29 of heavily doped first conduction type.
Utilize repeatedly rapid thermal anneal process to make metal level with poly-SiGe base 16 and with the polysilicon lifting outer base area 20 contacted, silicification reaction occur with the portion of monocrystalline SiGe base 14 contacted above below, form low resistance Titanium silicide layer 32.Meanwhile, thermal anneal process is utilized to make the impurity in the polysilicon emissioning area 29 of heavily doped first conduction type form the heavy doping mono-crystalline emitter 38 of the first conduction type by the downward outdiffusion of emitter window.Deposit hole dielectric layer 40, completes contact hole photoetching and etching; Complete the sputtering of interconnecting metal layer, photoetching and etching, form emitter metal electrode 42 and base metal electrode 44.Finally complete technological process prepared by device.
Above; be only preferred embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, the protection range that protection scope of the present invention should define with claim is as the criterion.
Claims (9)
1. an autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor, described transistor mainly comprises Si collector region, local medium district, base above Si collector region and locally dielectric area, heavily doped polysilicon emitter region above base and emitter region-spacer medium district, base, heavy doping mono-crystalline emitter under the emitter window that emitter region-spacer medium district, base surrounds, the base region low-resistance metal silicide layer of base region surface, heavily doped polysilicon lifting outer base area above base region low-resistance metal silicide layer, contact hole dielectric layer, emitter metal electrode and base metal electrode, wherein, described base is made up of monocrystalline SiGe base and poly-SiGe base, described emitter region-spacer medium district, base is made up of L conformal silicon oxide floor and silicon nitride spacer, it is characterized in that: described base region low-resistance metal silicide layer extends to outside emitter region-spacer medium district, base always, the lower surface of described base region low-resistance metal silicide layer is lower than the lower surface of described heavily doped polysilicon emitter region.
2. an autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method, is characterized in that, described method at least comprises the steps:
The Si epitaxial loayer of 2.1 preparation the first conduction types, in gained Si epitaxial loayer, form local medium district, the part not forming local medium district in Si epitaxial loayer is Si collector region;
2.2 SiGe base of preparing the second conduction type above resulting structures, form monocrystalline SiGe base in the position of corresponding Si collector region, form poly-SiGe base in the position in corresponding local medium district;
2.3 deposits or splash-proofing sputtering metal layer;
2.4 deposit first polysilicon layers, form the first polysilicon layer of heavily doped second conduction type; Deposit first silicon oxide layer on described first polysilicon layer;
2.5 mid portions successively removing the first silicon oxide layer, the first polysilicon layer and metal level selectively, form first window, expose the mid portion on surface, monocrystalline SiGe base; Remaining first polysilicon layer forms polysilicon lifting outer base area;
2.6 deposit second silicon oxide layers;
2.7 deposit silicon nitride layers, recycling anisotropic etching method forms silicon nitride spacer at first window inward flange;
2.8 remove not by the second silicon oxide layer that silicon nitride spacer covers, emitter region-spacer medium the district, base forming L conformal silicon oxide floor and be made up of L conformal silicon oxide floor and silicon nitride spacer, open the emitter window that described emitter region-spacer medium district, base surrounds, expose the mid portion on surface, monocrystalline SiGe base;
2.9 deposit second polysilicon layers, and the polysilicon layer by described second polysilicon layer heavy doping being the first conduction type;
Part second polysilicon layer and part first silicon oxide layer etch away by 2.10, form the polysilicon emissioning area of heavily doped first conduction type;
There is silicification reaction and obtain base region low-resistance metal silicide layer in the poly-SiGe base that 2.11 metal levels contact with it respectively, portion of monocrystalline SiGe base and polysilicon lifting outer base area; Impurity in the polysilicon emissioning area of heavily doped first conduction type that step 2.10 is formed forms the heavy doping mono-crystalline emitter of the first conduction type by the downward outdiffusion of emitter window;
2.12 deposit hole dielectric layers, prepare contact hole, draw emitter metal electrode and base metal electrode.
3. autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method according to claim 2, is characterized in that, the method preparing local medium district in step 2.1 in Si epitaxial loayer is that grooving recharges dielectric material or selective oxidation.
4. autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method according to claim 2, is characterized in that, in step 2.3, the material of metal level is the one in titanium, cobalt or nickel.
5. autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method according to claim 2, it is characterized in that, in step 2.6, the thickness of the second silicon oxide layer is between 5nm to 50nm.
6. autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method according to claim 2, it is characterized in that, in step 2.7, the formation method of silicon nitride spacer is that first deposit silicon nitride carries out anisotropic etching again, and the width of described side wall is between 10nm to 500nm.
7. autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method according to claim 2, it is characterized in that, be the method for the first conductivity type polysilicon layer by described polysilicon layer heavy doping in step 2.9 be adopt in-situ doped method in depositing polysilicon layer process, or adopt dosage to be greater than 10 after the deposition
14/ cm
2the method of ion implantation.
8. autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method according to claim 2, is characterized in that, the method forming base region low-resistance metal silicide layer in step 2.11 is for utilizing once or repeatedly rapid thermal anneal process.
9. autoregistration lifting outer base area Ge-Si heterojunction bipolar transistor preparation method according to claim 2, it is characterized in that, in step 2.11 heavily doped first conduction type polysilicon emissioning area in the impurity method that formed the heavy doping mono-crystalline emitter of the first conduction type by the downward outdiffusion of emitter window be utilize the one or many rapid thermal anneal process forming base region low-resistance metal silicide layer, or utilize rapid thermal annealing before this or afterwards or other thermal diffusions to advance technique.
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| US13/625,233 US20130313614A1 (en) | 2012-05-22 | 2012-09-24 | METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME |
| US14/189,106 US9202901B2 (en) | 2012-05-22 | 2014-02-25 | Metal silicide self-aligned SiGe heterojunction bipolar transistor and method of forming the same |
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