CN105119782A - New type bit error rate test equipment with full rate 1.25G to 64 G capable of arbitrarily setting test speed - Google Patents
New type bit error rate test equipment with full rate 1.25G to 64 G capable of arbitrarily setting test speed Download PDFInfo
- Publication number
- CN105119782A CN105119782A CN201510642688.8A CN201510642688A CN105119782A CN 105119782 A CN105119782 A CN 105119782A CN 201510642688 A CN201510642688 A CN 201510642688A CN 105119782 A CN105119782 A CN 105119782A
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- China
- Prior art keywords
- circuit
- detector
- clock source
- error rate
- test equipment
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
- H04B10/079—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
- H04B10/0795—Performance monitoring; Measurement of transmission parameters
- H04B10/07953—Monitoring or measuring OSNR, BER or Q
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
Abstract
The invention discloses new type bit error rate test equipment with full rate 1.25G to 64 G capable of arbitrarily setting test speed, the problems that multi-band test cannot be realized and the cost is high in the prior art are solved. The new type bit error rate test equipment comprises an MCU (Microprogrammed Control Unit), a USB (Universal Serial Bus) interface, a pseudo random type generator and detector, a clock source circuit, a signal shaping circuit, and a power circuit, wherein the MCU, the clock source circuit, the signal shaping circuit are respectively connected with the pseudo random type generator and detector; the MCU further is connected with the USB interface, and is communicated with an external computer through the USB interface; the power circuit is used for supplying power to the MCU, the clock source circuit, the signal shaping circuit and the pseudo random type generator and detector. The new type bit error rate test equipment provided by the invention can meet a test of sending and receiving ends of a mainstream optical communication module in the current market, only a DCA and an attenuator are configured for completing all index tests before the shipment of an optical module, and the production cost of the optical module is effectively lowered.
Description
Technical field
The present invention relates to a kind of full rate 1.25G-64G, the novel error rate test equipment of test rate can be set arbitrarily.
Background technology
A lot of Error Detector in the market, it is all but a frequency, continuous arbitrary velocity can not be done, performance can not meet the client in this frequency ranges all, need to buy multiple devices, hardware cost causes waste, and also will programme respectively to different equipment in the process of automated production, increases construction cycle and cost.
Summary of the invention
The object of the present invention is to provide a kind of full rate 1.25G-64G, the novel error rate test equipment of test rate can be set arbitrarily, solve prior art and cannot realize multiband test, the problem that cost is higher.
To achieve these goals, the technical solution used in the present invention is as follows:
A kind of full rate 1.25G-64G, can set arbitrarily the novel error rate test equipment of test rate, comprise MCU controller, USB interface, pseudorandom pattern generator and detector, clock source circuit, signal transformation circuit, power circuit;
Wherein, MCU controller, clock source circuit, signal transformation circuit are connected with detector with pseudorandom pattern generator respectively;
Described MCU controller is also connected with USB interface, and is communicated with outer computer by USB interface;
Described power circuit is MCU controller, clock source circuit, signal transformation circuit, pseudorandom pattern generator and detector provide power supply.
Further, the reference clock frequency of described clock source circuit is 0 ~ 200MHz.That is clock source circuit can produce any clock frequency of 0 ~ 200MHz.
Again further, described clock source circuit adopts SI5338A chip, and signal transformation circuit adopts GN2017 chip, and pseudorandom pattern generator and detector adopt GT1706 chip.Wherein, pseudorandom pattern generator and detector have multi-channel data transmission function, and signal transformation circuit has multi-channel data transmission function.
The present invention compared with prior art, has the following advantages and beneficial effect:
The present invention is a kind of full rate 1.25G-64G, can set arbitrarily the novel error rate test equipment of test rate, can regulate continuously in this frequency range.Meet the sending and receiving end test of main flow optical communications module in the market, a DCA and attenuator of only need arranging in pairs or groups just can complete all index tests before optical module shipment, effectively reduces the production cost of optical module.In addition, the present invention also can be used for the vision signal of other high speed data transfer, the test of the products such as broadcast.
Accompanying drawing explanation
Fig. 1 is system block diagram of the present invention.
Fig. 2 is clock source circuit schematic diagram in the present invention.
Fig. 3 is signal transformation circuit schematic diagram in the present invention.
Fig. 4 is the circuit theory diagrams of pseudorandom pattern generator and detector in the present invention.
Fig. 5 is the circuit theory diagrams of MCU controller in the present invention.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described, and embodiments of the present invention include but not limited to the following example.
Embodiment
As shown in Fig. 1 ~ 5, a kind of full rate 1.25G-64G, can set arbitrarily the novel error rate test equipment of test rate, comprise MCU controller, USB interface, pseudorandom pattern generator and detector, clock source circuit, signal transformation circuit, power circuit;
Wherein, MCU controller, clock source circuit, signal transformation circuit are connected with detector with pseudorandom pattern generator respectively;
Described MCU controller is also connected with USB interface, and is communicated with outer computer by USB interface;
Described power circuit is MCU controller, clock source circuit, signal transformation circuit, pseudorandom pattern generator and detector provide power supply.
In addition, the reference clock frequency of described clock source circuit is 0 ~ 200MHz.Described clock source circuit adopts SI5338A chip, and signal transformation circuit adopts GN2017 chip, and pseudorandom pattern generator and detector adopt GT1706 chip.
Operation principle of the present invention is as follows:
Clock source circuit produces any clock frequency of 0 ~ 200MHz, and pseudorandom pattern generator and detector carry out arbitrary integer frequency adjustment doubly according to the clock of input, the bandwidth Design that but chip ensures is 1.25G ~ 64G, so within the scope of this, the Error detection of arbitrary velocity within the scope of this can be accomplished as required; And because pseudorandom pattern generator and detector are multichannel designs, employ 4 passages in the present invention, detect so can do 4 tunnels simultaneously, can 40G(4 × 16G be met) test of module, also can use wherein any a few road, each passage works alone, signal transformation circuit also has 4 tunnels accordingly, every road signal is independently adjusted, can shake be reduced, the rise and fall time of adjustment signal and signal output amplitude.In addition, power circuit is by outside 5V DC power supply input, the power supply that on generation equipment, all parts need.
When reality uses, MCU controller controls above-mentioned each parts, simultaneously by USB interface and compunication, realizes automatic test.
What deserves to be explained is, the present invention can realize detecting the error rate of different rates, and one multiplex, does not need to be equipped with special tester to each speed, greatly reduces input cost.
According to above-described embodiment, just the present invention can be realized well.What deserves to be explained is; under prerequisite based on said structure design, for solving same technical problem, even if some making on the invention are without substantial change or polishing; the essence of the technical scheme adopted is still the same with the present invention, therefore it also should in protection scope of the present invention.
Claims (3)
1. a full rate 1.25G-64G, can set arbitrarily the novel error rate test equipment of test rate, it is characterized in that, comprise MCU controller, USB interface, pseudorandom pattern generator and detector, clock source circuit, signal transformation circuit, power circuit;
Wherein, MCU controller, clock source circuit, signal transformation circuit are connected with detector with pseudorandom pattern generator respectively;
Described MCU controller is also connected with USB interface, and is communicated with outer computer by USB interface;
Described power circuit is MCU controller, clock source circuit, signal transformation circuit, pseudorandom pattern generator and detector provide power supply.
2. a kind of full rate 1.25G-64G according to claim 1, can set arbitrarily the novel error rate test equipment of test rate, it is characterized in that, the reference clock frequency of described clock source circuit is 0 ~ 200MHz.
3. a kind of full rate 1.25G-64G according to claim 2, the novel error rate test equipment of test rate can be set arbitrarily, it is characterized in that, described clock source circuit adopts SI5338A chip, signal transformation circuit adopts GN2017 chip, and pseudorandom pattern generator and detector adopt GT1706 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510642688.8A CN105119782A (en) | 2015-09-30 | 2015-09-30 | New type bit error rate test equipment with full rate 1.25G to 64 G capable of arbitrarily setting test speed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510642688.8A CN105119782A (en) | 2015-09-30 | 2015-09-30 | New type bit error rate test equipment with full rate 1.25G to 64 G capable of arbitrarily setting test speed |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105119782A true CN105119782A (en) | 2015-12-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510642688.8A Pending CN105119782A (en) | 2015-09-30 | 2015-09-30 | New type bit error rate test equipment with full rate 1.25G to 64 G capable of arbitrarily setting test speed |
Country Status (1)
| Country | Link |
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| CN (1) | CN105119782A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113259000A (en) * | 2021-07-13 | 2021-08-13 | 深圳市力子光电科技有限公司 | Optical module testing arrangement |
Citations (5)
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|---|---|---|---|---|
| US20030198116A1 (en) * | 2002-04-15 | 2003-10-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device equipped with control circuit for controlling memory cell array in non-normal operation mode |
| US20050135259A1 (en) * | 2000-06-05 | 2005-06-23 | Sami Yazdi | Hand-held electronic tester for telecommunications networks |
| CN1688137A (en) * | 2005-04-14 | 2005-10-26 | 武汉电信器件有限公司 | 155 M bit error code analysis tester based on field programmable gate array |
| CN104539356A (en) * | 2014-11-28 | 2015-04-22 | 武汉电信器件有限公司 | 10G multifunctional test system |
| CN205123762U (en) * | 2015-09-30 | 2016-03-30 | 成都瑞索高创光电技术有限公司 | 1. 25G -64G novel error rate test equipment of test speed can be set for wantonly to full rate |
-
2015
- 2015-09-30 CN CN201510642688.8A patent/CN105119782A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050135259A1 (en) * | 2000-06-05 | 2005-06-23 | Sami Yazdi | Hand-held electronic tester for telecommunications networks |
| US20030198116A1 (en) * | 2002-04-15 | 2003-10-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device equipped with control circuit for controlling memory cell array in non-normal operation mode |
| CN1688137A (en) * | 2005-04-14 | 2005-10-26 | 武汉电信器件有限公司 | 155 M bit error code analysis tester based on field programmable gate array |
| CN104539356A (en) * | 2014-11-28 | 2015-04-22 | 武汉电信器件有限公司 | 10G multifunctional test system |
| CN205123762U (en) * | 2015-09-30 | 2016-03-30 | 成都瑞索高创光电技术有限公司 | 1. 25G -64G novel error rate test equipment of test speed can be set for wantonly to full rate |
Non-Patent Citations (1)
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| 范成相: "《基于VSC8248的高速误码测试系统的设计与实现》", 《中国优秀硕士论文论文全文数据库（电子期刊）信息科技辑》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113259000A (en) * | 2021-07-13 | 2021-08-13 | 深圳市力子光电科技有限公司 | Optical module testing arrangement |
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| PB01 | Publication | ||
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151202 |