CN202041645U - Pseudo code generator - Google Patents
Pseudo code generator Download PDFInfo
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- CN202041645U CN202041645U CN2011200978745U CN201120097874U CN202041645U CN 202041645 U CN202041645 U CN 202041645U CN 2011200978745 U CN2011200978745 U CN 2011200978745U CN 201120097874 U CN201120097874 U CN 201120097874U CN 202041645 U CN202041645 U CN 202041645U
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- control circuit
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Abstract
The utility model relates to pseudo code generator which comprises an FPGA (Field Programmable Gate Array) circuit. The internal circuit structure of the FPGA circuit is as follows: a plurality of pseudo code generating circuits are connected in parallel; a command analysis control circuit and a address decoder are connected with pseudo code generating circuits (1 to n) respectively; and the command analysis control circuit and the address decoder are connected. The utility model has the advantages of simple circuit, flexibility in use, random configuration of pseudo code types and rates, multi-way output, and settable phase relation among the multiple ways.
Description
Technical field
The utility model relates to the pseudo-code generating apparatus of a kind of satellite navigation communications field, particularly a kind of pseudo-code generator, because its control is pseudo-code type, way, phase place, and the particularly compatible situation about receiving of multimode system.
Background technology
In the satellite navigation communication process, can run into the compatible situation about receiving of multimode system.Adopt a plurality of different pseudo-code generators can increase system cost, reduce system's switching efficiency.Common pseudo-code generator has characteristics such as type is fixed, single channel is exported, phase place is fixing usually.Configuration mode is more single, is difficult to realize the collaborative work of polymorphic type multichannel leggy.When the collaborative work of needs polymorphic type multichannel leggy pseudo-code signal, just can not be suitable for.
Summary of the invention
In view of the deficiency that prior art exists, the utility model provides a kind of pseudo-code type configurable, and duplex cooperation work, the pseudo-code generator that the phase place between the multichannel output can freely be set.
The utility model for achieving the above object, the technical scheme of being taked is: a kind of pseudo-code generator is characterized in that: comprise the FPGA circuit, the internal circuit configuration of described FPGA circuit is: the polylith pseudo-code produces the circuit parallel connection; Command analysis control circuit, address decoder produce circuit 1 ~ n with pseudo-code respectively and are connected; The command analysis control circuit is connected with address decoder.It is identical circuit that described pseudo-code produces circuit 1 ~ n, pseudo-code produces circuit connecting relation: the shift register group I is connected with the feedback control circuit I, the shift register group II is connected with the feedback control circuit II, and shift register group I, shift register group II, PN-ROM are in parallel; The counter group connects shift register group I, shift register group II, PN-ROM respectively; Shift register group I, shift register group II, PN-ROM and subcarrier maker are connected with selector switch respectively.The annexation of described command analysis control circuit is: initial phase control circuit, subcarrier control circuit, pseudo-code polynomial control circuit, counter are in parallel; Initial phase control circuit, subcarrier control circuit, pseudo-code polynomial control circuit, counter are connected with the control register group respectively.
Characteristics of the present utility model: 1, circuit is simple; 2, use flexibly, can arbitrarily dispose pseudo-code type and speed; 3, multichannel output can be provided with the phase relation between the multichannel.
Description of drawings
Fig. 1 is that circuit of the present utility model connects block diagram.
Fig. 2 is a port output synoptic diagram of the present utility model.
Fig. 3 is the connection block diagram of pseudo-code generation circuit of the present utility model.
Fig. 4 is the connection block diagram of command analysis control circuit of the present utility model.
Embodiment
As shown in Figure 1, pseudo-code generator comprises the FPGA circuit, and gate array can be compiled in the FPGA(scene) internal circuit configuration of circuit is: the polylith pseudo-code produces the circuit parallel connection; Command analysis control circuit, address decoder produce circuit 1 ~ n with pseudo-code respectively and are connected; The command analysis control circuit is connected with address decoder.The command analysis control circuit receives the pseudo-code configuration-direct, and pseudo-code generation circuit produces the pseudo-code of polymorphic type multichannel leggy according to configuration information.Can export multiple pseudo-code type according to exterior arrangement information, phase place, frequency are controlled.The external RAM that this circuit can be used as controller (as MCU) uses, and adopts non-multiplex mode to connect.Controller can be operated quick operation FPGA internal register as the operation external RAM like this.Configuration and that speed is set is fast.
As shown in Figure 2, output n road pseudo-code signal.Form the correspondence with foreign country port by address, data and write signal, convenient configuration and setting.Among the figure: PN1 ~ PNn is pseudo-code signal output, A0～7 address signals, D0～7 data-signals, WR write signal.
As shown in Figure 3, it is identical circuit that pseudo-code produces circuit 1 ~ n, pseudo-code produces circuit connecting relation: the shift register group I is connected with the feedback control circuit I, and the shift register group II is connected with the feedback control circuit II, and shift register group I, shift register group II, PN-ROM are in parallel; The counter group connects shift register group I, shift register group II, PN-ROM respectively; Shift register group I, shift register group II, PN-ROM and subcarrier maker are connected with selector switch respectively.Pseudo-code generation circuit, it is made of two shift register group, shift register group produces different pseudo-codes according to different initial phases, polynomial construction, selector switch is selected computing according to different generating modes and subcarrier pattern to pseudo-code information, and operation result is exported according to required frequency.Because the public counter of a plurality of pseudo-code generation circuits is made time reference, so between the multichannel output precedence relationship can be set.
As shown in Figure 4, the annexation of command analysis control circuit is: extraneous control information is connected successively with initial phase control circuit, subcarrier control circuit, pseudo-code polynomial control circuit, counter; Initial phase control circuit, subcarrier control circuit, pseudo-code polynomial control circuit, counter are connected with the control register group.The command analysis control circuit comprises parser circuitry such as subcarrier pattern, initial phase, polynomial construction, configuration information is converted into pseudo-code generates control.
These circuit exterior arrangement data resolvedly go out specifying informations such as subcarrier pattern, initial phase, polynomial construction at this, and control pseudo-code generation circuit by special register.
Claims (3)
1. pseudo-code generator, it is characterized in that: comprise the FPGA circuit, the internal circuit configuration of described FPGA circuit is: the polylith pseudo-code produces circuit 1 ~ n parallel connection; Command analysis control circuit, address decoder produce circuit 1 ~ n with pseudo-code respectively and are connected; The command analysis control circuit is connected with address decoder.
2. pseudo-code generator according to claim 1, it is characterized in that: it is identical circuit that described pseudo-code produces circuit 1 ~ n, pseudo-code produces circuit connecting relation: the shift register group I is connected with the feedback control circuit I, the shift register group II is connected with the feedback control circuit II, and shift register group I, shift register group II, PN-ROM are in parallel; The counter group connects shift register group I, shift register group II, PN-ROM respectively; Shift register group I, shift register group II, PN-ROM and subcarrier maker are connected with selector switch respectively.
3. pseudo-code generator according to claim 1 is characterized in that: the annexation of described command analysis control circuit is: initial phase control circuit, subcarrier control circuit, pseudo-code polynomial control circuit, counter are in parallel; Initial phase control circuit, subcarrier control circuit, pseudo-code polynomial control circuit, counter are connected with the control register group respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200978745U CN202041645U (en) | 2011-04-06 | 2011-04-06 | Pseudo code generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011200978745U CN202041645U (en) | 2011-04-06 | 2011-04-06 | Pseudo code generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202041645U true CN202041645U (en) | 2011-11-16 |
Family
ID=44969083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011200978745U Expired - Fee Related CN202041645U (en) | 2011-04-06 | 2011-04-06 | Pseudo code generator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202041645U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103675862A (en) * | 2013-11-29 | 2014-03-26 | 航天恒星科技有限公司 | Method for generating satellite-borne multi-frequency and multi-mode universal pseudo-codes with configurable relevant separation distances |
| CN112272052A (en) * | 2020-10-13 | 2021-01-26 | 中国人民解放军63921部队 | Equipment and method for multiplexing pseudo codes of large-scale satellite constellation |
-
2011
- 2011-04-06 CN CN2011200978745U patent/CN202041645U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103675862A (en) * | 2013-11-29 | 2014-03-26 | 航天恒星科技有限公司 | Method for generating satellite-borne multi-frequency and multi-mode universal pseudo-codes with configurable relevant separation distances |
| CN103675862B (en) * | 2013-11-29 | 2015-08-19 | 航天恒星科技有限公司 | The general pseudo-code generating method of spaceborne multi-frequency multi-mode that a kind of relevant spacing can be joined |
| CN112272052A (en) * | 2020-10-13 | 2021-01-26 | 中国人民解放军63921部队 | Equipment and method for multiplexing pseudo codes of large-scale satellite constellation |
| CN112272052B (en) * | 2020-10-13 | 2022-04-19 | 中国人民解放军63921部队 | Equipment and method for multiplexing pseudo codes of large-scale satellite constellation |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: TIANJIN KANGQIAO ENERGY-SAVING TECHNOLOGY CO., LTD Free format text: FORMER OWNER: TIANJIN PHOTOELECTRIC TELECOM TECHNOLOGY CO., LTD. Effective date: 20120807 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 300211 HEXI, TIANJIN TO: 300384 NANKAI, TIANJIN |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20120807 Address after: 300384 Tianjin City Guangdong Huayuan Industrial Zone Road No. 6, room 502-3 Patentee after: Tianjin Cambridge Energy Saving Technology Co., Ltd. Address before: 300211 No. six, Taishan Road, Tianjin, Hexi District Patentee before: Tianjin Photoelectric Telecom Technology Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111116 Termination date: 20150406 |
|
| EXPY | Termination of patent right or utility model |