CN202041645U - pseudo code generator - Google Patents

Abstract

The utility model relates to pseudo code generator which comprises an FPGA (Field Programmable Gate Array) circuit. The internal circuit structure of the FPGA circuit is as follows: a plurality of pseudo code generating circuits are connected in parallel; a command analysis control circuit and a address decoder are connected with pseudo code generating circuits (1 to n) respectively; and the command analysis control circuit and the address decoder are connected. The utility model has the advantages of simple circuit, flexibility in use, random configuration of pseudo code types and rates, multi-way output, and settable phase relation among the multiple ways.

Description

pseudo code generator

technical field

The utility model relates to a pseudo-code generating device in the field of satellite navigation and communication, in particular to a pseudo-code generator, which controls the pseudo-code type, channel number and phase, and especially relates to the situation of multi-mode system compatible reception.

Background technique

In the process of satellite navigation communication, it will encounter the situation of compatible reception of multi-mode system. Using multiple different pseudocode generators will increase system cost and reduce system switching efficiency. Common pseudocode generators usually have the characteristics of fixed type, single output, and fixed phase. The configuration method is relatively simple, and it is difficult to realize multi-type, multi-channel and multi-phase cooperative work. There is no way to apply when multi-type multi-channel multi-phase pseudo-code signals are required to work together.

Contents of the invention

In view of the shortcomings of the existing technology, the utility model provides a pseudo-code generator with configurable pseudo-code type, multi-channel cooperative work, and the phase between multiple outputs can be set freely.

In order to achieve the above object, the utility model adopts the technical scheme as follows: a pseudo-code generator, characterized in that it comprises an FPGA circuit, and the internal circuit structure of the FPGA circuit is: a plurality of pseudo-code generation circuits are connected in parallel; command analysis The control circuit and the address decoder are respectively connected with pseudo code generating circuits 1~n; the command analysis control circuit is connected with the address decoder. The pseudo-code generation circuits 1~n are the same circuits, and the connection relationship of the pseudo-code generation circuits is: the shift register group I is connected to the feedback control circuit I, the shift register group II is connected to the feedback control circuit II, and the shift register group I is connected to the feedback control circuit II. Ⅰ, shift register group II, and PN-ROM are connected in parallel; the counter group is respectively connected to shift register group I, shift register group II, and PN-ROM; shift register group I, shift register group II, PN-ROM and The subcarrier generators are respectively connected to the selectors. The connection relation of described order analysis control circuit is: initial phase control circuit, subcarrier control circuit, pseudocode polynomial control circuit, counter are connected in parallel; Initial phase control circuit, subcarrier control circuit, pseudocode polynomial control circuit, counter are respectively connected with The control register set is connected.

The utility model features: 1. The circuit is simple; 2. It is flexible to use, and the type and rate of the pseudo-code can be configured at will; 3. Multi-channel output, and the phase relationship between multiple channels can be set.

Description of drawings

Fig. 1 is the circuit connection block diagram of the utility model.

Fig. 2 is a schematic diagram of port output of the present invention.

Fig. 3 is a connection block diagram of the pseudo code generating circuit of the present invention.

Fig. 4 is a connection block diagram of the command analysis control circuit of the present invention.

Detailed ways

As shown in Figure 1, the pseudo-code generator includes an FPGA circuit. The internal circuit structure of the FPGA (Field Programmable Gate Array) circuit is: multiple pseudo-code generation circuits are connected in parallel; the command analysis control circuit and the address decoder are respectively connected to the pseudo-code The code generation circuit 1~n is connected; the command analysis control circuit is connected with the address decoder. The command analysis control circuit receives the pseudo-code configuration instruction, and the pseudo-code generation circuit generates multi-type, multi-channel and multi-phase pseudo-codes according to the configuration information. A variety of pseudocode types can be output according to external configuration information, and the phase and frequency are controllable. This circuit can be used as an external RAM of a controller (such as an MCU) and is connected in a non-multiplexed manner. In this way, the controller can operate and quickly operate FPGA internal registers like operating external RAM. Configuration and setup are fast.

As shown in Figure 2, n channels of pseudo-code signals are output. The external communication port is composed of address, data and write signal, which is convenient for configuration and setting. In the figure: PN1~PNn are pseudo code signal output, A0~7 address signal, D0~7 data signal, WR write signal.

As shown in Figure 3, the pseudo-code generation circuits 1~n are the same circuits, and the connection relationship of the pseudo-code generation circuits is: the shift register group I is connected to the feedback control circuit I, the shift register group II is connected to the feedback control circuit II, Shift register group I, shift register group II, and PN-ROM are connected in parallel; counter groups are respectively connected to shift register group I, shift register group II, and PN-ROM; shift register group I, shift register group II, The PN-ROM and the subcarrier generator are respectively connected to the selector. Pseudo-code generation circuit, which is composed of two shift register groups. The shift register groups generate different pseudo-codes according to different initial phases and polynomial structures. The selector performs pseudo-code information according to different generation methods and subcarrier types. Select the operation, and the operation result will be output according to the required frequency. Since multiple pseudo-code generating circuits share a counter as a time reference, a sequential relationship can be set between multiple outputs.

As shown in Figure 4, the connection relationship of the command analysis control circuit is: the external control information is connected with the initial phase control circuit, the subcarrier control circuit, the pseudo code polynomial control circuit, and the counter in sequence; the initial phase control circuit, the subcarrier control circuit, the pseudo The code polynomial control circuit, the counter and the control register group are connected. The command analysis control circuit includes analysis circuits such as subcarrier type, initial phase, polynomial structure, etc., and converts configuration information into pseudo code generation control.

The external configuration data of the circuit is analyzed to obtain specific information such as subcarrier type, initial phase, polynomial structure, etc., and the pseudo code generation circuit is controlled through a special register.

Claims (3)

1. a kind of pseudo-code generator, it is characterized in that: comprise FPGA circuit, the internal circuit structure of described FPGA circuit is: many pieces of pseudo-code generation circuit 1～n are connected in parallel; The code generation circuit 1~n is connected; the command analysis control circuit is connected with the address decoder. 2. The pseudo-code generator according to claim 1, characterized in that: the pseudo-code generating circuits 1 to n are identical circuits, and the pseudo-code generating circuit connection relationship is: shift register group I and feedback control circuit I Connection, shift register group II is connected with feedback control circuit II, shift register group I, shift register group II, and PN-ROM are connected in parallel; counter groups are respectively connected to shift register group I, shift register group II, PN-ROM ROM; shift register group I, shift register group II, PN-ROM and subcarrier generator are respectively connected to the selector. 3. pseudo-code generator according to claim 1, is characterized in that: the connection relation of described order analysis control circuit is: initial phase control circuit, subcarrier control circuit, pseudo-code polynomial control circuit, counter are connected in parallel; The phase control circuit, the subcarrier control circuit, the pseudo code polynomial control circuit and the counter are respectively connected with the control register group.

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