CN108156716B

CN108156716B - Control circuit, method and device for flashing back multiple LED lamps

Info

Publication number: CN108156716B
Application number: CN201810083790.2A
Authority: CN
Inventors: 仲维续; 陈孟邦; 郑海文; 蔡荣怀; 卢玉玲; 乔世成; 邹云根; 张丹丹; 雷先再; 曹进伟; 林丹
Original assignee: Zongren Technology Pingtan Co ltd
Current assignee: Zongren Technology Pingtan Co ltd
Priority date: 2018-01-29
Filing date: 2018-01-29
Publication date: 2024-03-19
Anticipated expiration: 2038-01-29
Also published as: CN108156716A

Abstract

The invention is suitable for the technical field of flash lamp circuits, and provides a control circuit, a method and a device for back flash of a plurality of LED lamps. The circuit comprises a frequency division module, a signal output module and a control module, wherein the frequency division module is used for obtaining a clock signal of a clock signal source, performing frequency division processing on the clock signal to obtain a frequency division signal, and sending the frequency division signal to the signal output module connected with the current LED lamp according to the number of the flicker periods of the current LED lamp; the plurality of signal output modules are connected with the plurality of LED lamps in a one-to-one correspondence manner; each signal output module carries out combination logic operation on the frequency division signals to obtain high-level signals and sends the high-level signals to the corresponding connected LED lamps; and the resetting module is used for sending a resetting signal to the frequency dividing module when the period number of the clock signal is larger than the total number of the flashing periods of the LED lamp, so that the frequency dividing module resets the current frequency dividing signal. The invention can realize the back flashing of a plurality of LED lamps, eliminates the phenomenon that a flashing circuit always flashes twice repeatedly at the head and the tail lamps in work, ensures that the back flashing of the plurality of LED lamps is smoother, and improves the user experience.

Description

Control circuit, method and device for flashing back multiple LED lamps

Technical Field

The invention belongs to the technical field of flash lamp circuits, and particularly relates to a control circuit, a method and a device for back flashing of a plurality of LED (Light Emitting Diode ) lamps.

Background

With the rapid development of the LED industry in the world in recent years, the LED landscaping illumination is paid more attention to, and the change forms of the LED lamps are also various, such as meteor change, flow display, jump, shallow change, seven-color change, back and forth flow change and the like, so that better sceneries are brought to the city at night.

In general, a common back-and-forth flashing LED lamp control circuit always appears in the process of repeatedly flashing the head lamp and the tail lamp twice, so that the change effect of back-and-forth flashing is poor.

Disclosure of Invention

In view of the above, the embodiment of the invention provides a control circuit, a method and a device for back flashing of a plurality of LED lamps, so as to solve the problem that in the prior art, a flashing lamp circuit always flashes twice repeatedly at the head and tail lamps during operation.

A first aspect of an embodiment of the present invention provides a control circuit for flashing a plurality of LED lamps, including: the device comprises a frequency division module, a plurality of signal output modules and a reset module;

the frequency dividing module is suitable for being connected with a clock signal source and also connected with a plurality of signal output modules, and is used for obtaining clock signals of the clock signal source, carrying out frequency dividing processing on the clock signals to obtain frequency dividing signals, and sending the frequency dividing signals to the signal output modules connected with the current LED lamps according to the number of the flicker periods of the current LED lamps;

The signal output modules are suitable for being connected with the LED lamps in a one-to-one correspondence manner;

each signal output module is used for carrying out combination logic operation on the frequency division signals to obtain high-level signals and sending the high-level signals to the corresponding connected LED lamps;

and the reset module is connected with the frequency division module and is used for sending a reset signal to the frequency division module when the period number of the clock signal is greater than the total number of the flashing periods of the LED lamp, so that the frequency division module resets the current frequency division signal.

Optionally, the frequency dividing module includes a plurality of frequency dividers;

the number of the frequency dividers is related to the number of the signal output modules: 2 ^K ≥2N-2；

The number of the frequency dividers is the minimum integer of K, and the number of the signal output modules is N.

Optionally, the plurality of frequency dividers are sequentially connected, the positive output end of the former frequency divider is connected with the first clock input end of the next frequency divider, and the negative output end of the former frequency divider is connected with the second clock input end of the next frequency divider; the positive output ends and the negative output ends of the frequency dividers are also connected with the signal output module;

the signal input ends of the frequency dividers are connected with the reset module;

Wherein the first clock input and the second clock input of the first of said frequency dividers are each adapted to be connected to said clock signal source.

Optionally, the signal output module correspondingly connected to the first LED lamp and the signal output module correspondingly connected to the last LED lamp both include a first logic gate;

the input end of the first logic gate is connected with the frequency dividing module, and the output end of the first logic gate is suitable for being connected with a corresponding LED lamp;

the signal output modules which are connected with the LED lamps between the first LED lamp and the last LED lamp in a one-to-one correspondence mode comprise first combination logic gates;

the first input end and the second input end of the first combinational logic gate are both connected with the frequency dividing module, and the output end of the first combinational logic gate is suitable for being connected with a corresponding LED lamp.

Optionally, the first combinational logic gate includes a second logic gate, a third logic gate, a fourth logic gate, and a fifth logic gate;

the input end of the second logic gate is a first input end of the first combination logic gate, and the output end of the second logic gate is connected with the first input end of the fourth logic gate;

the input end of the third logic gate is a second input end of the first combination logic gate, and the output end of the third logic gate is connected with the second input end of the fourth logic gate;

The second logic gate is connected with the third logic gate in parallel;

the output end of the fourth logic gate is connected with the input end of the fifth logic gate, and the output end of the fifth logic gate is the output end of the first combination logic gate.

Optionally, the reset module includes a second combinational logic gate;

the first input end and the output end of the second combinational logic gate are both connected with the frequency dividing module, and the second input end of the second combinational logic gate is connected with an external power grid.

The second aspect of the embodiment of the invention provides a control method for back flashing of a plurality of LED lamps, which is applicable to a control circuit for back flashing of a plurality of LED lamps comprising a frequency division module, a signal output module and a reset module, and comprises the following steps:

the frequency division module acquires a clock signal of the clock signal source, performs frequency division processing on the clock signal to obtain a frequency division signal, and sends the frequency division signal to a signal output module connected with the current LED lamp according to the number of the flicker periods of the current LED lamp;

each signal output module carries out combination logic operation on the frequency division signals to obtain high-level signals and sends the high-level signals to the corresponding connected LED lamps;

when the number of the periods of the clock signal is larger than the total number of the flickering periods of the LED lamp, the reset module sends a reset signal to the frequency dividing module, so that the frequency dividing module resets the current frequency dividing signal.

Optionally, the LED lamp flashing period refers to a period in which one LED lamp flashes once;

the total number of LED lamp flickering cycles is the total number of LED lamp flickering cycles required in the process of realizing one-time back and forth flickering of a plurality of LED lamps;

the period of the clock signal is equal to the LED lamp flickering period.

Optionally, the number of the LED lamps is N, and the total number of the flickering periods of the LED lamps is 2N-2;

the LED lamp comprises a first LED lamp and a last LED lamp, wherein the first LED lamp and the last LED lamp flash once, and a plurality of LED lamps between the first LED lamp and the last LED lamp flash twice.

A third aspect of the embodiment of the present invention provides an LED lamp control device, which includes a plurality of LED lamps, and further includes a control circuit for back flashing of any one of the plurality of LED lamps provided in the first aspect of the embodiment.

Compared with the prior art, the embodiment of the invention has the beneficial effects that: the frequency division module obtains a clock signal of the clock signal source, performs frequency division processing on the clock signal to obtain a frequency division signal, and sends the frequency division signal to the signal output module connected with the current LED lamp according to the number of the flicker periods of the current LED lamp; the signal output modules are connected with the LED lamps in a one-to-one correspondence manner, and each signal output module carries out combination logic operation on the frequency division signals to obtain high-level signals and sends the high-level signals to the corresponding connected LED lamps; when the number of the periods of the clock signal is larger than the total number of the flashing periods of the LED lamps, the reset module sends a reset signal to the frequency division module, so that the frequency division module resets the current frequency division signal, a plurality of LED lamps are enabled to flash back, the phenomenon that a flashing circuit always flashes twice repeatedly at the head and the tail in work is eliminated, the plurality of LED lamps flash back and forth more smoothly, and the user experience degree is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a control circuit for controlling a plurality of LED lamps to flash back according to a first embodiment of the present invention;

fig. 2 is a schematic circuit diagram of a control circuit for controlling a plurality of LED lamps to flash back according to a first embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a signal output module correspondingly connected to a first LED lamp or a last LED lamp according to a first embodiment of the present invention;

fig. 4 is a schematic circuit diagram of a signal output module correspondingly connected to an LED lamp between a first LED lamp and a last LED lamp according to a first embodiment of the present invention;

fig. 5 is a schematic waveform diagram of a frequency-divided signal of a frequency-dividing module according to an embodiment of the invention;

fig. 6 is a flowchart of an implementation method of controlling a plurality of LED lamps to flash back according to the second embodiment of the present invention;

Fig. 7 is a schematic waveform diagram of a frequency-divided signal of another frequency-dividing module according to the second embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

In order to illustrate the technical scheme of the invention, the following description is made by specific examples.

Example 1

Referring to fig. 1, the control circuit for back lighting of a plurality of LED lamps provided in this embodiment includes a frequency dividing module 100, a plurality of signal output modules 200, and a reset module 300.

The frequency division module 100 is suitable for being connected with a clock signal source, and is also connected with a plurality of signal output modules 200, and is used for obtaining a clock signal of the clock signal source, performing frequency division processing on the clock signal to obtain a frequency division signal, and sending the frequency division signal to the signal output modules 200 connected with the current LED lamp according to the number of the flashing periods of the current LED lamp.

The plurality of signal output modules 200 are adapted to be connected to the plurality of LED lamps in a one-to-one correspondence.

Each signal output module 200 is configured to perform a combinational logic operation on the frequency-divided signals, and obtain a high-level signal to send to the LED lamp correspondingly connected.

The reset module 300 is connected to the frequency division module 100, and is configured to send a reset signal to the frequency division module 100 when the number of periods of the clock signal is greater than the total number of flashing periods of the LED lamp, so that the frequency division module 100 resets the current frequency division signal.

In the control circuit for the back flashing of the LED lamps, the frequency dividing module acquires the clock signal of the clock signal source, performs frequency dividing processing on the clock signal to obtain a frequency dividing signal, and sends the frequency dividing signal to the signal output module connected with the current LED lamp according to the number of the flashing periods of the current LED lamp; each signal output module carries out combination logic operation on the frequency division signals to obtain high-level signals and sends the high-level signals to the corresponding connected LED lamps; when the number of the periods of the clock signal is larger than the total number of the flashing periods of the LED lamps, the reset module sends a reset signal to the frequency division module, so that the frequency division module resets the current frequency division signal, a plurality of LED lamps are enabled to flash back, the phenomenon that a flashing circuit always flashes twice repeatedly at the head and the tail in work is eliminated, the plurality of LED lamps flash back and forth more smoothly, and the user experience degree is improved.

Further, as a specific embodiment, the frequency dividing module 100 includes a plurality of frequency dividers.

The number of the frequency dividers is related to the number of the signal output modules: 2 ^K ≥2N-2。

The number of the frequency dividers is the smallest integer of K, and the number of the signal output modules 200 is N. The number of the signal output modules 200 is the same as the number of the LED lamps. For example, if the number of LED lamps is 7, the relationship between the number of frequency dividers and the number of LED lamps is 2 ^K More than or equal to 2X 7-2, and obtaining the divisionThe number of the frequency devices is 4; if the number of the LED lamps is 5, the number of the frequency dividers is 3. The number of the frequency dividers is selected according to the number of the LED lamps, so that the waste of devices in the control circuit is avoided, and the cost of the control circuit is saved.

Optionally, the plurality of frequency dividers are sequentially connected, a positive output end of a previous frequency divider is connected with a first clock input end of a next frequency divider, and a negative output end of the previous frequency divider is connected with a second clock input end of the next frequency divider; the positive output end and the negative output end of the frequency dividers are also connected with the signal output module 200.

The signal input ends of a plurality of frequency dividers are connected with the reset module 300.

For example, referring to fig. 2, when the control circuit is connected to 7 LED lamps, the circuit connection of the frequency dividing module 100 is schematically shown. The frequency dividing module 100 includes 4 frequency dividers, which are a first frequency divider ZTR1, a second frequency divider ZTR2, a third frequency divider ZTR3, and a fourth frequency divider ZTR4.

The first clock input end and the second clock input end of the first frequency divider ZTR1 are both suitable for being connected with the clock signal source, the positive output end of the first frequency divider ZTR1 is connected with the first clock input end of the second frequency divider ZTR2, the negative output end of the first frequency divider ZTR1 is connected with the second clock input end of the second frequency divider ZTR2, and the positive output end and the negative output end of the first frequency divider ZTR1 are also connected with the signal output module 200. The positive output end of the first frequency divider ZTR1 outputs the frequency-divided signal A1, and the negative output end of the first frequency divider ZTR1 outputs the frequency-divided signal A1B.

The positive output end of the second frequency divider ZTR2 is connected to the first clock input end of the third frequency divider ZTR3, the inverse output end of the second frequency divider ZTR2 is connected to the second clock input end of the third frequency divider ZTR3, and the positive output end and the inverse output end of the second frequency divider ZTR2 are also connected to the signal output module 200. The positive output end of the second frequency divider ZTR2 outputs the frequency-divided signal A2, and the negative output end of the second frequency divider ZTR2 outputs the frequency-divided signal A2B.

The positive output end of the third frequency divider ZTR3 is connected to the first clock input end of the fourth frequency divider ZTR4, the negative output end of the third frequency divider ZTR3 is connected to the second clock input end of the fourth frequency divider ZTR4, and the positive output end and the negative output end of the third frequency divider ZTR3 are also connected to the signal output module 200. The positive output end of the third frequency divider ZTR3 outputs the frequency-divided signal A3, and the negative output end of the third frequency divider ZTR3 outputs the frequency-divided signal A3B.

The positive output end and the negative output end of the fourth frequency divider ZTR4 are both connected to the signal output module 200. The positive output end of the fourth frequency divider ZTR4 outputs the frequency-divided signal A4, and the negative output end of the fourth frequency divider ZTR4 outputs the frequency-divided signal A4B.

The signal waveform output by the positive output end of each frequency divider is opposite to the signal waveform output by the negative output end. Such as the divided signal A1 output from the positive output terminal and the divided signal A1B output from the negative output terminal of the first frequency divider in fig. 5.

Optionally, the control circuit further comprises a first inverting gate and a second inverting gate.

The second clock input of the first frequency divider is connected to the clock signal source via a first inverting gate. The first inverse gate is used for integrating the waveform of the clock signal, so that the waveform of the clock signal forms a complete square wave, and meanwhile, the inverse clock signal is input to the second clock input end of the first frequency divider.

The first clock input of the first frequency divider is connected to the output of the first inverting gate through the second inverting gate. The second inverse gate is used for integrating the waveform of the clock signal to enable the waveform of the clock signal to form a complete square wave, and meanwhile, the forward clock signal is input to the first clock input end of the first frequency divider. It should be understood that the number of the inversion gates is not limited in this embodiment, so long as the forward clock signal is input to the first clock input terminal of the first frequency divider, the reverse clock signal is input to the second clock input terminal of the first frequency divider, and the waveforms of the clock signals are integrated at the same time, so that the waveforms of the clock signals form a more complete square wave.

Further, as a specific embodiment, the signal output module 200 correspondingly connected to the first LED lamp and the signal output module 200 correspondingly connected to the last LED lamp each include a first logic gate. The first logic gate is used for stabilizing the waveform of the frequency division signal, and meanwhile, logic operation on the frequency division signal is realized, so that the first logic gate outputs a stable high-level signal to the correspondingly connected LED lamp, waste of circuit devices is reduced, and stability of the control circuit is improved.

The input end of the first logic gate is connected with the frequency dividing module 100, and the output end of the first logic gate is suitable for being connected with a corresponding LED lamp. The input end of the first logic gate comprises K+1 ports, and K is the number of frequency dividers.

Referring specifically to fig. 3, the signal output module 200 correspondingly connected to the first LED lamp and the signal output module 200 correspondingly connected to the last LED lamp each include a first nor gate, and at this time, the signal output module 200 receives the low-level frequency-divided signal output by the frequency-dividing module 100.

The input end of the first NOR gate comprises K+1 ports, and K is the number of frequency dividers.

For example, the control circuit is connected to 7 LED lamps, the frequency dividing module 100 includes 4 frequency dividers, and the input terminal of the first nor gate includes 5 ports. The first port of the input end of the first nor gate is connected with a clock signal source and is used for receiving a clock signal, and other ports of the input end of the first nor gate are all connected with the frequency division module 100; the output end of the first NOR gate is connected with the corresponding LED lamp. It should be understood that the kind of the first logic gate is not limited in this embodiment, and it is only required to ensure that the output end of the first logic gate sends a high-level signal to the LED lamp correspondingly connected. For example, the signal output module 200 corresponding to the first LED lamp and the signal output module 200 corresponding to the last LED lamp may include an and gate, and the signal output module 200 receives the high-level frequency-divided signal output from the frequency-dividing module 100.

Further, the plurality of signal output modules 200, which are connected in one-to-one correspondence to the plurality of LED lamps between the first LED lamp and the last LED lamp, each include a first combinational logic gate. The first combinational logic gate is used for receiving the frequency division signals, performing combinational logic operation to obtain high-level signals, and sending the high-level signals to the corresponding connected LED lamps.

The first input end and the second input end of the first combinational logic gate are both connected with the frequency division module 100, and the output end of the first combinational logic gate is suitable for being connected with a corresponding LED lamp. The first input end and the second input end of the first combinational logic gate comprise K+1 ports, and K is the number of frequency dividers.

Optionally, the first combinational logic gate includes a second logic gate, a third logic gate, a fourth logic gate, and a fifth logic gate. The second logic gate is used for receiving the frequency division signal that the LED lamp connected with the signal output module 200 correspondingly flashes for the first time, and the third logic gate is used for receiving the frequency division signal that the LED lamp connected with the signal output module 200 correspondingly flashes for the second time. The fourth logic gate performs logic operation on signals output by the second logic gate and the third logic gate. The fifth logic gate is used for stabilizing the waveform of the signal output by the fourth logic gate and outputting a stable high-level signal to the corresponding connected LED lamp.

The second logic gate and the third logic gate are the same type of logic gate.

The input end of the second logic gate is the first input end of the first combination logic gate, and the output end of the second logic gate is connected with the first input end of the fourth logic gate.

The input end of the third logic gate is the second input end of the first combination logic gate, and the output end of the third logic gate is connected with the second input end of the fourth logic gate.

The second logic gate is connected in parallel with the third logic gate.

For example, referring to fig. 4, the control circuit connects 7 LED lamps, the frequency dividing module 100 includes 4 frequency dividers, the LED lamps between the first LED lamp and the last LED lamp, that is, the signal output module 200 corresponding to the 2 nd LED lamp, the signal output module 200 corresponding to the 3 rd LED lamp, the signal output module 200 corresponding to the 4 th LED lamp, the signal output module 200 corresponding to the 5 th LED lamp, and the signal output module 200 corresponding to the 6 th LED lamp all include a first combinational logic gate, and the first input end and the second input end of the first combinational logic gate all include 5 ports, that is, the input end of the second logic gate and the input end of the third logic gate all include 5 ports.

The first combination logic gate comprises a second nor gate, a third nor gate, a fourth nor gate and a third inverting gate, namely the second logic gate, the third logic gate and the fourth logic gate are all nor gates, and the fifth logic gate is an inverting gate. The signal output module 200 receives the low-level frequency-divided signal output from the frequency-dividing module 100 at this time.

The first port of the input end of the second nor gate and the first port of the input end of the third nor gate are connected with a clock signal source and are used for receiving clock signals, and the other ports of the input end of the second nor gate and the other ports of the input end of the third nor gate are connected with the frequency division module 100; the output end of the second nor gate is connected with the first input end of the fourth nor gate, the output end of the third nor gate is connected with the second input end of the fourth nor gate, the output end of the fourth nor gate is connected with the input end of the third inversion gate, and the output end of the third inversion gate is connected with the corresponding LED lamp.

It should be understood that this embodiment is illustrative of the first combinational logic gate and is not limiting of the combinational logic gate. The first combinational logic gate of the embodiment only needs to ensure that the output end of the first combinational logic gate sends a high-level signal to the correspondingly connected LED lamp. For example, the second logic gate and the third logic gate may also be and gates, where the signal output module 200 receives a high level signal of the frequency division signal output by the frequency division module 100.

Further, in one embodiment, the reset module 300 includes a second combinational logic gate.

The first input end and the output end of the second combinational logic gate are both connected with the frequency division module 100, and the second input end of the second combinational logic gate is connected with an external power grid. The second combinational logic gate sends a reset signal to the frequency divider module 100.

The first input end of the second combinational logic gate comprises K ports, and K is the number of frequency dividers.

Optionally, the second combinational logic gate includes a sixth logic gate, a seventh logic gate, and an eighth logic gate. The sixth logic gate is configured to receive the frequency division signal of the frequency division module 100, perform a logic operation on the frequency division signal, and output a signal POR1 to the seventh logic gate; the seventh logic gate is configured to receive the voltage signal POR of the external power grid, perform logic operation with the signal POR1, and shape the waveform of the signal output by the seventh logic gate, and send a more stable reset signal to the frequency division module 100.

The input end of the sixth logic gate is the first input end of the second combination logic gate, and the output end of the sixth logic gate is connected with the first input end of the seventh logic gate; the second input end of the seventh logic gate is the second input end of the second combination logic gate, and the output end of the seventh logic gate is connected with the input end of the eighth logic gate; the output ends of the eighth logic gate are connected with the signal input ends of the frequency dividers.

For example, referring to fig. 2, the control circuit is connected to 7 LED lamps, the frequency dividing module 100 includes 4 frequency dividers, and the first input terminal of the second combinational logic gate includes 4 ports, i.e., the input terminal of the sixth logic gate includes 4 ports.

The sixth logic gate and the seventh logic gate are both nor gates, and the eighth logic gate is an inverse gate.

It should be understood that this embodiment is illustrative of the second combinational logic gate and is not limiting of the combinational logic gate. The type of the logic gate included in the second combinational logic gate is not limited in this embodiment, as long as the second combinational logic gate sends a high-level reset signal to the signal input terminal of the frequency division module 100. For example, the fifth logic gate may be an and gate, the sixth logic gate is a nand gate, and the seventh logic gate is an inverse gate, where the fifth logic gate receives the high signal of the frequency division signal, and the sixth logic gate receives the high signal of the external power grid signal.

Optionally, the reset module 300 further includes a third combinational logic gate.

The input end of the third logic gate is connected with an external power grid, and the output end of the third logic gate is connected with the second input end of the seventh logic gate. The third logic gate is used for shaping the waveform of the external power grid signal and outputting a low-level signal to the second input end of the second combination logic gate.

Optionally, the third logic gate includes: a fourth inversion gate, a fifth inversion gate, and a sixth inversion gate.

The fourth reverse gate, the fifth reverse gate and the sixth reverse gate are sequentially connected, the input end of the fourth reverse gate is the input end of the third logic gate, and the output end of the sixth reverse gate is the output end of the third logic gate.

Optionally, the reset module 300 further includes a PMOS (Positive channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor) tube and a first capacitor.

The drain electrode of the PMOS tube is connected with the positive electrode of the first capacitor, the drain electrode of the PMOS tube is also connected with the input end of the third combinational logic gate, the source electrode of the PMOS tube is connected with the external power supply, and the grid electrode of the PMOS tube is grounded; the negative electrode of the first capacitor is grounded.

The PMOS transistor is configured to receive a voltage signal from an external power supply. Specifically, the external power supply transmits voltage to the PMOS transistor, and the PMOS transistor is turned on, so that the PMOS transistor charges the first capacitor, the voltage of the positive electrode of the first capacitor is equal to the external power supply voltage from 0V, the PMOS transistor stops charging the first capacitor, and at this time, the voltage signal is output to the third combinational logic gate, that is, the waveform of the voltage signal is shaped through 3 inverters, and the shaped voltage signal POR is sent to the second input end of the second combinational logic gate. The duration of the high level of the voltage signal depends on the size of the PMOS and the capacitance value of the first capacitor.

The embodiment is to realize the process of flashing back and forth of a plurality of LED lamps, wherein the total number of flashing periods of the LED lamps required in the process of flashing back and forth of the plurality of LED lamps once is 2N-2, namely the total number of flashing periods of the LED lamps is 2N-2, and N is the number of the LED lamps. The first LED lamp and the last LED lamp flash once, and the plurality of LED lamps between the first LED lamp and the last LED lamp flash twice. The LED lamp flickering cycle refers to a cycle of flickering one LED lamp once, and is expressed as T; the period of the clock signal is equal to the LED lamp blinking period, also denoted T, as in fig. 5.

The principle of the signal output module 200 logically combining the divided signals of the frequency division module 100 is as follows:

the control circuit is connected with N LED lamps;

the 1 st LED lamp flashes when the clock signal is the 1 st LED lamp flashing period, and when the signal output module 200 logically combines the received frequency division signals in the 1 st LED lamp flashing period, the 1 st LED lamp is sent to the 1 st LED lamp in the 1 st LED lamp flashing period, and other LED lamps receive the low-level signals.

The M (1 < M < N) th LED lamp flashes in the period that the clock signal is the M th LED lamp flashing period, the signal output module 200 receives the frequency division signal of the M th LED lamp flashing period and carries out logic combination, and when the M th LED lamp flashing period, the signal output module sends a high-level signal to the M th LED lamp, and other LED lamps receive a low-level signal; meanwhile, symmetry of back flashing is considered, the Mth LED lamp flashes when the clock signal is the 2N-M LED lamp flashing period, namely the signal output module 200 logically combines frequency division signals of the 2N-M LED lamp flashing period, and sends a high-level signal to the Mth LED lamp when the clock signal is the 2N-M LED lamp flashing period, and other LED lamps receive a low-level signal.

The nth LED lamp flashes when the clock signal is the nth LED lamp flashing period, the signal output module 200 logically combines the frequency division signals transmitted to the nth LED lamp, so that the frequency division signals of the nth LED lamp flashing period are high-level signals and are transmitted to the nth LED lamp, and other LED lamps receive low-level signals.

Further, the frequency division module 100 is connected with the plurality of signal output modules 200 in a manner of connecting the current LED lamp with the signal output modules 200 connected with the current LED lamp according to the number of the flicker periods of the current LED lamp, and sending a frequency division signal to the signal output modules 200 connected with the current LED lamp.

Specifically, each LED lamp flashes in what LED lamp flashing period, which determines how the signal output module 200 corresponding to the LED lamp is connected to the frequency dividing module 100, and which path of frequency dividing signal of the frequency dividing module 100 is received.

For example, referring to fig. 2, 3, 4 and 5, the control circuit is connected to 7 LED lamps, and the frequency dividing module 100 includes 4 frequency dividers. In this embodiment, 7 LED lamps flash back and forth, so the total period for completing the whole back and forth flashing process is 2*7-2=12 LED lamp flashing periods. The frequency dividing module 100 includes 4 frequency dividers, which are a first frequency divider ZTR1, a second frequency divider ZTR2, a third frequency divider ZTR3, and a fourth frequency divider ZTR4.

The positive output end of the first frequency divider ZTR1 outputs the frequency-divided signal A1, and the negative output end of the first frequency divider ZTR1 outputs the frequency-divided signal A1B. The positive output end of the second frequency divider ZTR2 outputs the frequency-divided signal A2, and the negative output end of the second frequency divider ZTR2 outputs the frequency-divided signal A2B. The positive output end of the third frequency divider ZTR3 outputs the frequency-divided signal A3, and the negative output end of the third frequency divider ZTR3 outputs the frequency-divided signal A3B. The positive output end of the fourth frequency divider ZTR4 outputs the frequency-divided signal A4, and the negative output end of the fourth frequency divider ZTR4 outputs the frequency-divided signal A4B. The waveforms of the divided signals output from the four frequency dividers of the frequency dividing module 100 are shown in fig. 5.

The 1 st LED lamp flashes in the 1 st LED lamp flashing period, the 1 st port of the NOR gate of the 1 st signal output module 200 correspondingly connected with the 1 st LED lamp receives the clock signal, namely is connected with a clock signal source, the other four ports are respectively connected with the positive output end of the frequency divider ZTR1, the positive output end of the frequency divider ZTR2, the positive output end of the frequency divider ZTR3 and the positive output end of the frequency divider ZTR4, and respectively receives the frequency division signal A1, the frequency division signal A2, the frequency division signal A3 and the frequency division signal A4, namely receives the low-level frequency division signal of the 4 frequency dividers in the 1 st LED lamp flashing period, and then outputs a high-level signal to the 1 st LED lamp through NOR gate logic operation.

The 2 nd LED lamp flashes in the 2 nd LED lamp flashing period and flashes in the 12 th LED lamp flashing period, the 1 st port of the 2 nd signal output module 200 and the 1 st port of the second NOR gate which are correspondingly connected with the 2 nd LED lamp receive clock signals, namely are connected with a clock signal source, the first NOR gate is used for receiving frequency division signals in the 2 nd LED lamp flashing period, the other four ports of the first NOR gate are respectively connected with the inverse output end of the frequency divider ZTR1, the positive output end of the frequency divider ZTR2, the positive output end of the frequency divider ZTR3 and the positive output end of the frequency divider ZTR4, respectively receive the frequency division signal A1B, the frequency division signal A2, the frequency division signal A3 and the frequency division signal A4, namely, in the 2 nd LED lamp flashing period, receive low-level frequency division signals of the 4 frequency dividers, and then transmit high-level signals to the third NOR gate through logic operation of the first NOR gate; the second nor gate is used for receiving the frequency division signal in the flicker period of the 12 th LED lamp, the other four ports of the second nor gate are respectively connected with the inverted output end of the frequency divider ZTR1, the inverted output end of the frequency divider ZTR2, the positive output end of the frequency divider ZTR3 and the inverted output end of the frequency divider ZTR4, respectively receiving the frequency division signal A1B, the frequency division signal A2B, the frequency division signal A3 and the frequency division signal A4B, namely, in the flicker period of the 12 th LED lamp, receiving the low-level frequency division signal of the 4 frequency dividers, then transmitting a high-level signal to the third nor gate through the logic operation of the second nor gate, and the third nor gate carries out the logic operation on the two high-level signals to output the low-level signal to the inverted gate, and the inverted gate outputs the high-level signal to the 2 nd LED lamp.

Similarly, the 3 rd LED lamp blinks in the 11 th LED lamp blinks in the 3 rd LED lamp blinks in the period, and the 1 st port of the first nor gate and the second nor gate of the 3 rd signal output module 200, which are correspondingly connected with the 3 rd LED lamp, receive clock signals. The first nor gate of the 3 rd signal output module 200 is configured to receive the frequency-divided signal during the 3 rd LED lamp flashing period, and the other four ports are respectively connected to the positive output end of the frequency divider ZTR1, the negative output end of the frequency divider ZTR2, the positive output end of the frequency divider ZTR3, and the positive output end of the frequency divider ZTR4, and receive the frequency-divided signal A1, the frequency-divided signal A2B, the frequency-divided signal A3, and the frequency-divided signal A4, that is, receive the low-level frequency-divided signal of the 4 frequency dividers during the 3 rd LED lamp flashing period, and then send the high-level signal to the third nor gate through the logic operation of the first nor gate; the second nor gate is used for receiving the frequency division signal in the 11 th LED lamp flashing period, the other four ports of the second nor gate are respectively connected with the positive output end of the frequency divider ZTR1, the negative output end of the frequency divider ZTR2, the positive output end of the frequency divider ZTR3 and the negative output end of the frequency divider ZTR4, respectively receiving the frequency division signal A1, the frequency division signal A2B, the frequency division signal A3 and the frequency division signal A4B, namely, in the 11 th LED lamp flashing period, receiving the low-level frequency division signal of the 4 frequency dividers, then transmitting the high-level signal to the third nor gate through the logic operation of the second nor gate, and the third nor gate carries out the logic operation of the two high-level signals to output the low-level signal to the reverse gate, and the reverse gate outputs the high-level signal to the 3 rd LED lamp.

The 4 th LED lamp blinks in the 10 th LED lamp blinks in the 4 th LED lamp blinks in the period, and the 1 st port of the first nor gate and the second nor gate of the 4 th signal output module 200, which are correspondingly connected with the 4 th LED lamp, both receive clock signals. The first nor gate of the 4 th signal output module 200 is configured to receive the frequency-divided signal during the 4 th LED lamp flashing period, and the other four ports are respectively connected to the inverted output end of the frequency divider ZTR1, the inverted output end of the frequency divider ZTR2, the positive output end of the frequency divider ZTR3, and the positive output end of the frequency divider ZTR4, and receive the frequency-divided signal A1B, the frequency-divided signal A2B, the frequency-divided signal A3, and the frequency-divided signal A4, that is, receive the low-level frequency-divided signal of the 4 frequency dividers during the 4 th LED lamp flashing period, and then send the high-level signal to the third nor gate through the logic operation of the first nor gate; the second nor gate is used for receiving the frequency division signal in the 10 th LED lamp flashing period, the other four ports of the second nor gate are respectively connected with the inverse output end of the frequency divider ZTR1, the positive output end of the frequency divider ZTR2, the positive output end of the frequency divider ZTR3 and the inverse output end of the frequency divider ZTR4, respectively receiving the frequency division signal A1B, the frequency division signal A2, the frequency division signal A3 and the frequency division signal A4B, namely, in the 10 th LED lamp flashing period, receiving the low-level frequency division signal of the 4 frequency dividers, then transmitting the high-level signal to the third nor gate through the logic operation of the second nor gate, and the third nor gate carries out the logic operation of the two high-level signals to output the low-level signal to the inverse gate, and the inverse gate outputs the high-level signal to the 4 th LED lamp.

The 5 th LED lamp blinks in the 9 th LED lamp blinks in the 5 th LED lamp blinks in the period, and the 1 st port of the first nor gate and the second nor gate of the 5 th signal output module 200, which are correspondingly connected with the 5 th LED lamp, both receive clock signals. The first nor gate of the 5 th signal output module 200 is configured to receive the frequency-divided signal during the 5 th LED lamp flashing period, and the other four ports are respectively connected to the positive output end of the frequency divider ZTR1, the positive output end of the frequency divider ZTR2, the negative output end of the frequency divider ZTR3, and the positive output end of the frequency divider ZTR4, and receive the frequency-divided signal A1, the frequency-divided signal A2, the frequency-divided signal A3B, and the frequency-divided signal A4, that is, receive the low-level frequency-divided signal of the 4 frequency dividers during the 5 th LED lamp flashing period, and then send the high-level signal to the third nor gate through the logic operation of the first nor gate; the second nor gate is used for receiving the frequency division signal in the 9 th LED lamp flashing period, the other four ports of the second nor gate are respectively connected with the positive output end of the frequency divider ZTR1, the positive output end of the frequency divider ZTR2, the positive output end of the frequency divider ZTR3 and the inverse output end of the frequency divider ZTR4, respectively receiving the frequency division signal A1, the frequency division signal A2, the frequency division signal A3 and the frequency division signal A4B, namely, in the 9 th LED lamp flashing period, receiving the low-level frequency division signal of the 4 frequency dividers, then transmitting the high-level signal to the third nor gate through the logic operation of the second nor gate, and the third nor gate carries out the logic operation of the two high-level signals to output the low-level signal to the inverse gate, and the inverse gate outputs the high-level signal to the 5 th LED lamp.

The 6 th LED lamp blinks in the 8 th LED lamp blinks in the 6 th LED lamp blinks in the period, and the 1 st port of the first nor gate and the second nor gate of the 6 th signal output module 200, which are correspondingly connected with the 6 th LED lamp, both receive clock signals. The first nor gate of the 6 th signal output module 200 is configured to receive the frequency-divided signal during the 6 th LED lamp flashing period, and the other four ports are respectively connected to the inverted output end of the frequency divider ZTR1, the positive output end of the frequency divider ZTR2, the inverted output end of the frequency divider ZTR3, and the positive output end of the frequency divider ZTR4, and receive the frequency-divided signal A1B, the frequency-divided signal A2, the frequency-divided signal A3, and the frequency-divided signal A4, that is, receive the low-level frequency-divided signals of the 4 frequency dividers during the 6 th LED lamp flashing period, and then send the high-level signal to the third nor gate through the logic operation of the first nor gate; the second nor gate is used for receiving the frequency division signal in the 8 th LED lamp flashing period, the other four ports of the second nor gate are respectively connected with the inverted output end of the frequency divider ZTR1, the inverted output end of the frequency divider ZTR2, the inverted output end of the frequency divider ZTR3 and the positive output end of the frequency divider ZTR4, respectively receiving the frequency division signal A1B, the frequency division signal A2B, the frequency division signal A3B and the frequency division signal A4, namely, in the 8 th LED lamp flashing period, receiving the low-level frequency division signal of the 4 frequency dividers, then transmitting a high-level signal to the third nor gate through the logic operation of the second nor gate, and the third nor gate carries out the logic operation of the two high-level signals to output the low-level signal to the inverted gate, and the inverted gate outputs the high-level signal to the 6 th LED lamp.

The 7 th LED lamp flashes in the 7 th LED lamp flashing period, the 1 st port of the NOR gate of the 7 th signal output module 200 correspondingly connected with the 7 th LED lamp receives the clock signal, namely is connected with the clock signal source, the other four ports respectively receive the frequency division signal A1, the frequency division signal A2B, the frequency division signal A3B and the frequency division signal A4, namely the other four ports are respectively connected with the positive output end of the frequency divider ZTR1, the counter output end of the frequency divider ZTR2, the counter output end of the frequency divider ZTR3 and the positive output end of the frequency divider ZTR4, namely in the 7 th LED lamp flashing period, the low-level frequency division signal of the 4 frequency dividers is received, and then the high-level signal is output to the 7 th LED lamp through the NOR gate logic operation.

Meanwhile, when the number of periods of the clock signal is greater than the total number of flashing periods of the LED lamps, i.e., when the number of periods of the clock signal is 13, the plurality of LED lamps enter a process of flashing again for the second time, and the frequency division signal 100 resets the frequency division signal waveform when the number of periods of the clock signal is 13 to be the same as the frequency division signal waveform when the first LED lamp flashes, i.e., when the number of periods of the clock signal is 13, the reset module 300 sends a reset signal to the frequency division module 100. That is, four ports of the input end of the first nor gate of the reset module 300 are respectively connected with the positive output end of the frequency divider ZTR1, the positive output end of the frequency divider ZTR2, the inverted output end of the frequency divider ZTR3 and the inverted output end of the frequency divider ZTR4, and receive the divided signals A1, A2, A3B and A4B, that is, when the period number of the clock signal is 13, receive the divided signals of the low level of the 4 frequency dividers, output the high level signal to the second nor gate of the reset module 300 through the logic operation of the first nor gate, receive the low level signal of the external power grid, perform the logic operation of the low level signal and the high level signal of the first nor gate to output the low level signal to the inverted gate, the inverted gate outputs the reset signal of the high level to the frequency divider module 100, and the divided signal waveform when the period number of the clock signal is 13 is reset to be the same as the signal waveform when the first LED lamp flashes, so that the plurality of LED lamps enter the second time to enable the LED lamps to enter the second time, and the two flash lamps to be more smooth in the two flash back and forth in operation.

Optionally, the signal output module 200 correspondingly connected to the first LED lamp and the last LED lamp includes an and gate, and the frequency division signals received by the signal output module 200 correspondingly connected to the first LED lamp and the last LED lamp are all high-level signals. For example, the signal output module 200, to which the 1 st LED lamp is correspondingly connected, receives the divided signal A1B, the divided signal A2B, the divided signal A3B, and the divided signal A4B, that is, receives the divided signals of high levels of the 4 frequency dividers when the 1 st LED lamp blinks in a period.

Optionally, when the second logic gate and the third logic gate of the first combinational logic gate are both and gates, the frequency division signals received by the signal output module 200 correspondingly connected to the LED lamp between the first LED lamp and the last LED lamp are all high level signals. The signal output module 200 correspondingly connected to the 2 nd LED lamp receives the frequency-divided signal A1, the frequency-divided signal A2B, the frequency-divided signal A3B, and the frequency-divided signal A4B, that is, receives the high-level frequency-divided signals of the 4 frequency dividers during the flashing period of the 2 nd LED lamp.

In the above embodiment, the control circuit for the LED lamps to flash back obtains the clock signal of the clock signal source through the frequency dividing module, performs frequency dividing processing on the clock signal to obtain the frequency dividing signal, and sends the frequency dividing signal to the signal output module connected with the current LED lamp according to the number of the flashing cycles of the current LED lamp; the signal output modules are connected with the LED lamps in a one-to-one correspondence manner, and each signal output module carries out combination logic operation on the frequency division signals to obtain high-level signals and sends the high-level signals to the corresponding connected LED lamps; when the number of the periods of the clock signal is larger than the total number of the flashing periods of the LED lamps, the reset module sends a reset signal to the frequency division module, so that the frequency division module resets the current frequency division signal, a plurality of LED lamps are enabled to flash back, the phenomenon that a flashing circuit always flashes twice repeatedly at the head and the tail in work is eliminated, the plurality of LED lamps flash back and forth more smoothly, and the user experience degree is improved.

Example two

Corresponding to the control circuit for flashing back the plurality of LED lamps in the first embodiment, the present embodiment provides a control method for flashing back the plurality of LED lamps. Referring specifically to fig. 6, a schematic implementation flow diagram of an embodiment of a method for controlling a plurality of LED lamps to flash back is described in detail below:

in step S601, the frequency dividing module obtains a clock signal of the clock signal source, performs frequency dividing processing on the clock signal to obtain a frequency dividing signal, and sends the frequency dividing signal to the signal output module connected with the current LED lamp according to the number of the flashing periods of the current LED lamp.

Optionally, the LED lamp flashing period refers to a period in which one LED lamp flashes once; the period of the clock signal is equal to the LED lamp flickering period.

In step S602, each signal output module performs a combinational logic operation on the frequency-divided signals, so as to obtain a high-level signal, and the high-level signal is sent to the corresponding connected LED lamp.

And step S603, when the period number of the clock signal is greater than the total number of the flashing periods of the LED lamp, the reset module sends a reset signal to the frequency dividing module, so that the frequency dividing module resets the current frequency dividing signal.

The total number of LED lamp flickering cycles is the total number of LED lamp flickering cycles required in the process of realizing one-time back and forth flickering of a plurality of LED lamps.

Optionally, the number of the LED lamps is N, and the total number of the flickering periods of the LED lamps is 2N-2.

the control circuit is connected with N LED lamps;

When the M (1 < M < N) th LED lamp is in the flickering period of the M th LED lamp, the signal output module 200 logically combines the received frequency division signals of the flickering period of the M th LED lamp, and when the M th LED lamp is in the flickering period, the signal output module sends a high-level signal to the M th LED lamp, and other LED lamps receive a low-level signal; meanwhile, symmetry of back flashing is considered, the Mth LED lamp flashes when the clock signal is the 2N-M LED lamp flashing period, namely the signal output module 200 logically combines frequency division signals of the 2N-M LED lamp flashing period, and sends a high-level signal to the Mth LED lamp when the clock signal is the 2N-M LED lamp flashing period, and other LED lamps receive a low-level signal.

The nth LED lamp blinks when the clock signal is the nth LED lamp blinks period, and when the signal output module 200 logically combines the frequency division signals transmitted to the nth LED lamp, the nth LED lamp sends a high-level signal to the nth LED lamp and the other LED lamps receive a low-level signal.

For example, referring to fig. 7, a schematic waveform diagram of a frequency division signal of another frequency division module provided in this embodiment is shown, where the control circuit is connected to 5 LED lamps, that is, 3 frequency dividers, and the total number of LED lamp flashing periods is 8. The frequency dividing module, the signal outputting module, and the resetting module are the same as those of fig. 2, 3, and 4 in the first embodiment described above.

The first frequency divider outputs a frequency-divided signal A1 and a frequency-divided signal A1B, the middle frequency divider outputs a frequency-divided signal A2 and a frequency-divided signal A2B, and the last frequency divider outputs a frequency-divided signal A3 and a frequency-divided signal A3B. The clock waveforms of the frequency-divided signal A1 and the frequency-divided signal A1B are opposite, that is, when the frequency-divided signal A1 is at a high level, the frequency-divided signal A1B is at a low level, the clock waveforms of the frequency-divided signal A2 and the frequency-divided signal A2B are opposite, and the clock waveforms of the frequency-divided signal A3 and the frequency-divided signal A3B are opposite.

The 1 st LED lamp flashes in the 1 st LED lamp flashing period, and the 1 st signal output module correspondingly connected with the 1 st LED lamp receives the frequency division signal A1, the frequency division signal A2 and the frequency division signal A3, namely, receives the low-level frequency division signal output by the 3 frequency dividers in the 1 st LED lamp flashing period, and outputs the high-level signal to the 1 st LED lamp through NOR gate logic operation.

The 2 nd LED lamp flashes in the 2 nd LED lamp flashing period and flashes in the 8 th LED lamp flashing period, the first NOR gate of the 2 nd signal output module 200 correspondingly connected with the 2 nd LED lamp receives the frequency division signal A1B, the frequency division signal A2 and the frequency division signal A3, namely, receives the low-level frequency division signal output by the 3 frequency dividers in the 2 nd LED lamp flashing period, and sends a high-level signal to the third NOR gate through the logic operation of the first NOR gate; the second nor gate receives the frequency division signal A1B, the frequency division signal A2B and the frequency division signal A3B, namely, receives the low-level frequency division signal output by the 3 frequency dividers during the flicker period of the 8 th LED lamp, sends a high-level signal to the third nor gate through the logic operation of the second nor gate, the third nor gate carries out the logic operation on the two high-level signals to output the low-level signal to the reverse gate, and the reverse gate outputs the high-level signal to the 2 nd LED lamp.

Similarly, the 3 rd LED lamp blinks in the 3 rd LED lamp blinking period and the 7 th LED lamp blinking period, and the first nor gate of the 3 rd signal output module 200, to which the 3 rd LED lamp is correspondingly connected, receives the frequency division signal A1, the frequency division signal A2B and the frequency division signal A3, that is, receives the low-level frequency division signal output by the 3 rd frequency divider in the 3 rd LED lamp blinking period, and sends a high-level signal to the third nor gate through the logic operation of the first nor gate; the second nor gate receives the frequency division signal A1, the frequency division signal A2B and the frequency division signal A3B, namely, receives the low-level frequency division signal output by the 3 frequency dividers during the flicker period of the 7 th LED lamp, sends a high-level signal to the third nor gate through the logic operation of the second nor gate, the third nor gate carries out the logic operation on the two high-level signals to output the low-level signal to the reverse gate, and the reverse gate outputs the high-level signal to the 3 rd LED lamp.

The 4 th LED lamp blinks at the 4 th LED lamp blinks period and the 6 th LED lamp blinks at the 6 th LED lamp blinks period. The first nor gate of the 4 th signal output module 200 correspondingly connected with the 4 th LED lamp receives the frequency division signal A1B, the frequency division signal A2B and the frequency division signal A3, namely, receives the low-level frequency division signal output by the 3 frequency dividers during the flicker period of the 4 th LED lamp, and sends a high-level signal to the third nor gate through the logic operation of the first nor gate; the second nor gate receives the frequency division signal A1B, the frequency division signal A2 and the frequency division signal A3B, namely, receives the low-level frequency division signal output by the 3 frequency dividers during the flicker period of the 6 th LED lamp, sends a high-level signal to the third nor gate through the logic operation of the second nor gate, the third nor gate carries out the logic operation on the two high-level signals to output the low-level signal to the reverse gate, and the reverse gate outputs the high-level signal to the 4 th LED lamp.

The 5 th LED lamp flashes in the 5 th LED lamp flashing period, and the 5 th signal output module correspondingly connected with the 5 th LED lamp receives the frequency division signal A1, the frequency division signal A2 and the frequency division signal A3B, namely, receives the low-level frequency division signal output by the 3 frequency dividers in the 5 th LED lamp flashing period, and outputs the high-level signal to the 5 th LED lamp through NOR gate logic operation.

Meanwhile, when the number of the periods of the clock signal is larger than the total number of the flashing periods of the LED lamps, namely when the number of the periods of the clock signal is 9, the LED lamps enter a secondary flashing process, and the frequency division signal resets the frequency division signal waveform when the number of the periods of the clock signal is 9 to be the same as the frequency division signal waveform when the 1 st LED lamp flashes. The reset module receives the frequency division signals A1, A2 and A3, namely when the number of the periods of the clock signal is 9, the reset module receives the low-level frequency division signals of the 3 frequency dividers, outputs high-level signals to the second NOR gate of the reset module through the logic operation of the first NOR gate, the second NOR gate receives the low-level signals of the external power grid, carries out the logic operation on the low-level signals of the external power grid and the high-level signals of the first NOR gate to output low-level signals to the reverse gate, the reverse gate outputs high-level reset signals to the frequency division module, and the frequency division signals reset the frequency division signal waveforms when the number of the periods of the clock signal is 13 to be the same as the frequency division signal waveforms when the 1 st LED lamp flashes, so that a plurality of LED lamps enter the process of secondary flash.

When the number of the periods of the clock signal is larger than the total number of the flashing periods of the LED lamps, a reset signal is sent to the frequency division module, so that the frequency division module resets the current frequency division signal, the phenomenon that the flashing lamp circuit always flashes twice repeatedly at the head lamp and the tail lamp during operation can be eliminated, and the plurality of LED lamps flash more smoothly back and forth.

In the control method for the back flashing of the LED lamps, the frequency dividing module obtains the clock signal of the clock signal source, performs frequency dividing processing on the clock signal to obtain a frequency dividing signal, and sends the frequency dividing signal to the signal output module connected with the current LED lamp according to the flashing period number of the current LED lamp; each signal output module carries out combination logic operation on the frequency division signals to obtain high-level signals and sends the high-level signals to the corresponding connected LED lamps; when the number of the periods of the clock signal is larger than the total number of the flashing periods of the LED lamps, the reset module sends a reset signal to the frequency division module, so that the frequency division module resets the current frequency division signal, a plurality of LED lamps are enabled to flash back, the phenomenon that a flashing circuit always flashes twice repeatedly at the head and the tail in work is eliminated, the plurality of LED lamps flash back and forth more smoothly, and the user experience degree is improved.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.

Example III

The embodiment of the invention provides an LED lamp control device, which comprises a plurality of LED lamps and further comprises any one of the control circuits for back flashing of the plurality of LED lamps provided in the first embodiment, and has the beneficial effects of the control circuits for back flashing of the plurality of LED lamps.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims

1. A control circuit for a plurality of light emitting diode, LED, lamps to flash back, comprising: the device comprises a frequency division module, a plurality of signal output modules and a reset module;

the resetting module is connected with the frequency dividing module and is used for sending a resetting signal to the frequency dividing module when the period number of the clock signal is larger than the total number of the flashing periods of the LED lamp, so that the frequency dividing module resets the current frequency dividing signal;

the signal output module correspondingly connected with the first LED lamp and the signal output module correspondingly connected with the last LED lamp both comprise first logic gates;

the first input end and the second input end of the first combinational logic gate are connected with the frequency dividing module, and the output end of the first combinational logic gate is suitable for being connected with a corresponding LED lamp;

the first combinational logic gate comprises a second logic gate, a third logic gate, a fourth logic gate and a fifth logic gate;

the second logic gate is connected with the third logic gate in parallel; the second logic gate and the third logic gate are logic gates of the same type;

2. The control circuit for a plurality of LED lamps to flash back of claim 1, wherein the frequency dividing module comprises a plurality of frequency dividers;

3. The control circuit for a plurality of LED lamps to flash back according to claim 2, wherein a plurality of said frequency dividers are connected in sequence, the positive output terminal of the previous said frequency divider being connected to the first clock input terminal of the next said frequency divider, the negative output terminal of the previous said frequency divider being connected to the second clock input terminal of the next said frequency divider; the positive output ends and the negative output ends of the frequency dividers are also connected with the signal output module;

4. The control circuit for a plurality of LED lamps to flash back of claim 1, wherein the reset module comprises a second combinational logic gate;

5. A control method for back lighting of a plurality of LED lamps, which is suitable for a control circuit for back lighting of a plurality of LED lamps according to any one of claims 1 to 4, comprising a frequency dividing module, a signal outputting module and a resetting module, and is characterized by comprising:

6. The method for controlling a plurality of LED lamps to flash back according to claim 5, wherein the LED lamp flashing cycle means a cycle in which one LED lamp flashes once;

the period of the clock signal is equal to the LED lamp flickering period.

7. The method for controlling the back lighting of a plurality of LED lamps according to claim 5, wherein the number of LED lamps is N, and the total number of LED lamp lighting periods is 2N-2;

8. A control device for a plurality of LED lamps to flash back, comprising a plurality of LED lamps, further comprising a control circuit for a plurality of LED lamps to flash back according to any one of claims 1 to 4.