CN105141295A - Self-calibration circuit of built-in clock - Google Patents
Self-calibration circuit of built-in clock Download PDFInfo
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Abstract
The invention provides a self-calibration circuit of a built-in clock. The self-calibration circuit comprises a time sequence management circuit, a clock generator and a self-calibration unit, wherein the clock generator is used for generating and outputting a clock signal to the self-calibration unit through an output end of the clock generator; the self-calibration unit is used for completing self-calibration based on the clock signal sent from the clock generator and sending out an effective self-calibration locking signal after self-calibration is completed; an input end of the time sequence management circuit is connected with an enable signal, and an output end of the time sequence management circuit is connected with an enable end of the clock generator; when the enable signal is jumped to a valid level from an invalid level, a clock control signal output from the time sequence management circuit is jumped to a valid level from an invalid level; and when the enable signal is jumped to the invalid level from the valid level, the valid level of the clock control signal output from the time sequence management circuit is jumped to the invalid level after continuing a plurality of clock periods. Therefore, the problem of logic error caused by early closure of the clock signal can be solved.
Description
[technical field]
The present invention relates to technical field of circuit design, particularly a kind of self-calibration circuit of embedded clock.
[background technology]
Self-calibration circuit in the course of the work, generally provide clock by its exterior, but the complexity consideration in order to reduce system, and embedded clock technology becomes main flow gradually, but embedded clock also has a shortcoming: time due to system closing, clock signal is also closed simultaneously.Therefore, some circuit modules can be caused signal can not to be sent out in time, thus produce logic error.
Therefore, be necessary to provide a kind of technical scheme of improvement to solve the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of self-calibration circuit of embedded clock, it can, after self calibration completes, make several cycles of clock signal delay close, thus solution is closed too early due to clock signal and causes producing the problem of logic error.
In order to solve the problem, the invention provides a kind of self-calibration circuit, it comprises timing management circuit, clock generator, self-locking logical block and self calibration unit.Described clock generator comprises Enable Pin and output, and described clock generator is for generation of also giving described self calibration unit, using the clock signal as described self calibration unit by its output clock signal.The clock signal that described self calibration unit is sent here based on clock generator completes self calibration, sends effective self calibration locking signal after self calibration completes.The input of described timing management circuit is connected with enable signal, its output is connected with the Enable Pin of clock generator, described timing management circuit gives the Enable Pin of described clock generator based on described enable signal output clock control signal, when described enable signal is significant level by inactive level saltus step, the clock control signal that described timing management circuit exports is significant level by inactive level saltus step, when described clock control signal is significant level, described clock generator starts to export described clock signal; When described enable signal is inactive level by significant level saltus step, after the significant level of the clock control signal that described timing management circuit exports continues several clock cycle, saltus step is inactive level, when described clock signal is inactive level, described clock generator stops exporting described clock signal.Described self-locking logical block, when described self calibration unit exports effective self calibration locking signal, makes described enable signal be inactive level by significant level redirect.
Further, described timing management circuit comprises logical operation module and N number of shift register, between the input that described N number of shift register is series at described timing management circuit successively and the first input end of logical operation circuit, wherein, the input of first displacement shift register is connected with the input of described timing management circuit, the output of N number of shift register is connected with the first output of described logical operation module, and the clock end of each shift register is all connected with the output of described clock generator; Second input of described logical operation module is directly connected with the input of described timing management circuit, its output is connected with the output of described timing management circuit, described logical operation module is used for carrying out logical operation to the signal that its first input end and the second input receive, and export described clock control signal, wherein, N be more than or equal to 1 natural number.
Further, the significant level of described enable signal is high level, and its inactive level is low level; The significant level of described clock control signal is high level, its inactive level is low level, described logical operation module comprises NOR gate and inverter INV1, an input of described NOR gate is connected with the input of described timing management circuit, another input of described NOR gate is connected with the output of N number of shift register, the output of described NOR gate is connected with the input of described inverter INV1, and the output of described inverter INV1 is connected with the output of described timing management circuit.
Further, described clock generator is ring oscillator, described ring oscillator comprises starting of oscillation switch, inverter INV2 and (2n+1) individual not gate, wherein, n be more than or equal to 1 natural number, all not gates join end to end formation ring-type successively, a link of described starting of oscillation switch is connected with power end, its another link is connected with the control end of at least one not gate, the control end of described starting of oscillation switch is connected with the output of inverter INV2, the input of described inverter INV2 is connected with the Enable Pin of described clock generator, the output of described clock generator is connected with the connected node between adjacent two not gates.
Further, described starting of oscillation switch is PMOS transistor, and the source electrode of described PMOS transistor, drain and gate are respectively a link of described starting of oscillation switch, another link and control end.
Further, described clock generator is LC oscillator or RC oscillator.
Further, described self calibration unit comprises analogue unit and digital units, described analogue unit is used for comparison object analog signal and reference analog signal, and result exports calibration control signal to described digital units based on the comparison, described digital units is based on described calibration control signal adjustment calibration data, and described calibration data is fed back to described analogue unit, described analogue unit is calibrated described target simulation signal based on the calibration data after adjustment, by continuous calibration, until described target simulation signal equals described reference analog signal, now self calibration completes, send effective self calibration locking signal.
Compared with prior art, the present invention increases timing management circuit between the enable signal and the Enable Pin of embedded clock generator of self-calibration circuit, described timing management circuit manages again based on the clock signal of enable signal to self-calibration circuit, produce new sequential, thus when enable signal is inactive level signal by the saltus step of significant level signal, clock signal is closed after can continuing several clock cycle again, thus several week after date realized upon completion of the calibration closes clock signal again, to solve because clock signal closes the problem causing too early producing logic error.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is a kind of circuit diagram of self-calibration circuit;
Fig. 2 is the sequential chart of each signal in the self-calibration circuit in Fig. 1;
Fig. 3 is the sequential chart that alignment error appears in self-calibration circuit in Fig. 1.
Fig. 4 is the circuit diagram of the present invention's self-calibration circuit in one embodiment;
Fig. 5 is the timing management circuit circuit diagram in one embodiment in Fig. 4;
Fig. 6 is for adopting the sequential chart of each signal of self-calibration circuit in Fig. 2 of the timing management circuit shown in Fig. 5;
Fig. 7 is the clock generator circuit diagram in one embodiment in Fig. 2.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the present invention.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
Please refer to shown in Fig. 1, it is a kind of circuit diagram of self-calibration circuit.Self-calibration circuit in Fig. 1 comprises clock generator 110 and self calibration unit 140.
The Enable Pin of described clock generator 110 is connected with enable signal ENABLE, and described enable signal ENABLE works for controlling described clock generator 110 or closes, thus controls work or the closedown of self calibration unit 140; The clock signal that described self calibration unit 140 is sent here based on clock generator completes self calibration, sends effective self calibration locking signal Lock_Ready after self calibration completes.
Described self-calibration circuit also comprises self-locking logical block (not shown), described self-locking logical block is when self calibration unit 140 exports effective self calibration locking signal Lock_Ready, described enable signal ENABLE is made to be inactive level by significant level redirect, described like this clock generator 110 is not just at clock signal, described self calibration unit 110 also quits work, and the oneself completing self-calibration circuit closes in time.
In one example, described self calibration unit 140 comprises analogue unit 120 and digital units 130.
Described clock generator 110 operationally produces also clock signal CLK and, to described analogue unit 120 and described digital units 130, thinks that described analogue unit 120 and described digital units 130 provide synchronised clock.Described analogue unit 120 is for comparison object analog signal and reference analog signal, and result exports calibration control signal to described digital units 130 based on the comparison, described digital units 130 is based on described calibration control signal adjustment calibration data, and described calibration data is fed back to described analogue unit 120, described analogue unit 120 is calibrated described target simulation signal based on the calibration data after adjustment.By continuous calibration, until described target simulation signal equals described reference analog signal, now self calibration completes, described analogue unit 120 sends effective self calibration locking signal Lock_Ready, and described digital units 130 exports the calibration data Data_out<N:0> calibrated.Wherein said target simulation signal can be electric current, also can be voltage, and described reference analog signal can be the reference value of predefined.In some example, described analogue unit 430 is based on calibration data conducting or turn off a calibration switch, thus realizes the adjustment for described target simulation signal.But the technology contents completing self-calibrating about self calibration unit 140 all belongs to prior art, and the present invention has nothing to do with the concrete self calibration that how to complete, and does not therefore elaborate to this in the present invention.
Please refer to shown in Fig. 2, it is the sequential chart of each signal in the self-calibration circuit in Fig. 1.The course of work of the calibration circuit in Fig. 1 is introduced based on Fig. 2, because clock generator 110 is embedded clock generator, therefore, when enable signal ENABLE is high level by low transition, clock generator 110 is started working, and clock signal CLK, thus analogue unit 120 is worked together with digital units 130.When the self calibration locking signal Lock_Ready that analogue unit 120 exports is high (significant level) by low transition, self calibration completes, described self-locking logical block makes enable signal ENABLE be low level by high level saltus step at once, thus close described clock generator 110, analogue unit 120 and digital units 130, like this, system is again in and treats wake-up states, and system power dissipation is minimum.Because described clock generator 110, analogue unit 120 and digital units 130 shares an enable signal ENABLE, therefore, they can close (or quitting work) simultaneously, in this process, may not finish the work and close with clock signal clk, because the work of digital units 130 is terminated in advance by number word cell 130.Therefore, the calibration data Data_Out<N:0> that digital units 130 exports is likely mistake, thus generation logic error, cause self-calibration circuit alignment error, specifically please refer to shown in Fig. 3, Fig. 3 is the sequential chart that alignment error appears in self-calibration circuit in Fig. 1.
In order to solve above-mentioned self-calibration circuit when calibration completes, because clock signal clk closes the problem of the erroneous results causing self calibration unit to export too early, timing management circuit is increased between the enable signal ENABLE of the present invention's self-calibration circuit in FIG and the Enable Pin of clock generator 110, again to manage the clock signal of self-calibration circuit, produce new sequential, thus realize calibration complete after several clock cycle of delay close described clock signal again.
Please refer to shown in Fig. 4, it is the circuit diagram of the present invention's self-calibration circuit in one embodiment.Self-calibration circuit shown in Fig. 4 comprises clock generator 410, self calibration unit 450, self-locking logical block (not shown) and timing management circuit 440.In one example, described self calibration unit 450 comprises analogue unit 420, digital units 430.
Wherein, the clock generator 410 in Fig. 4, analogue unit 420, digital units 430 and clock generator 110 corresponding in Fig. 1, analogue unit 120 are identical with the operation principle of digital units 130.Described clock generator 410 operationally produces also clock signal CLK and, to described analogue unit 420 and described digital units 430, thinks that described analogue unit 420 and described digital units 430 provide synchronised clock.Described analogue unit 420 is for comparison object analog signal and reference analog signal, and result exports calibration control signal to described digital units 430 based on the comparison, described digital units 430 is based on described calibration control signal adjustment calibration data, and described calibration data is fed back to described analogue unit 420, described analogue unit 420 is calibrated described target simulation signal based on the calibration data after adjustment.By continuous calibration, until described target simulation signal equals described reference analog signal, now self calibration completes, described analogue unit 420 sends effective self calibration locking signal Lock_Ready, and described digital units 430 exports the calibration data Data_out<N:0> calibrated.
The input of described timing management circuit 440 is connected with described enable signal ENABLE, its output is connected with the Enable Pin of described clock generator 410, its clock end is connected with the output of described clock generator 410, and described timing management circuit 440 gives the Enable Pin of described clock generator 410 based on described enable signal ENABLE output clock control signal T_CTL.When described enable signal ENABLE is significant level by inactive level saltus step, the clock control signal T_CTL that described timing management circuit 440 exports is significant level by inactive level saltus step; When described enable signal ENABLE is inactive level by significant level saltus step, after the clock control signal T_CTL that described timing management circuit 440 exports continues several clock cycle by significant level, saltus step is inactive level.Concrete, when described enable signal ENABLE is significant level by inactive level saltus step, system calibration starts; After system calibration completes, described analogue unit 420 exports effective self calibration locking signal Lock_Ready, described self-locking logical block makes described enable signal ENABLE be inactive level by significant level saltus step, now, after several clock cycle of described clock control signal T_CTL time delay, ability is inactive level by significant level saltus step.When described clock control signal T_CTL is significant level by inactive level saltus step, described clock generator 310 is worked, starts to export described clock signal clk; When described clock control signal T_CTL is inactive level by significant level saltus step, described clock generator 310 cuts out, stop exporting described clock signal clk, now analogue unit 420 and digital units 430 quit work.
Please refer to shown in Fig. 5, it is the timing management circuit circuit diagram in one embodiment in Fig. 4; Fig. 6 is for adopting the sequential chart of each signal of self-calibration circuit in Fig. 2 of the timing management circuit shown in Fig. 5.It should be noted that, in the embodiment shown in Fig. 5 and Fig. 6, the significant level of described enable signal ENABLE is logic high 1, and its inactive level is logic low 0, the significant level of described clock control signal T_CTL is high level, and its inactive level is low level.
First, please refer to shown in Fig. 5, the timing management circuit in Fig. 5 comprises logical operation module 510, first shift register 520, second shift register 530.The input of described first shift register 520 is connected with the input (namely with enable signal ENABLE) of described timing management circuit, the output of described first shift register 520 is connected with the input of described second shift register 530, the output of described second shift register 530 is connected with the first input end 1 of described logical operation module 510, and the first shift register 520 is all connected with the output (namely with clock signal clk) of described timing management circuit with the clock end of the second shift register 530.
Second input 2 of described logical operation module 510 is directly connected with the input of described timing management circuit, its output is connected with the output of described timing management circuit (i.e. described logical operation module 510 output clock control signal T_CTL), described logical operation module 510 carries out logical operation for the signal received its first input end and the second input, and will export described clock control signal T_CTL.
In the embodiment described in Fig. 5, described logical operation module 510 comprises NOR gate 512 and inverter INV1, an input of described NOR gate 512 is connected with the input of described timing management circuit, its another input is connected with the output of described second shift register 530, its output is connected with the input of described inverter INV1, and the output of inverter INV1 is connected with the output of described timing management circuit.Because an input of NOR gate 512 is directly connected with enable signal ENABLE, and another input is just being connected with enable signal ENABLE successively after two shift registers, therefore, according to NOR-operation rule, when enable signal ENABLE is 1 by 0 saltus step, the signal that described NOR gate 512 exports is 0 by 1 saltus step immediately, and the clock control signal T_CTL that logical operation module 510 is exported is 1 by 0 saltus step immediately, thus makes clock generator 410 clock signal immediately; When enable signal ENABLE is 0 by 1 saltus step, be 1 by 0 saltus step after two clock cycle of the signal delay clock signal clk that described NOR gate 512 exports, be 0 by 1 saltus step after the clock control signal T_CTL that logical operation module 510 is exported postpones two clock cycle, thus close again after making clock generator 410 postpone two clock cycle, (specifically shown in Figure 6).That is, when enable signal ENABLE is 1 by 0 saltus step, system starts immediately; When enable signal ENABLE is 0 by 1 saltus step, system delay is closed after two clock cycle again, enough processing times are reserved to give analogue unit 420 and digital units 430, thus can be implemented in after digital units 430 has been dealt with the work and respond enable signal ENABLE again, close clock signal.Like this, would not there is logic error due to the too early closedown of clock signal clk in the logic of the digital units 430 of system, thus can improve the accuracy of self-calibration circuit of the present invention.
In another embodiment, if the significant level of described enable signal ENABLE is logic high 1, its inactive level is logic low 0, but the significant level of described clock control signal T_CTL is low level, its inactive level is high level, then can save the inverter INV1 of the logical operation module 510 in Fig. 5, the output of described NOR gate 512 is directly connected with the output of described timing management circuit.
Known by the above-mentioned analysis to Fig. 5 and Fig. 6, quantity due to the shift register in the timing management circuit shown in Fig. 5 determines that clock generator 410 can time of late release, therefore, the quantity of the shift register in the timing management circuit shown in Fig. 5 can specifically be set as required.That is, timing management circuit in Fig. 5 can comprise N number of shift register, this N number of shift register is series between the input ENABLE of described timing management circuit and the first input end 1 of logical operation module 510 successively, wherein, the input of first displacement shift register is connected with the input ENABLE of described timing management circuit, the output of N number of shift register is connected with the first output 1 of described logical operation module 510, and the clock end CLK of each shift register is all connected with the output CLK of clock generator 410; Second input 2 of described logical operation module 510 is connected with the input ENABLE of described timing management circuit, and its output is connected with the output T_CTL of described timing management circuit.
Please refer to shown in Fig. 7, it is the clock generator circuit diagram in one embodiment in Fig. 2.Clock generator shown in Fig. 7 is ring oscillator, and this ring oscillator comprises starting of oscillation switch 710, inverter INV2, (2n+1) individual not gate, wherein, n be more than or equal to 1 natural number.All not gates successively first place are connected to form ring-type, a link of described starting of oscillation switch 710 is connected with power end VDD, its another link is connected with the control end of at least one not gate, the control end of described starting of oscillation switch 710 is connected with the output of inverter INV2, the input of described inverter INV2 is connected with the Enable Pin T-CTL of described clock generator, and the output CLK of described clock generator is connected with the connected node between adjacent two not gates.
In the embodiment shown in fig. 7, described starting of oscillation switch 710 is the source electrode of PMOS transistor MP1, this PMOS transistor MP1, drain and gate is respectively a link of described starting of oscillation switch 710, another link and control end.In another embodiment, the PMOS transistor MP1 in Fig. 7 also can be replaced nmos pass transistor, and the source electrode of corresponding described nmos pass transistor, drain and gate are respectively another link of described starting of oscillation switch 710, a link and control end; Save inverter INV2, the grid of nmos pass transistor is directly connected with the output T_CTL of described clock generator.
It should be noted that, the clock generator in the present invention also can be LC oscillator, RC oscillator isochronon generator.
In the present invention, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (7)
1. a self-calibration circuit, is characterized in that, it comprises timing management circuit, clock generator, self-locking logical block and self calibration unit,
Described clock generator comprises Enable Pin and output, and described clock generator is for generation of also giving described self calibration unit, using the clock signal as described self calibration unit by its output clock signal;
The clock signal that described self calibration unit is sent here based on clock generator completes self calibration, sends effective self calibration locking signal after self calibration completes,
The input of described timing management circuit is connected with enable signal, its output is connected with the Enable Pin of clock generator, described timing management circuit gives the Enable Pin of described clock generator based on described enable signal output clock control signal, when described enable signal is significant level by inactive level saltus step, the clock control signal that described timing management circuit exports is significant level by inactive level saltus step, when described clock control signal is significant level, described clock generator starts to export described clock signal; When described enable signal is inactive level by significant level saltus step, after the significant level of the clock control signal that described timing management circuit exports continues several clock cycle, saltus step is inactive level, when described clock signal is inactive level, described clock generator stops exporting described clock signal
Described self-locking logical block, when described self calibration unit exports effective self calibration locking signal, makes described enable signal be inactive level by significant level redirect.
2. self-calibration circuit according to claim 1, is characterized in that, described timing management circuit comprises logical operation module and N number of shift register,
Between the input that described N number of shift register is series at described timing management circuit successively and the first input end of logical operation circuit, wherein, the input of first displacement shift register is connected with the input of described timing management circuit, the output of N number of shift register is connected with the first output of described logical operation module, and the clock end of each shift register is all connected with the output of described clock generator; Second input of described logical operation module is directly connected with the input of described timing management circuit, its output is connected with the output of described timing management circuit, described logical operation module is used for carrying out logical operation to the signal that its first input end and the second input receive, and export described clock control signal
Wherein, N be more than or equal to 1 natural number.
3. self-calibration circuit according to claim 2, is characterized in that,
The significant level of described enable signal is high level, and its inactive level is low level; The significant level of described clock control signal is high level, and its inactive level is low level,
Described logical operation module comprises NOR gate and inverter INV1, an input of described NOR gate is connected with the input of described timing management circuit, another input of described NOR gate is connected with the output of N number of shift register, the output of described NOR gate is connected with the input of described inverter INV1, and the output of described inverter INV1 is connected with the output of described timing management circuit.
4. self-calibration circuit according to claim 1, is characterized in that,
Described clock generator is ring oscillator, and described ring oscillator comprises starting of oscillation switch, inverter INV2 and (2n+1) individual not gate, wherein, n be more than or equal to 1 natural number,
All not gates join end to end formation ring-type successively,
A link of described starting of oscillation switch is connected with power end, its another link is connected with the control end of at least one not gate, the control end of described starting of oscillation switch is connected with the output of inverter INV2, the input of described inverter INV2 is connected with the Enable Pin of described clock generator, and the output of described clock generator is connected with the connected node between adjacent two not gates.
5. self-calibration circuit according to claim 4, is characterized in that,
Described starting of oscillation switch is PMOS transistor, and the source electrode of described PMOS transistor, drain and gate are respectively a link of described starting of oscillation switch, another link and control end.
6. self-calibration circuit according to claim 1, is characterized in that, described clock generator is LC oscillator or RC oscillator.
7. self-calibration circuit according to claim 1, is characterized in that,
Described self calibration unit comprises analogue unit and digital units,
Described analogue unit is used for comparison object analog signal and reference analog signal, and result exports calibration control signal to described digital units based on the comparison, described digital units is based on described calibration control signal adjustment calibration data, and described calibration data is fed back to described analogue unit, described analogue unit is calibrated described target simulation signal based on the calibration data after adjustment, by continuous calibration, until described target simulation signal equals described reference analog signal, now self calibration completes, and sends effective self calibration locking signal.
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| CN201510458799.3A CN105141295B (en) | 2015-07-30 | 2015-07-30 | The self-calibration circuit of embedded clock |
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