CN1617439A - Self-calibrating crystal oscillator and its calibration method and its application-specific integrated circuit - Google Patents

Abstract

The invention discloses a crystal oscillator capable of self-calibrating, comprising: a phase comparator, a clock signal pad electrically connected to a first input of the phase comparator, an oscillating element electrically connected to a second input of the phase comparator, an analog/digital converter electrically connected to an output of the phase comparator, and a memory electrically connected to an output of the analog/digital converter. The oscillation element is a temperature compensation type oscillation element or a surface acoustic wave oscillation element. The self-calibratable crystal oscillator of the present invention may further comprise: the phase comparator comprises a first switch arranged between the first input end of the phase comparator and the clock signal pad, a second switch arranged between the oscillating element and the clock signal pad, and a logic control element for controlling the first switch and the second switch.

Description

Self-calibrating crystal oscillator and its calibration method and its application-specific integrated circuit

technical field

The present invention relates to a crystal oscillator, in particular, to a self-calibrating crystal oscillator, which can shorten the testing time of finished products and reduce the overall testing cost.

Background technique

Crystal oscillators are generally used in electronic products that require a stable output frequency, such as mobile communication electronic products such as mobile phones. Most of these crystal oscillators use an AT-cut quartz plate with a frequency of about 10MHz as a vibration source to form an oscillation circuit. Since the output frequency of the AT cut-off quartz plate will change with the surrounding temperature, a temperature compensation circuit must be designed to eliminate the change in the output frequency of the AT cut-off quartz plate.

FIG. 1 illustrates the relationship between the output frequency of an AT cut-off quartz plate and the ambient temperature. As shown in Figure 1, the output frequency of the AT cut-off quartz plate has a roughly cubic relationship with the ambient temperature, for example: f=αT ³ +βT ² +γT+δ. The cubic curve can be divided into three temperature ranges: low temperature, medium temperature and high temperature. In the low temperature range (-35°C to about +10°C), the curve contains a linear region of positive slope and a non-linear region that changes the polarity of the slope. In the middle temperature range (+10°C to +50°C), the curve has a linear region with a negative slope. In the high temperature range (+50°C to +90°C), the curve contains a linear region with a positive slope and a non-linear region that changes the polarity of the slope.

FIG. 2 is a circuit diagram of a conventional crystal oscillator 10 . As shown in FIG. 2 , the crystal oscillator 10 includes a temperature detection circuit 12 , an oscillation circuit 20 and a temperature compensation circuit 40 . The oscillation circuit 20 includes an AT cut-off quartz plate 22 , a feedback resistor 24 connected in parallel to the AT cut-off quartz plate 22 , and an inverter 26 connected in parallel to the AT cut-off quartz plate 22 . An output 28 of the crystal oscillator 10 projects from the output side of the inverter 26 . The oscillation circuit 20 also includes two DC blocking capacitors 32 , 34 and two variable capacitors 36 , 38 electrically connected to the two ends of the AT blocking quartz plate 22 . The temperature detection circuit 12 can use a thermistor to detect the temperature around the AT cut-off quartz plate 22, and the temperature compensation circuit 40 maintains the output frequency of the oscillation circuit 20 at a predetermined value according to the temperature detection signal from the temperature detection circuit 12.

The temperature compensation circuit 40 includes a storage circuit 42 and a digital/analog conversion circuit 44 . The storage circuit 42 is generally composed of a non-volatile memory, and is used to store compensation data required for temperature compensation (ie, parameters used to describe the cubic curve). The digital/analog conversion circuit 44 outputs a control voltage according to the compensation data and the temperature detection signal from the temperature detection circuit 12 , and the control voltage is respectively applied to the positive terminals of the variable capacitors 36 and 38 to adjust their oscillation capacitances. In this way, the oscillating frequency of the oscillating circuit 20 can be controlled, so that the output frequency of the crystal oscillator 10 can be maintained within the range allowed by product specifications.

Since the AT cut-off quartz pieces 22 are cut mechanically (laser), the thickness and cutting angle of each AT cut-off quartz piece 22 are not completely the same, resulting in their temperature-frequency characteristics are also different from each other. Similarly, the electronic components of the crystal oscillator 10 also have characteristic differences caused by process drift. All in all, there are differences between the crystal oscillators 10 due to the manufacturing process, so the temperature-frequency characteristics of each crystal oscillator 10 are also different, so it is necessary to measure the operating temperature range (high temperature) of each crystal oscillator 10. , middle and low temperature ranges) temperature-frequency characteristics, and according to generate temperature compensation data and then write in the storage circuit 42. However, measuring the temperature-frequency characteristics of each crystal oscillator 10 separately is a rather time-consuming task, resulting in a drastic increase in the overall testing cost of the crystal oscillator 10 .

Contents of the invention

The main purpose of the present invention is to provide a self-calibrating crystal oscillator, which can shorten the testing time of finished products and reduce the overall testing cost.

In order to achieve the above object, the present invention provides a self-calibrating crystal oscillator, which includes a phase comparator, a clock signal pad electrically connected to the first input end of the phase comparator, a clock signal pad electrically connected to the phase comparator An oscillating element at the second input end of the phase comparator, an analog/digital converter electrically connected to the output end of the phase comparator, and a memory electrically connected to the output end of the analog/digital converter. The oscillating element is a temperature compensation type oscillating element or a surface acoustic wave oscillating element, and the memory is a non-volatile memory.

The self-calibrating crystal oscillator of the present invention may further comprise a first switch disposed between the first input terminal of the phase comparator and the clock signal pad, a first switch disposed between the oscillating element and the clock signal pad The second switch and a logic control element for controlling the first switch and the second switch. When the crystal oscillator is performing self-calibration, the second switch is in the off state and the first switch is in the on state, so a reference clock can be transmitted to the first input terminal of the phase comparator through the clock signal pad . Correspondingly, when the crystal oscillator intends to output a clock signal, the first switch is in the off state and the second switch is in the on state, so the clock signal of the oscillating element can pass through the clock signal pad after temperature compensation And stable output.

Compared with the prior art, since the crystal oscillator of the present invention can calibrate itself after receiving the calibration signal, a test platform can perform temperature calibration simultaneously (in parallel) after several crystal oscillators are connected in parallel. In this way, the calibration time consumed by the test platform is equally divided by the several crystal oscillators, thereby reducing the calibration time of each crystal oscillator to reduce its test cost.

Description of drawings

Fig. 1 illustrates the relationship diagram of the output frequency of an AT cut-off quartz plate to the ambient temperature;

Fig. 2 is a circuit diagram of an existing crystal oscillator;

3 is a schematic diagram of a crystal oscillator according to the present invention;

Figure 4 is a functional block diagram of an integrated circuit according to the present invention;

Fig. 5 is the operation flowchart of crystal oscillator according to the present invention;

Fig. 6 is a parallel schematic diagram of a crystal oscillator according to the present invention;

Fig. 7 is a functional block diagram of an ASIC according to the present invention.

Explanation of component symbols in the figure:

50 crystal oscillator

52 Oscillating elements

60 integrated circuits

62, 102 clock signal pad

64 power pads

66 ground pad

68 control pad

70, 110 phase comparator,

70A, 110A first input terminal,

70B, 110B second input terminal,

70C, 110C output

72, 112 first switch

74, 114 Second switch

76 logic control element

78 High voltage detector

80, 120 Analog/Digital Converter

80C output

82, 134 digital/analog converter

84, 136 Temperature detector

90 memory

100 ASIC,

122 system bus, 124 built-in processor, 126 system memory

132 registers

Best Mode for Carrying Out the Invention

FIG. 3 is a schematic diagram of a self-calibrating crystal oscillator 50 according to the present invention. As shown in FIG. 3 , the self-calibrating crystal oscillator 50 includes an oscillating element 52, an integrated circuit 60 electrically connected to the oscillating element 52, a clock signal pad 62, a power pad 64, a ground pad 66, and a control Pad 68. The oscillating element 52 may be a temperature compensated oscillating element or a surface acoustic wave oscillating element.

FIG. 4 is a functional block diagram of an integrated circuit 60 according to the present invention. As shown in FIG. 4, the integrated circuit 60 includes a phase comparator 70, an analog/digital converter 80 electrically connected to the output terminal 70C of the phase comparator 70, and an output terminal 80C electrically connected to the analog/digital converter 80 memory 90. The clock signal pad 62 is electrically connected to the first input terminal 70A of the phase comparator 70 , and the oscillating element 52 is electrically connected to the second input terminal 70B of the phase comparator 70 . The memory 90 is a non-volatile memory.

The integrated circuit 60 according to the present invention may also include a first switch 72 disposed between the first input terminal 70A of the phase comparator 70 and the clock signal pad 62, a switch 72 disposed between the oscillator element 52 and the clock signal pad 62. The second switch 74 and a logic control element 76 for controlling the first switch 72 and the second switch 74 , wherein the data flow direction of the second switch 74 is opposite to the data flow direction of the first switch 72 . The working clock required for the operation of the logic control element 76 can be provided by a built-in clock generator (such as a resistor-capacitor clock generator). The integrated circuit 60 may also include a high voltage detector 78 electrically connected to the power pad 64 and the logic control element 76 .

When the crystal oscillator 50 is performing self-calibration, the logic control element 76 turns off the second switch 74 and turns on the first switch 72 . Therefore, a test platform can input a reference clock to the first input terminal 70A of the phase comparator 70 through the clock signal pad 62 and the first switch 72 . The phase comparator 70 compares the clock of the reference clock and the oscillating element 52 and generates a phase difference signal (ie, a frequency error signal), and the analog/digital converter 80 converts the phase difference signal into a digital signal (temperature compensation data) by A boosting circuit is stored in the memory 90 .

Correspondingly, when the crystal oscillator 50 intends to output a clock signal, the logic control element 76 will turn off the first switch 72 and turn on the second switch 74 . The digital/analog converter 82 then outputs a control voltage to calibrate the clock of the oscillating element 52 according to the temperature compensation data stored in the memory 90 and the temperature detection signal from the temperature detector 84, so that the clock of the oscillating element 52 is temperature-compensated It can be stably output through the second switch 74 and the clock signal pad 62 .

FIG. 5 is a flowchart of the operation of the crystal oscillator 50 according to the present invention. As shown in FIG. 5 , it is firstly checked whether the power supply voltage is higher than a threshold voltage, wherein the threshold voltage can be set as 120% of the power supply voltage, for example. If the supply voltage is lower than the threshold voltage, the crystal oscillator 50 is in a normal operation mode and outputs a temperature-compensated clock signal. If the power supply voltage is higher than the critical voltage, check whether the ambient temperature is the last calibration temperature (generally speaking, the crystal oscillator needs to be calibrated in three temperature ranges of low temperature, medium temperature and high temperature). If the last calibration temperature, the calibration procedure is terminated. If it is not the last calibration temperature, the oscillation element 52 is activated and a reference clock is input from the clock signal pad 62 . Then, the phase comparator 70 compares the reference clock with the clock of the oscillator 52 and generates a phase difference signal (ie, a frequency error signal). The analog/digital converter 80 then converts the frequency error signal into a digital signal, and writes it into the memory 90 through a boost circuit. Afterwards, the oscillating element 52 is turned off and the next temperature calibration is performed.

FIG. 6 is a schematic diagram of a parallel connection of a crystal oscillator 50 according to the present invention. Since the crystal oscillator 50 of the present invention can calibrate itself after receiving a voltage (i.e. a calibration signal) higher than 120% of the power supply voltage, the clock signal pad (CLK) 62, After the power pad (VDD) 64, the ground pad (GND) 66 and the control pad (PDN) 68, the reference clock is input from the clock signal pad 62 through a test platform, and the calibration signal is input through the power pad 64 to activate the logic control Element 76. Afterwards, the logic control element 76 of each crystal oscillator 50 can control itself and perform a temperature calibration procedure. That is, each crystal oscillator 50 is temperature calibrated simultaneously (in parallel).

FIG. 7 is a functional block diagram of an ASIC 100 according to the present invention. As shown in FIG. 7 , the ASIC 100 includes a system bus 122, a built-in processor 124 electrically connected to the system bus 122, a system memory 126 electrically connected to the system bus 122, a clock signal pad 102, an electrical The phase comparator 110 connected to the clock signal pad 102 , and an analog/digital converter 120 electrically connected to the output terminal 110C of the phase comparator 110 . The analog/digital converter 120 is also electrically connected to the system bus 122 to transmit its output to the system memory 124 via the system bus 122 . The ASIC 100 also includes a first switch 112 disposed between the first input terminal 110A of the phase comparator 110 and the clock signal pad 102, and a first switch 112 disposed between an external oscillating element 130 and the clock signal pad 102. Two switches 114 .

When the ASIC 100 performs temperature calibration of the external oscillating element 130 , the built-in processor 124 transmits a control command via the system bus 122 to turn off the second switch 114 and turn on the first switch 112 . Therefore, a test platform can input a reference clock to the first input terminal 110A of the phase comparator 110 through the clock signal pad 102 and the first switch 112 . The phase comparator 110 compares the reference clock with the clock of the external oscillating element 130 and generates a phase difference signal (ie, a frequency error signal), and the analog/digital converter 120 converts the frequency error signal into a digital signal (temperature compensation data) It is then stored in the system memory 126 via the system bus 122 .

Correspondingly, when the ASIC 100 intends to output a clock signal, the embedded processor 124 transmits a control command via the system bus 122 to close the first switch 112 and open the second switch 114, and store the temperature in the system memory 106 The compensation data is loaded into the buffer 132 . The digital/analog converter 134 outputs a control voltage to calibrate the clock of the external oscillator 130 according to the temperature compensation data stored in the register 132 and the temperature detection signal from the temperature detector 136 . Therefore, the clock of the external oscillating element 130 can be stably output through the second switch 114 and the clock signal pad 102 after temperature compensation.

Compared with the prior art, since the crystal oscillator 50 according to the present invention can calibrate itself after receiving the calibration signal, a test platform can simultaneously (in parallel) carry out temperature calibration after several crystal oscillators 50 are connected in parallel . In this way, the calibration time consumed by the test platform is equally divided by several crystal oscillators 50, thereby reducing the calibration time of each crystal oscillator 50 and reducing its test cost.

As mentioned above, the technical content and technical characteristics of the present invention have been disclosed, however, those skilled in the art can still make various replacements and modifications without departing from the spirit of the present invention according to the teaching and disclosure of the present invention. Therefore, the protection scope of the present invention should not be limited to the contents disclosed in the embodiments, but should include various replacements and modifications that do not deviate from the present invention, and are covered by the claims of this patent application.

Claims (13)

1. A self-calibrating crystal oscillator, characterized in that it comprises: A phase comparator, including a first input terminal, a second input terminal and an output terminal; a clock signal pad electrically connected to the first input terminal; an oscillating element electrically connected to the second input terminal; an analog/digital converter electrically connected to the output of the phase comparator; A memory is electrically connected to the output terminal of the analog/digital converter. 2. The self-calibrating crystal oscillator as claimed in claim 1, wherein the oscillating element is a temperature-compensated oscillating element or a surface acoustic wave oscillating element. 3. The self-calibrating crystal oscillator as claimed in claim 1, further comprising: a first switch disposed between the first input terminal of the phase comparator and the clock signal pad; A second switch is arranged between the oscillating element and the clock signal pad, and the data flow direction of the second switch is opposite to that of the first switch; A logic control element is used for controlling the first switch and the second switch. 4. The self-calibrating crystal oscillator as claimed in claim 3, further comprising: a power pad; A high voltage detector is electrically connected to the power pad and the logic control element. 5. The self-calibrating crystal oscillator as claimed in claim 3, further comprising a built-in clock generator for providing the working clock required for the operation of the logic control element. 6. The self-calibrating crystal oscillator as claimed in claim 5, wherein the built-in clock generator is a resistor-capacitor oscillator. 7. An ASIC of a crystal oscillator, characterized in that it comprises: a system bus; a built-in processor electrically connected to the system bus; a system memory electrically connected to the system bus; a clock signal pad capable of receiving a reference clock; a phase comparator for generating the clock of the oscillating element of the crystal oscillator and the frequency error of the reference clock; An analog/digital converter is used to convert the frequency error into a digital signal and store it in the system memory through the system bus. 8. The application specific integrated circuit of crystal oscillator as claimed in claim 7, is characterized in that also comprising: a first switch disposed between the phase comparator and the clock signal pad; A second switch is arranged between the oscillating element and the clock signal pad. 9. The ASIC of a crystal oscillator as claimed in claim 8, further comprising a register electrically connected to the system bus for storing data of the system memory when the second switch is turned on. 10. A calibration method for a crystal oscillator, characterized in that it comprises the following steps: Connect several crystal oscillators in parallel; inputting a test activation signal and a reference clock to the plurality of crystal oscillators from a test platform; Each crystal oscillator compares the clock of its internal oscillating element with the reference clock, and generates a frequency error signal; Each crystal oscillator writes the frequency error signal into its internal memory. 11. The method for calibrating a crystal oscillator as claimed in claim 10, wherein the test activation signal is a voltage higher than a threshold voltage. 12. The method for calibrating crystal oscillators as claimed in claim 10, further comprising a step of each crystal oscillator checking whether an ambient temperature is equal to a final calibration temperature. 13. The method for calibrating a crystal oscillator as claimed in claim 10, further comprising a step of converting the frequency error signal into a digital signal.

Images