CN105141295B - The self-calibration circuit of embedded clock - Google Patents
The self-calibration circuit of embedded clock Download PDFInfo
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- CN105141295B CN105141295B CN201510458799.3A CN201510458799A CN105141295B CN 105141295 B CN105141295 B CN 105141295B CN 201510458799 A CN201510458799 A CN 201510458799A CN 105141295 B CN105141295 B CN 105141295B
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Abstract
The present invention provides a kind of self-calibration circuit of embedded clock, and it includes timing management circuit, clock generator and self calibration unit.Clock generator is used to produce and export clock signal by its output end to give self calibration unit.Self calibration unit completes self calibration based on the clock signal that clock generator is sent, and effective self calibration locking signal is sent after the completion of self calibration.The input of timing management circuit is connected with enabling signal, and its output end is connected with the Enable Pin of clock generator.When it is significant level to enable signal by inactive level saltus step, the clock control signal that timing management circuit is exported is significant level by inactive level saltus step；When it is inactive level to enable signal by significant level saltus step, it is inactive level that the significant level of the clock control signal of timing management circuit output, which continues saltus step after several clock cycle,.So, it can solve due to the problem of clock signal closing causes to produce logic error too early.
Description
【Technical field】
The present invention relates to technical field of circuit design, more particularly to a kind of self-calibration circuit of embedded clock.
【Background technology】
Self-calibration circuit in the course of the work, typically provides clock by its exterior, but in order to reduce system design
Complexity considers that embedded clock technology has been increasingly becoming main flow, but embedded clock also has one disadvantage in that：Due to system close when
Wait, clock signal is also simultaneously closed off.Therefore, some circuit modules can be caused signal to be sent out can not in time, so as to produce
Logic error.
Therefore, it is necessary to provide a kind of improved technical scheme to solve the above problems.
【The content of the invention】
It is an object of the invention to provide a kind of self-calibration circuit of embedded clock, it can make after the completion of self calibration
The closing of several cycles of clock signal delay is obtained, so as to solve to cause to produce logic error because clock signal is closed too early
Problem.
In order to solve the above problems, the present invention provides a kind of self-calibration circuit, and it, which includes timing management circuit, clock, occurs
Device, self-locking logic unit and self calibration unit.The clock generator includes Enable Pin and output end, and the clock generator is used
In producing and exporting clock signal to the self calibration unit by its output end, using the clock letter as the self calibration unit
Number.The self calibration unit completes self calibration based on the clock signal that clock generator is sent, and has been sent after the completion of self calibration
The self calibration locking signal of effect.The input of the timing management circuit is connected with enabling signal, and its output end occurs with clock
The Enable Pin of device is connected, and the timing management circuit is based on the enable signal output clock control signal to be occurred to the clock
The Enable Pin of device, when the enable signal is significant level by inactive level saltus step, timing management circuit output when
Clock control signal is significant level by inactive level saltus step, when the clock control signal is significant level, the clock hair
Raw device starts to export the clock signal；When the enable signal is inactive level by significant level saltus step, the sequential pipe
Managing the significant level of the clock control signal of circuit output, to continue after several clock cycle saltus step be inactive level, when described
When clock signal is inactive level, the clock generator stops the output clock signal.The self-locking logic unit is described
When self calibration unit exports effective self calibration locking signal so that the enable signal is redirected as invalid electricity by significant level
It is flat.
Further, the timing management circuit includes logical operation module and N number of shift register, N number of displacement
Register is sequentially connected in series between the input of the timing management circuit and the first input end of logical operation circuit, wherein,
The input of first displacement shift register is connected with the input of the timing management circuit, n-th shift register
Output end is connected with the first output end of the logical operation module, and the clock end of each shift register is sent out with the clock
The output end of raw device is connected；Input phase of second input of the logical operation module directly with the timing management circuit
Even, its output end is connected with the output end of the timing management circuit, and the logical operation module is used for its first input end
Logical operation is carried out with the signal that the second input is received, and exports the clock control signal, wherein, N is more than or equal to 1
Natural number.
Further, the significant level for enabling signal is high level, and its inactive level is low level；Clock when described
The significant level of signal processed is high level, and its inactive level is low level, and the logical operation module includes nor gate and anti-phase
Device INV1 a, input of the nor gate is connected with the input of the timing management circuit, the nor gate it is another
Individual input is connected with the output end of n-th shift register, and the output end of the nor gate is defeated with the phase inverter INV1's
Enter end to be connected, the output end of the phase inverter INV1 is connected with the output end of the timing management circuit.
Further, the clock generator is ring oscillator, and the ring oscillator includes starting of oscillation switch, phase inverter
INV2 and (2n+1) individual NOT gate, wherein, n is the natural number more than or equal to 1, and all NOT gates join end to end to form ring-type successively, institute
A connection end for stating starting of oscillation switch is connected with power end, and its another connection end is connected with the control end of at least one NOT gate, institute
The control end for stating starting of oscillation switch is connected with phase inverter INV2 output end, and input and the clock of the phase inverter INV2 are sent out
The Enable Pin of raw device is connected, and the connecting node between the output end of the clock generator and two adjacent NOT gates is connected.
Further, the starting of oscillation switch is PMOS transistor, the source electrode of the PMOS transistor, drain and gate difference
A connection end, another connection end and the control end switched for the starting of oscillation.
Further, the clock generator is LC oscillators or RC oscillators.
Further, the self calibration unit includes analogue unit and digital units, and the analogue unit is used to compare mesh
Analog signal and reference analog signal are marked, and calibration control signal is exported to the digital units, the number based on comparative result
Word cell is based on the calibration control signal adjustment calibration data, and the calibration data is fed back into the analogue unit, institute
Analogue unit is stated to calibrate the target simulation signal based on the calibration data after adjustment, by constantly calibrating, until
The target simulation signal is equal to the reference analog signal, and now self calibration is completed, and sends effective self calibration locking signal.
Compared with prior art, the present invention self-calibration circuit the Enable Pin for enabling signal and embedded clock generator it
Between increase timing management circuit, the timing management circuit is managed again based on signal is enabled to the clock signal of self-calibration circuit
Reason, produces new sequential, so that when it is inactive level signal to enable signal by the saltus step of significant level signal, and clock signal can be with
Turned off after continuing several clock cycle, so that clock signal is turned off after realizing several cycles upon completion of the calibration,
To solve because clock signal closes the problem of causing to produce logic error too early.
【Brief description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, being used required in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also obtain other according to these accompanying drawings
Accompanying drawing.Wherein：
Fig. 1 is a kind of circuit diagram of self-calibration circuit；
Fig. 2 be Fig. 1 in self-calibration circuit in each signal timing diagram；
Fig. 3 is that the self-calibration circuit in Fig. 1 the timing diagram of alignment error occurs.
The circuit diagram of self-calibration circuits of the Fig. 4 for the present invention in one embodiment；
Circuit diagrams of the Fig. 5 for the timing management circuit in Fig. 4 in one embodiment；
Fig. 6 is using the timing diagram of each signal of self-calibration circuit in Fig. 2 of the timing management circuit shown in Fig. 5；
Circuit diagrams of the Fig. 7 for the clock generator in Fig. 2 in one embodiment.
【Embodiment】
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one implementation of the invention
Special characteristic, structure or characteristic." in one embodiment " that different places occur in this manual not refers both to same
Individual embodiment, nor the single or selective embodiment mutually exclusive with other embodiment.Unless stated otherwise, herein
In connect, be connected, connecting expression be electrically connected with word represent directly or indirectly to be electrical connected.
It refer to shown in Fig. 1, it is a kind of circuit diagram of self-calibration circuit.When self-calibration circuit in Fig. 1 includes
Clock generator 110 and self calibration unit 140.
The Enable Pin of the clock generator 110 is connected with enabling signal ENABLE, and the enable signal ENABLE is used for
The clock generator 110 is controlled to work or close, so as to control the work or closing of self calibration unit 140；The self calibration
Unit 140 completes self calibration based on the clock signal that clock generator is sent, and effective self calibration is sent after the completion of self calibration
Locking signal Lock_Ready.
The self-calibration circuit also includes self-locking logic unit (not shown), and the self-locking logic unit is in self calibration unit
During the 140 effective self calibration locking signal Lock_Ready of output so that the enable signal ENABLE is redirected by significant level
For inactive level, so described clock generator 110 is not just in output clock signal, and the self calibration unit 110 also stops work
Make, complete self closing in time for self-calibration circuit.
In one example, the self calibration unit 140 includes analogue unit 120 and digital units 130.
The clock generator 110 operationally produces and exports clock signal clk to the analogue unit 120 and described
Digital units 130, to be that the analogue unit 120 and the digital units 130 provide synchronised clock.The analogue unit 120
Calibration control signal is exported to the numeral list for comparison object analog signal and reference analog signal, and based on comparative result
Member 130, the digital units 130 are based on the calibration control signal adjustment calibration data, and the calibration data is fed back to
The analogue unit 120, the analogue unit 120 carries out school based on the calibration data after adjustment to the target simulation signal
It is accurate.By constantly calibrating, until the target simulation signal is equal to the reference analog signal, now self calibration is completed, institute
State analogue unit 120 and send effective self calibration locking signal Lock_Ready, what the output of digital units 130 calibration was completed
Calibration data Data_out<N：0>.Wherein described target simulation signal can be electric current or voltage, the reference mould
Intend the reference value that signal can be predefined.In some examples, the analogue unit 430 is based on calibration data and turns on or close
A disconnected calibration switch, so as to realize the adjustment for the target simulation signal.However, relevant self calibration unit 140 is completed
The technology contents of self-calibrating belong to prior art, and the present invention is unrelated with the specific self calibration that how to complete, therefore at this
This is not elaborated in invention.
Refer to shown in Fig. 2, its be Fig. 1 in self-calibration circuit in each signal timing diagram.Introduced based on Fig. 2 in Fig. 1
Calibration circuit the course of work, due to clock generator 110 be embedded clock generator, therefore, when enable signal ENABLE
When by low transition being high level, clock generator 110 is started working, and export clock signal clk, so that simulation
Unit 120 and digital units 130 work together.When the self calibration locking signal Lock_Ready of the output of analogue unit 120 is by low
When level saltus step is high (significant level), self calibration is completed, the self-locking logic unit to enable signal ENABLE at once by
High level saltus step is low level, so as to close the clock generator 110, analogue unit 120 and digital units 130, so, is
System is again at treating wake-up states, and system power dissipation is minimum.Due to the clock generator 110, analogue unit 120 and digital units
130 share an enable signal ENABLE, and therefore, they can simultaneously close off (or being stopped), in this process, may
There are digital units 130 not complete work and close with clock signal clk, the work due to digital units 130 is tied in advance
Beam.Therefore, the calibration data Data_Out that digital units 130 are exported<N:0>Mistake is likely to, so that it is wrong to produce logic
By mistake, cause self-calibration circuit alignment error, specifically refer to shown in Fig. 3, Fig. 3 is that the self-calibration circuit in Fig. 1 calibration mistake occurs
Timing diagram by mistake.
In order to solve above-mentioned self-calibration circuit when calibrating completion, closed due to clock signal clk causes self calibration too early
The problem of result mistake of unit output, the enable signal ENABLE and clock of the self-calibration circuit of the present invention in Fig. 1 occur
Increase timing management circuit between the Enable Pin of device 110, managed again with the clock signal to self-calibration circuit, when producing new
Sequence, so that postponing several clock cycle after the completion of realizing calibration turns off the clock signal.
It refer to shown in Fig. 4, it is the circuit diagram of the self-calibration circuit of the present invention in one embodiment.Fig. 4 institutes
The self-calibration circuit shown includes clock generator 410, self calibration unit 450, self-locking logic unit (not shown) and timing management
Circuit 440.In one example, the self calibration unit 450 includes analogue unit 420, digital units 430.
Wherein, in Fig. 4 clock generator 410, analogue unit 420, digital units 430 clock hair corresponding with Fig. 1
Raw device 110, analogue unit 120 are identical with the operation principle of digital units 130.The clock generator 410 is operationally produced
And clock signal clk is exported to the analogue unit 420 and the digital units 430, think the analogue unit 420 and described
Digital units 430 provide synchronised clock.The analogue unit 420 is used for comparison object analog signal and reference analog signal, and
Calibration control signal is exported to the digital units 430 based on comparative result, the digital units 430 are based on the calibration control
Signal adjusts calibration data, and the calibration data is fed back into the analogue unit 420, and the analogue unit 420 is based on adjusting
Calibration data after whole is calibrated to the target simulation signal.By constantly calibrating, until the target simulation signal
Equal to the reference analog signal, now self calibration completion, the analogue unit 420 sends effective self calibration locking signal
Lock_Ready, the calibration data Data_out that the output of digital units 430 calibration is completed<N：0>.
The input of the timing management circuit 440 is connected with the enable signal ENABLE, its output end with it is described when
The Enable Pin of clock generator 410 is connected, and its clock end is connected with the output end of the clock generator 410, the timing management
Circuit 440 exports enables of the clock control signal T_CTL to the clock generator 410 based on the enable signal ENABLE
End.When the enable signal ENABLE is significant level by inactive level saltus step, the timing management circuit 440 export when
Clock control signal T_CTL is significant level by inactive level saltus step；When the enable signal ENABLE by significant level saltus step is
During inactive level, the clock control signal T_CTL that the timing management circuit 440 is exported continues several clocks by significant level
Saltus step is inactive level after cycle.Specifically, it is significant level, system to work as the enable signal ENABLE by inactive level saltus step
Calibration starts；After the completion of system calibration, the analogue unit 420 exports effective self calibration locking signal Lock_Ready,
The self-locking logic unit causes the enable signal ENABLE to be inactive level, now, the clock by significant level saltus step
It is just inactive level by significant level saltus step that control signal T_CTL, which was delayed after several clock cycle,.When clock control letter
When number T_CTL is significant level by inactive level saltus step, the clock generator 310 is worked, start to export the clock letter
Number CLK；When the clock control signal T_CTL is inactive level by significant level saltus step, close the clock generator 310
Close, stop the output clock signal clk, now analogue unit 420 and digital units 430 are stopped.
It refer to shown in Fig. 5, it is the timing management circuit circuit diagram in one embodiment in Fig. 4；Fig. 6 is
Using the timing diagram of each signal of self-calibration circuit in Fig. 2 of the timing management circuit shown in Fig. 5.It should be noted that in Fig. 5
In the embodiment shown in Fig. 6, the significant level for enabling signal ENABLE is logic high 1, and its inactive level is to patrol
Low level 0 is collected, the significant level of the clock control signal T_CTL is high level, and its inactive level is low level.
First, it refer to shown in Fig. 5, the timing management circuit in Fig. 5 includes the displacement of logical operation module 510, first and posted
Storage 520, the second shift register 530.The input of first shift register 520 is defeated with the timing management circuit
Enter end (i.e. with enabling signal ENABLE) to be connected, the output end of first shift register 520 and second shift LD
The input of device 530 is connected, and the first of the output end of second shift register 530 and the logical operation module 510 is defeated
Enter end 1 to be connected, the clock end of the first shift register 520 and the second shift register 530 with the timing management circuit
Output end (i.e. with clock signal clk) is connected.
Input of second input 2 of the logical operation module 510 directly with the timing management circuit is connected, its
Output end is connected with the output end of the timing management circuit, and (i.e. described logical operation module 510 exports clock control signal T_
CTL), the signal that the logical operation module 510 is used to receive its first input end and the second input carries out logic fortune
Calculate, and the clock control signal T_CTL will be exported.
In the embodiment described in Fig. 5, the logical operation module 510 includes nor gate 512 and phase inverter INV1, described
One input of nor gate 512 is connected with the input of the timing management circuit, its another input and described second
The output end of shift register 530 is connected, and its output end is connected with the input of the phase inverter INV1, and phase inverter INV1's is defeated
Go out end with the output end of the timing management circuit to be connected.Because an input of nor gate 512 is directly with enabling signal
ENABLE is connected, and another input is just connected after two shift registers are sequentially passed through with enabling signal ENABLE, because
This, according to NOR-operation rule, when it is 1 to enable signal ENABLE by 0 saltus step, the signal that the nor gate 512 is exported is immediately
It is 0 by 1 saltus step, it is immediately 1 by 0 saltus step to make the clock control signal T_CTL that logical operation module 510 is exported, so that clock
Generator 410 exports clock signal immediately；When it is 0 to enable signal ENABLE by 1 saltus step, the letter that the nor gate 512 is exported
By 0 saltus step it is 1 after number delay clock signals CLK two clock cycle, the clock control letter for exporting logical operation module 510
It is 0 that number T_CTL, which postpones after two clock cycle by 1 saltus step, so that so that clock generator 410 postpones after two clock cycle again
Close, (specific shown in Figure 6).That is, when it is 1 to enable signal ENABLE by 0 saltus step, system starts immediately；
When it is 0 to enable signal ENABLE by 1 saltus step, system delay is turned off after two clock cycle, to give the sum of analogue unit 420
Word cell 430 reserves enough processing times, makes so as to realize to respond again after the processing work of digital units 430 is completed
Can signal ENABLE, closing clock signal.So, the logic of the digital units 430 of system would not be due to clock signal clk
Close too early and logic error occur, so as to the accuracy for the self-calibration circuit for improving the present invention.
In another embodiment, if the significant level for enabling signal ENABLE is logic high 1, its invalid electricity
Put down as logic low 0, but the significant level of the clock control signal T_CTL is low level, and its inactive level is high level,
The phase inverter INV1 of the logical operation module 510 in Fig. 5 can then be saved, make the output end of the nor gate 512 directly with it is described
The output end of timing management circuit is connected.
By the above-mentioned analysis to Fig. 5 and Fig. 6, due to the shift register in the timing management circuit shown in Fig. 5
Quantity determine clock generator 410 can late release time, therefore, the sequential shown in Fig. 5 can be specifically set as needed
Manage the quantity of the shift register in circuit.That is, the timing management circuit in Fig. 5 can include N number of shift LD
Device, this N number of shift register is sequentially connected in series input ENABLE and logical operation module 510 in the timing management circuit
Between first input end 1, wherein, the input of first displacement shift register and the input of the timing management circuit
ENABLE is connected, and the output end of n-th shift register is connected with the first output end 1 of the logical operation module 510, each
The clock end CLK of shift register is connected with the output end CLK of clock generator 410；The of the logical operation module 510
Two inputs 2 are connected with the input ENABLE of the timing management circuit, and its output end is defeated with the timing management circuit
Go out to hold T_CTL to be connected.
It refer to shown in Fig. 7, it is the clock generator circuit diagram in one embodiment in Fig. 2.Shown in Fig. 7
Clock generator be ring oscillator, the ring oscillator include starting of oscillation switch 710, phase inverter INV2, (2n+1) individual NOT gate,
Wherein, n is the natural number more than or equal to 1.First place is connected to form ring-type, one of the starting of oscillation switch 710 to all NOT gates successively
Connection end is connected with power end VDD, and its another connection end is connected with the control end of at least one NOT gate, the starting of oscillation switch 710
Control end be connected with phase inverter INV2 output end, the input of the phase inverter INV2 and the enable of the clock generator
T-CTL is held to be connected, the connecting node between the output end CLK of the clock generator and two adjacent NOT gates is connected.
In the embodiment shown in fig. 7, the starting of oscillation switch 710 is PMOS transistor MP1, PMOS transistor MP1's
Source electrode, drain and gate are respectively a connection end, another connection end and the control end of the starting of oscillation switch 710.At another
In embodiment, the PMOS transistor MP1 in Fig. 7 also can be replaced nmos pass transistor, the source electrode of the corresponding nmos pass transistor,
Drain and gate is respectively another connection end, a connection end and the control end of the starting of oscillation switch 710；Save phase inverter
INV2, makes the grid of nmos pass transistor directly be connected with the output end T_CTL of the clock generator.
It should be noted that the clock generator in the present invention can also occur for LC oscillators, RC oscillators isochronon
Device.
In the present invention, " connection ", connected, " company ", " connecing " etc. represent the word being electrical connected, unless otherwise instructed, then
Represent direct or indirect electric connection.
It is pointed out that any change that one skilled in the art is done to the embodiment of the present invention
All without departing from the scope of claims of the present invention.Correspondingly, the scope of claim of the invention is also not merely limited to
In previous embodiment.
Claims (7)
1. a kind of self-calibration circuit, it is characterised in that it include timing management circuit, clock generator, self-locking logic unit and
Self calibration unit,
The clock generator includes Enable Pin and output end, and the clock generator is used to produce and export by its output end
Clock signal gives the self calibration unit, using the clock signal as the self calibration unit；
The self calibration unit completes self calibration based on the clock signal that clock generator is sent, and has been sent after the completion of self calibration
The self calibration locking signal of effect,
The input of the timing management circuit is connected with enabling signal, and its output end is connected with the Enable Pin of clock generator,
The timing management circuit gives the Enable Pin of the clock generator based on the enable signal output clock control signal, works as institute
When to state enable signal be significant level by inactive level saltus step, the clock control signal of timing management circuit output is by invalid
Level saltus step is significant level, and when the clock control signal is significant level, it is described that the clock generator starts output
Clock signal；When the enable signal is inactive level by significant level saltus step, the clock of the timing management circuit output
It is inactive level that the significant level of control signal, which continues saltus step after several clock cycle, is invalid in the clock control signal
During level, the clock generator stops the output clock signal,
The self-locking logic unit is when the self calibration unit exports effective self calibration locking signal so that the enable letter
Number redirected by significant level as inactive level.
2. self-calibration circuit according to claim 1, it is characterised in that the timing management circuit includes logical operation mould
Block and N number of shift register,
N number of shift register be sequentially connected in series in the timing management circuit input and logical operation module it is first defeated
Enter between end, wherein, the input of first displacement shift register is connected with the input of the timing management circuit, N
The output end of individual shift register is connected with the first input end of the logical operation module, the clock end of each shift register
Output end with the clock generator is connected；Second input of the logical operation module directly with the timing management
The input of circuit is connected, and its output end is connected with the output end of the timing management circuit, and the logical operation module is used for
The signal that is received to its first input end and the second input carries out logical operation, and exports the clock control signal,
Wherein, N is the natural number more than or equal to 1.
3. self-calibration circuit according to claim 2, it is characterised in that
The significant level for enabling signal is high level, and its inactive level is low level；The clock control signal it is effective
Level is high level, and its inactive level is low level,
The logical operation module includes nor gate and phase inverter INV1, an input and the sequential pipe of the nor gate
The input for managing circuit is connected, and another input of the nor gate is connected with the output end of n-th shift register, described
The output end of nor gate is connected with the input of the phase inverter INV1, the output end of the phase inverter INV1 and the sequential pipe
The output end for managing circuit is connected.
4. self-calibration circuit according to claim 1, it is characterised in that
The clock generator is ring oscillator, and the ring oscillator includes starting of oscillation switch, phase inverter INV2 and (2n+1)
Individual NOT gate, wherein, n is the natural number more than or equal to 1,
All NOT gates join end to end to form ring-type successively,
One connection end of the starting of oscillation switch is connected with power end, its another connection end and the control end phase of at least one NOT gate
Even, the control end of starting of oscillation switch is connected with phase inverter INV2 output end, the input of the phase inverter INV2 with it is described
The Enable Pin of clock generator is connected, the connecting node phase between the output end of the clock generator and two adjacent NOT gates
Even.
5. self-calibration circuit according to claim 4, it is characterised in that
The starting of oscillation switch is PMOS transistor, and source electrode, the drain and gate of the PMOS transistor are respectively that the starting of oscillation is opened
A connection end, another connection end and the control end closed.
6. self-calibration circuit according to claim 1, it is characterised in that the clock generator is that LC oscillators or RC shake
Swing device.
7. self-calibration circuit according to claim 1, it is characterised in that
The self calibration unit includes analogue unit and digital units,
The analogue unit is used for comparison object analog signal and reference analog signal, and based on comparative result output calibration control
Signal gives the digital units, and the digital units are based on the calibration control signal adjustment calibration data, and by the calibration
Data feedback gives the analogue unit, and the analogue unit is carried out based on the calibration data after adjustment to the target simulation signal
Calibration, by constantly calibrating, until the target simulation signal is equal to the reference analog signal, now self calibration is completed,
Send effective self calibration locking signal.
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| CN109756104B (en) * | 2017-11-07 | 2024-03-22 | 华润微集成电路(无锡)有限公司 | Two-phase dynamic synchronous clock generation circuit applied to charge pump system |
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| CN103066996A (en) * | 2012-12-20 | 2013-04-24 | 上海宏力半导体制造有限公司 | Oscillator and self-calibration method thereof |
| CN104135256A (en) * | 2014-07-29 | 2014-11-05 | 东南大学 | A delay sampling circuit having self-calibration function |
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