CN112787634B

CN112787634B - Circuit for correcting clock duty ratio and correction control method and device thereof

Info

Publication number: CN112787634B
Application number: CN202011611919.6A
Authority: CN
Inventors: 刘成
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2023-09-29
Anticipated expiration: 2040-12-30
Also published as: CN112787634A

Abstract

The present invention relates to clock correction of memory chips, and more particularly, to a circuit for correcting a clock duty cycle, and a correction control method and apparatus thereof. The circuit comprises: a clock delay correction circuit, a pulse width generation circuit, an integration circuit, a comparator circuit and a state machine circuit; the pulse width generating circuit, the integrating circuit, the comparator circuit and the state machine circuit are sequentially connected in series between the correction output end and the correction control end. According to the invention, two paths of rising edge trigger signals are used as transistor on-off control signals to trigger two paths of voltage signals, so that the comparator circuit detects the phase shift state quantity of a certain correction four-phase clock signal through the difference of voltage detection values of the two paths of voltage signals, and then the state machine outputs a corresponding correction control signal to control the clock delay correction circuit to carry out delay control on the original four-phase clock signal according to the state quantity, thereby realizing rapid and accurate clock duty ratio correction on a high-speed clock.

Description

Circuit for correcting clock duty ratio and correction control method and device thereof

Technical Field

The present invention relates to clock correction of memory chips, and more particularly, to a circuit for correcting a clock duty cycle, and a correction control method and apparatus thereof.

Background

Fig. 1 is a schematic diagram of clock control logic of eye diagram data of a conventional memory chip, in which a PLL (phase lock loop) frequency doubling circuit outputs high-frequency clock signals clk_t and clk_c with frequency F; then, clock signals clk_000, clk_090, clk_180 and clk_270 with four phases of frequencies of F/2 are output through frequency division processing of a frequency divider; thereafter, a pulse signal pul_0 is generated from the rising edges of clk_000 and clk_090, a pulse signal pul_1 is generated from the rising edges of clk_090 and clk_180, a pulse signal pul_2 is generated from the rising edges of clk_180 and clk_270, and a pulse signal pul_3 is generated from the rising edges of clk_270 and clk_000, wherein the pulse width of each pulse signal is one quarter of a high frequency clock cycle; finally, the eye pattern data d0 is outputted from the high level of the pulse signal pul_0, the eye pattern data d1 is outputted from the high level of the pulse signal pul_1, the eye pattern data d2 is outputted from the high level of the pulse signal pul_2, and the eye pattern data d3 is outputted from the high level of the pulse signal pul_3.

Since the data width of the eye pattern data d0, d1, d2, d3 is completely dependent on the high level width of the pulse signals pul_0, pul_1, pul_2, pul_3, that is, dependent on the phase difference between clk_000, clk_090, clk_180, clk_270. Then when the phase difference between clk_000, clk_090, clk_180, and clk_270 is not the standard 90 °, the data width of the output data eye patterns d0, d1, d2, and d3 deviate from the standard width, which affects the final eye pattern analysis result.

Therefore, how to perform fast and accurate clock duty cycle correction on a high-speed clock is a technical problem that needs to be solved at present.

Disclosure of Invention

The invention aims to provide a circuit for correcting clock duty ratio, a correction control method and a correction control device thereof, so as to carry out quick and accurate clock duty ratio correction on a high-speed clock.

The embodiment of the invention provides the following scheme:

in a first aspect, an embodiment of the present invention provides a circuit for correcting a clock duty cycle, including: a clock delay correction circuit, a pulse width generation circuit, an integration circuit, a comparator circuit and a state machine circuit;

the clock delay correction circuit comprises a correction input end for inputting an original four-phase clock signal, a correction output end for outputting a correction four-phase clock signal and a correction control end for inputting a clock delay correction control signal;

the pulse width generating circuit, the integrating circuit, the comparator circuit and the state machine circuit are sequentially connected in series between the correction output end and the correction control end.

In one possible embodiment, the integrating circuit includes: a first functional module, a second functional module and a third functional module;

The first functional module is used for generating a first trigger voltage signal corresponding to a first trigger signal output by the pulse width generation circuit; the second functional module is used for generating a second trigger voltage signal corresponding to the second trigger signal output by the pulse width generating circuit; the third functional module is used for providing a reference potential point for the first trigger voltage signal and the second trigger voltage signal.

In a possible embodiment, the first functional module includes a first branch, the second functional module includes a second branch, and the third functional module includes a third branch;

the first branch, the second branch and the third branch are connected in parallel between a working voltage end and a common ground end of the memory chip;

the first branch circuit comprises a first PMOS tube and a first NMOS tube which are connected in series; the first control end of the memory chip is connected with the grid electrode of the first PMOS tube, and the first output end of the pulse width generating circuit is connected with the grid electrode of the first NMOS tube;

the second branch circuit comprises a second PMOS tube and a second NMOS tube which are connected in series; the second control end of the memory chip is connected with the grid electrode of the second PMOS tube, and the second output end of the pulse width generating circuit is connected with the grid electrode of the second NMOS tube;

The third branch circuit comprises a third PMOS tube and a third NMOS tube which are connected in series; the common grounding end is connected with the grid electrode of the third PMOS tube, and the third output end of the pulse width generating circuit is connected with the grid electrode of the third NMOS tube;

the first voltage output end of the integrating circuit is connected between the drain electrode of the first PMOS tube and the source electrode of the first NMOS tube; the first voltage output end is also connected with the common ground end through a first capacitor;

the second voltage output end of the integrating circuit is connected between the drain electrode of the second PMOS tube and the source electrode of the second NMOS tube; the second voltage output end is also connected with the common ground end through a second capacitor.

In a possible embodiment, the integrating circuit further comprises: a fourth NMOS tube;

the source electrode of the fourth NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube;

the drain electrode of the fourth NMOS tube is connected with the common ground terminal;

and the source electrode of the fourth NMOS tube is connected with the third control end of the memory chip.

In one possible embodiment, the original four-phase clock signal comprises: a 0-phase clock signal, a 90-phase clock signal, a 180-phase clock signal and a 270-phase clock signal output by the frequency divider;

The correcting the four-phase clock signal includes: a 0 phase correction clock signal, a 90 phase correction clock signal, a 180 phase correction clock signal, and a 270 phase correction clock signal;

the clock delay correction control signal includes: a 90 phase clock correction control signal, a 180 phase clock correction control signal, and a 270 phase clock correction control signal.

In a second aspect, an embodiment of the present invention provides a correction control method based on the circuit for correcting a clock duty cycle according to any one of the first aspect, wherein the method includes:

step 11, a circuit for controlling the duty ratio of the correction clock adjusts the delay of the 180-phase correction clock signal and performs 180-phase PLL loop locking operation;

step 12, the circuit for controlling the duty ratio of the correction clock adjusts the delay of the 90-phase correction clock signal and performs 90-phase PLL loop locking operation;

step 13, the circuit controlling the duty cycle of the correction clock adjusts 270 the delay of the phase correction clock signal and performs 270 the phase PLL loop locking operation.

In a possible embodiment, the step 11 includes:

step 21, activating a pulse width generating circuit to enable the pulse width generating circuit to generate a first rising edge trigger signal and a second rising edge trigger signal based on a 0-phase clock correction control signal and a 180-phase correction clock signal;

Step 22, controlling an integrating circuit to generate a first trigger voltage corresponding to the first rising edge trigger signal and a second trigger voltage of the second rising edge trigger signal, so that a comparator circuit generates a first comparison result of the first trigger voltage and the second trigger voltage, and a state machine circuit generates a corresponding 180-phase clock correction control signal based on the first comparison result, controls a clock delay correction circuit to adjust delay of the 180-phase correction clock signal and updates the 180-phase correction clock signal;

step 23, judging whether the 180-phase correction clock signal meets 180-phase PLL loop locking criteria;

step 24, if the 180-phase PLL loop locking criterion is not met, returning to step 21; and if the 180-phase PLL loop locking criterion is met, performing the 180-phase PLL loop locking operation.

In a possible embodiment, the step 12 includes:

step 31, activating a pulse width generating circuit to enable the pulse width generating circuit to generate a third rising edge trigger signal and a fourth rising edge trigger signal based on a 0-phase clock correction control signal, a 180-phase correction clock signal and a 90-phase correction clock signal;

Step 32, controlling an integrating circuit to generate a third trigger voltage corresponding to the third rising edge trigger signal and a fourth trigger voltage of the fourth rising edge trigger signal, so that a comparator circuit generates a second comparison result of the third trigger voltage and the fourth trigger voltage, and a state machine circuit generates a corresponding 90-phase clock correction control signal based on the second comparison result, controls a clock delay correction circuit to adjust delay of the 90-phase correction clock signal and updates the 90-phase correction clock signal;

step 33, judging whether the 90-phase correction clock signal meets a 90-phase PLL loop locking criterion;

step 34, if the 90-phase PLL loop locking criterion is not met, returning to step 31; and if the 90-phase PLL loop locking criterion is met, performing the 90-phase PLL loop locking operation.

In a possible embodiment, the step 13 includes:

step 41, activating a pulse width generating circuit to enable the pulse width generating circuit to generate a fifth rising edge trigger signal and a sixth rising edge trigger signal based on a 0-phase clock correction control signal, a 180-phase correction clock signal and a 270-phase correction clock signal;

Step 42, controlling an integrating circuit to generate a fifth trigger voltage corresponding to the fifth rising edge trigger signal and a sixth trigger voltage of the sixth rising edge trigger signal, so that a comparator circuit generates a third comparison result of the fifth trigger voltage and the sixth trigger voltage, and a state machine circuit generates a corresponding 270-phase clock correction control signal based on the third comparison result, controls a clock delay correction circuit to adjust delay of the 270-phase correction clock signal, and updates the 270-phase correction clock signal;

step 43, judging whether the 270 phase correction clock signal meets 270 phase PLL loop locking criteria;

step 44, if the 270 phase PLL loop locking criterion is not met, returning to step 41; and if the 270-phase PLL loop locking criterion is met, performing the 270-phase PLL loop locking operation.

In a third aspect, an embodiment of the present invention provides a correction control apparatus based on the circuit for correcting a clock duty cycle according to any one of the first aspect, wherein the apparatus includes:

a first control module for controlling a circuit for correcting a duty cycle of a clock to adjust a delay of a 180-phase correction clock signal and performing a 180-phase PLL loop locking operation;

The second control module is used for controlling the circuit of the corrected clock duty cycle to adjust the delay of the 90-phase corrected clock signal and performing 90-phase PLL loop locking operation;

and a third control module for controlling the circuit of the corrected clock duty cycle to adjust 270 the delay of the phase corrected clock signal and to perform 270 the phase PLL loop locking operation.

In one possible embodiment, the first control module includes:

the first activating module is used for activating the pulse width generating circuit to enable the pulse width generating circuit to generate a first rising edge trigger signal and a second rising edge trigger signal based on the 0-phase clock correction control signal and the 180-phase correction clock signal;

a fourth control module, configured to control an integrating circuit to generate a first trigger voltage corresponding to the first rising edge trigger signal and a second trigger voltage corresponding to the second rising edge trigger signal, so that a comparator circuit generates a first comparison result of the first trigger voltage and the second trigger voltage, and the state machine circuit generates a corresponding 180-phase clock correction control signal based on the first comparison result, controls a clock delay correction circuit to adjust delay of the 180-phase correction clock signal, and updates the 180-phase correction clock signal;

A first judging module, configured to judge whether the 180-phase correction clock signal meets a 180-phase PLL loop locking criterion;

the first loop locking module is used for returning to the first activating module to be re-executed when the 180-phase PLL loop locking criterion is not met; and the method is also used for carrying out the 180-phase PLL loop locking operation when the 180-phase PLL loop locking criterion is met.

In one possible embodiment, the second control module includes:

a second activation module for activating the pulse width generation circuit to cause the pulse width generation circuit to generate a third rising edge trigger signal and a fourth rising edge trigger signal based on the 0-phase clock correction control signal, the 180-phase correction clock signal, and the 90-phase correction clock signal;

a fifth control module, configured to control an integrating circuit to generate a third trigger voltage corresponding to the third rising edge trigger signal and a fourth trigger voltage corresponding to the fourth rising edge trigger signal, so that a comparator circuit generates a second comparison result of the third trigger voltage and the fourth trigger voltage, and the state machine circuit generates a corresponding 90-phase clock correction control signal based on the second comparison result, controls a clock delay correction circuit to adjust delay of the 90-phase correction clock signal, and updates the 90-phase correction clock signal;

The second judging module is used for judging whether the 90-phase correction clock signal meets the 90-phase PLL loop locking criterion;

the second loop locking module is used for returning to the second activating module to be re-executed when the 90-phase PLL loop locking criterion is not met; and the device is also used for carrying out the 90-phase PLL loop locking operation when the 90-phase PLL loop locking criterion is met.

In one possible embodiment, the third control module includes:

a third activation module for activating the pulse width generation circuit to cause the pulse width generation circuit to generate a fifth rising edge trigger signal and a sixth rising edge trigger signal based on the 0-phase clock correction control signal, the 180-phase correction clock signal, and the 270-phase correction clock signal;

a sixth control module, configured to control the integrating circuit to generate a fifth trigger voltage corresponding to the fifth rising edge trigger signal and a sixth trigger voltage of the sixth rising edge trigger signal, so that the comparator circuit generates a third comparison result of the fifth trigger voltage and the sixth trigger voltage, and the state machine circuit generates a corresponding 270-phase clock correction control signal based on the third comparison result, controls the clock delay correction circuit to adjust delay of the 270-phase correction clock signal, and updates the 270-phase correction clock signal;

A sixth judging module, configured to judge whether the 270 phase correction clock signal meets a 270 phase PLL loop locking criterion;

a third loop locking module, configured to return to the third activation module for re-execution when the 270-phase PLL loop locking criterion is not met; and the method is also used for carrying out the 270-phase PLL loop locking operation when the 270-phase PLL loop locking criterion is met.

In a fourth aspect, an embodiment of the present invention provides a memory chip, including: a circuit for correcting clock duty cycle as claimed in any one of the first aspects.

In a fifth aspect, an embodiment of the present invention provides a computer system comprising a memory chip, the memory chip performing the steps of the method of any of the second aspects.

Compared with the prior art, the invention has the following advantages and beneficial effects:

the invention connects in series between the correction output end and the correction control end of the clock delay correction circuit, the pulse width generation circuit, the integration circuit, the comparator circuit and the state machine circuit, uses the two paths of rising edge trigger signals corresponding to the correction four-phase clock signals output by the pulse width generation circuit, then uses the integration circuit to output two paths of voltage signals corresponding to the two paths of rising edge trigger signals, then compares the voltage of the two paths of voltage signals by the comparator circuit, inputs the state quantity to the state machine circuit, and finally outputs the corresponding correction control signals by the state machine circuit to control the clock delay correction circuit to correct the original four-phase clock signals.

When the phase difference between the original four-phase clock signals is not standard 90 degrees, pulse widths of two paths of rising edge trigger signals generated according to a certain correction four-phase clock signal are not equal, so that trigger time of two paths of voltage signals triggered by the two paths of rising edge trigger signals as on-off control signals in one clock period is different, voltage detection values of the two paths of voltage signals detected by the comparator circuit are different, phase offset state quantity of the certain correction four-phase clock signal is detected, and a state machine circuit is enabled to output a corresponding correction control signal to control a clock delay correction circuit to carry out delay control on the original four-phase clock signal according to the state quantity, and therefore rapid and accurate clock duty ratio correction of a high-speed clock is achieved.

Drawings

In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present description, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of clock control logic for eye diagram data of a conventional memory chip;

FIG. 2 is a schematic diagram of a circuit for correcting clock duty cycle according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a clock delay correction circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of connection of an integrating circuit according to an embodiment of the present invention;

FIG. 5 is a flowchart of a correction control method according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a 180-phase correction clock provided by an embodiment of the present invention;

FIG. 7 is a schematic diagram of a 90 phase correction clock provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of a 270 phase correction clock provided by an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a calibration control device according to an embodiment of the present invention.

Reference numerals illustrate: 1 is a clock delay correction circuit, 2 is a pulse width generation circuit, 3 is an integration circuit, 4 is a comparator circuit, 5 is a state machine circuit, pa is a first PMOS tube, pb is a second PMOS tube, pc is a third PMOS tube, na is a first NMOS tube, nb is a second NMOS tube, nc is a third NMOS tube, cb is a first capacitor, ca is a second capacitor.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the embodiments of the present invention.

Referring to fig. 2, fig. 2 is a schematic connection diagram of a circuit for correcting clock duty ratio according to an embodiment of the invention, the circuit includes: a clock delay correction circuit 1, a pulse width generation circuit 2, an integration circuit 3, a comparator circuit 4, and a state machine circuit 5.

Fig. 3 is a schematic connection diagram of a clock delay correction circuit according to the present embodiment, where the clock delay circuit is provided with four branches: the first high-speed clock path of the 0-phase clock signal (clk000_i) is provided with a capacitor structure consisting of an NMOS tube and a PMOS tube, and the capacitor structures can correct and control the delay time of the 0-phase clock signal (clk000_i) and output a standard 0-phase correction clock signal (clk000_o) under the control of a working voltage end (vdd) and a common ground end (vss) of a memory chip, and the delay time of the other three-way phase clock signal is adjusted by taking the 0-phase correction clock signal (clk000_o) as a standard instead of adjusting the delay time of the 0-phase correction clock signal (clk000_o); the second high-speed clock path of the 90-phase clock signal (clk 090_i) is provided with a capacitor structure composed of an NMOS tube and a PMOS tube, and the delay time of the 90-phase clock signal (clk 090_i) is regulated under the control of the 90-phase clock correction control signals (cnt_090_n <4>, cnt_090<4>, cnt_090_n <3>, cnt_090_3 >, cnt_090_n <2>, cnt_090<2>, cnt_090_n <1>, cnt_090<1>, cnt_090_n <0> and cnt_0900) given by the state machine circuit 5, and the 90-phase clock correction signal (clk 090_o) is output, and the 90-phase clock correction signal (clk 090_o) is ideally phase-different from the 0-phase clock signal (000_o) by 90 degrees. The third high-speed clock path of 180-phase clock signals (clk180_i) is provided with a capacitor structure composed of NMOS tubes and PMOS tubes, and the delay time of the 180-phase clock signals (clk180_i) is regulated under the control of 90-phase clock correction control signals (clk180_n <4>, cnt_180<4>, cnt_180_n <3>, cnt_180<3>, cnt_180_n <2>, cnt_180<2>, cnt_180_n <1>, cnt_180<1>, cnt_180_n <0> and cnt_180<0 >) given by a state machine circuit 5, and 180-phase correction clock signals (clk180_o) are output, and the 180-phase correction clock signals (clk180_o) are 180 DEG out of phase with 0-phase correction clock signals (clk000_o) in ideal conditions. The fourth high-speed clock path of 270 phase clock signals (clk180_i) is provided with a capacitor structure composed of NMOS tubes and PMOS tubes, and the delay time of 270 phase clock signals (clk180_i) is regulated under the control of 90 phase clock correction control signals (clk270_n <4>, cnt_270<4>, cnt_270_n <3>, cnt_270<3>, cnt_270_n <2>, cnt_270<2>, cnt_270_n <1>, cnt_270<1>, cnt_270_n <0> and cnt_270<0 >) given by the state machine circuit 5, 270 phase correction clock signals (clk270_o) are output, and the 270 phase correction clock signals (clk270_o) are ideally phase-shifted from 0 phase correction clock signals (clk000_o) by 270 °.

The correction input end of the clock delay correction circuit 1 comprises the input ends of the four branches, the correction output end of the clock delay correction circuit comprises the output ends of the four branches, and the correction control end of the clock delay correction circuit comprises the grid electrodes of NMOS (N-channel metal oxide semiconductor) tubes and PMOS (P-channel metal oxide semiconductor) tubes in the capacitor structures of the four branches.

Specifically, the original four-phase clock signal includes: the 0-phase clock signal (clk000_i), the 90-phase clock signal (clk090_i), the 180-phase clock signal (clk180_i), and the 270-phase clock signal (clk180_i) output by the frequency divider; correcting the four-phase clock signal includes: a 0 phase correction clock signal (clk000_o), a 90 phase correction clock signal (clk 090_o), a 180 phase correction clock signal (clk180_o), and a 270 phase correction clock signal (clk270_o); the clock delay correction control signal includes: a 90 phase clock correction control signal, a 180 phase clock correction control signal, and a 270 phase clock correction control signal.

The pulse width generation circuit 2 can generate a pulse control signal having a fixed clock period by using any two signals of the four-phase clock signal as a trigger signal and using the rising edge of the trigger signal.

The integration circuit 3 is provided with a capacitor, and the integration circuit 3 uses the pulse control signal generated by the pulse width generation circuit 2 as an on-off control signal of a transistor to control on-off of a capacitor discharging process, thereby generating a voltage signal with the pulse control signal.

The comparator circuit 4 can compare the magnitudes of the two voltage signals input from the integrating circuit 3 and send the comparison result in a state quantity manner.

The state quantity may be encoded using a two-level system, for example, 01 for a first voltage signal greater than a second voltage signal, 10 for a first voltage signal less than the second voltage signal, and 00 for a first voltage signal equal to the second voltage signal.

The state machine circuit 5 belongs to a finite state machine (Finite State Machine, FSM) and is a hardware sequential circuit composed of a register set and combinational logic. The combination of 1 and 0 stored in the register set can constitute a limited number of states, one of which can only be shifted to the other in case of a same clock transition. In this embodiment, a corresponding clock delay correction control signal is set for the input state in the state machine circuit 5 in advance, and when a state quantity is input, the state machine circuit 5 outputs the corresponding clock delay correction control signal to control the original four-phase clock signal input into the clock delay correction circuit 1 to delay (or advance) a set time in a set direction.

The working principle of the embodiment is as follows:

in the pulse width generating circuit 2, the rising edge of the 0-phase clock correction control signal and the rising edge of the 180-phase clock correction control signal trigger the first rising edge trigger signal (pul_000_180), and the rising edge of the 180-phase clock correction control signal and the rising edge of the 0-phase clock correction control signal trigger the second rising edge trigger signal (pul_180_000); the third rising edge trigger signal (pul_000_090) may be triggered by the rising edge of the 0 phase clock correction control signal and the rising edge of the 90 phase clock correction control signal, and the fourth rising edge trigger signal (pul_090_180) may be triggered by the rising edge of the 90 phase clock correction control signal and the rising edge of the 180 phase clock correction control signal; the fifth rising edge trigger signal (pul_180_270) may be triggered by the 180 phase clock correction control signal rising edge and the 270 phase clock correction control signal rising edge, and the sixth rising edge trigger signal (pul_270_000) may be triggered by the 270 phase clock correction control signal rising edge and the 0 phase clock correction control signal rising edge.

In the case where the phase difference between the original four-phase clock signals is 90 ° as standard, the phase difference between the corrected four-phase clock signals directly output from the clock delay correction circuit 1 is also 90 ° as standard, and at this time, the pulse width of the first rising edge trigger signal (pul_000_180) is equal to the pulse width of the second rising edge trigger signal (pul_180_000), the pulse width of the third rising edge trigger signal (pul_000_090) is equal to the pulse width of the fourth rising edge trigger signal (pul_090_180), and the pulse width of the fifth rising edge trigger signal (pul_180_270) is equal to the pulse width of the sixth rising edge trigger signal (pul_270_000).

When the phase difference between the corrected four-phase clock signals directly output by the clock delay correction circuit 1 is not the standard 90 °, the memory chip can complete the phase correction of the 180-phase clock correction control signal relative to the 0-phase clock correction control signal by adjusting the pulse width of the first rising edge trigger signal (pul_000_180) and the pulse width of the second rising edge trigger signal (pul_180_000) to be equal by the clock delay correction circuit 1; phase correction of the 90-phase clock correction control signal with respect to the 0-phase clock correction control signal is accomplished by adjusting the pulse width of the third rising edge trigger signal (pul_000_090) to be equal to the pulse width of the fourth rising edge trigger signal (pul_090_180); the phase correction of the 270-phase clock correction control signal with respect to the 0-phase clock correction control signal is accomplished by adjusting the pulse width of the fifth rising edge trigger signal (pul_180_270) to be equal to the pulse width of the sixth rising edge trigger signal (pul_270_000).

The embodiment adopts a voltage comparison scheme to realize specific judgment of whether pulse widths of all groups of rising edge trigger signals are equal. The entire judgment process will be described here by taking 180-phase clock correction control signal phase correction as an example. In this embodiment, the first rising edge trigger signal (pul_000_180) and the second rising edge trigger signal (pul_180_000) are used as transistor on-off control signals, and the on-off control is performed on the capacitor discharging process in the integrating circuit 3, so that the triggering duration of the first rising edge trigger signal (pul_000_180) in one clock cycle of the first trigger voltage output by the integrating circuit 3 is equal to the pulse width of the first rising edge trigger signal (pul_000_180), and the triggering duration of the second rising edge trigger signal (pul_180_000) in one clock cycle of the second trigger voltage is equal to the pulse width of the second rising edge trigger signal (pul_180_000), and thus, according to the comparison result of the magnitudes of the first trigger voltage and the second trigger voltage by the comparator circuit 4, whether the pulse width of the first rising edge trigger signal (pul_000_180) is equal to the pulse width of the second rising edge trigger signal (pul_180_000) can be known.

After that, the comparator circuit 4 sends the comparison result to the state machine circuit 5 in the manner of 1 (up) and 0 (down), and finally the state machine circuit 5 generates a correction control signal according to the comparison result, delays (or advances) the 180-phase clock signal (clk180_i) input into the clock delay correction circuit 1 in the set direction by a set time, outputs a new 180-phase correction clock signal (clk180_o), and then repeats the above adjustment process until the comparator circuit 4 judges that the magnitudes of the first trigger voltage and the second trigger voltage are equal, that is, the pulse width of the first rising edge trigger signal (pul_000_180) is equal to the pulse width of the second rising edge trigger signal (pul_180_000), at which time the 180-phase PLL loop locking operation can be performed.

After the correction of the 180-phase clock signal (clk180_i) is completed, the correction of the 0-phase clock signal (clk000_i) and the 90-phase clock signal (clk090_i) is completed in the same manner.

In this embodiment, the clock delay correction circuit 1, the pulse width generation circuit 2, the integration circuit 3, the comparator circuit 4 and the state machine circuit 5 are skillfully arranged, and whether phase deviation still exists between the original four-phase clock signals is judged through the comparison result of the trigger voltage generated by the integration circuit 3, so that the phase correction of the original four-phase clock signals is rapidly and accurately completed.

The integrating circuit 3 specifically includes a first functional module, a second functional module, and a third functional module; the first functional module is used for generating a first trigger voltage signal corresponding to the first trigger signal output by the pulse width generating circuit; the second functional module is used for generating a second trigger voltage signal corresponding to the second trigger signal output by the pulse width generating circuit; the third functional module is used for providing a reference potential point for the first trigger voltage signal and the second trigger voltage signal.

The first trigger signal may be a first rising edge trigger signal (pul_000_180), a third rising edge trigger signal (pul_000_090), or a fifth rising edge trigger signal (pul_180_270) output from the pulse width generating circuit; the first trigger voltage signal may be a first trigger voltage corresponding to the first rising edge trigger signal (pul_000_180), a third trigger voltage corresponding to the third rising edge trigger signal (pul_000_090), or a fifth trigger voltage corresponding to the fifth rising edge trigger signal (pul_180_270).

The second trigger signal may be a second rising edge trigger signal (pul_180_000), a fourth rising edge trigger signal (pul_090_180), or a sixth rising edge trigger signal (pul_270_000) output from the pulse width generating circuit; the second trigger voltage signal may be a second trigger voltage corresponding to the second rising edge trigger signal (pul_180_000), a fourth trigger voltage corresponding to the fourth rising edge trigger signal (pul_090_180), or a sixth trigger voltage corresponding to the sixth rising edge trigger signal (pul_270_000).

Here, the present invention further provides an integrating circuit 3, as shown in fig. 4, which is a connection schematic diagram of the circuit, specifically, the first functional module includes a first branch, the second functional module includes a second branch, the third functional module includes a third branch, and the first branch, the second branch and the third branch are connected in parallel between a working voltage terminal (VDD) and a common ground terminal (VSS) of the memory chip; the first branch circuit comprises a first PMOS tube (pa) and a first NMOS tube (na) which are connected in series; the first control end of the memory chip is connected with the grid electrode of the first PMOS tube (pa), and the first output end of the pulse width generating circuit 2 is connected with the grid electrode of the first NMOS tube (na); the second branch comprises a second PMOS tube (pb) and a second NMOS tube (nb) which are connected in series; the second control end of the memory chip is connected with the grid electrode of the second PMOS tube (pb), and the second output end of the pulse width generating circuit 2 is connected with the grid electrode of the second NMOS tube (nb); the third branch circuit comprises a third PMOS tube (pc) and a third NMOS tube (nc) which are connected in series; the common ground end (VSS) is connected with the grid electrode of the third PMOS tube (pc), and the third output end of the pulse width generating circuit 2 is connected with the grid electrode of the third NMOS tube (nc); the first voltage output end of the integrating circuit is connected between the drain electrode of the first PMOS tube (pa) and the source electrode of the first NMOS tube (na); the first voltage output end is also connected with a common ground end (VSS) through a first capacitor; the second voltage output end of the integrating circuit is connected between the drain electrode of the second PMOS tube (pb) and the source electrode of the second NMOS tube (nb); the second voltage output terminal is also connected to a common ground terminal (VSS) through a second capacitor.

Wherein clk_r and clk_f represent different trigger signals according to different clock signals of current correction. In the correction of the 180-phase clock signal (clk180_i), clk_r is the first rising edge trigger signal (pul_000_180), and clk_f is the second rising edge trigger signal (pul_180_000); in the correction of the 90-phase clock signal (clk 090_i), clk_r is the third rising edge trigger signal (pul_000_090), and clk_f is the fourth rising edge trigger signal (pul_090_180); in the correction of the 270-phase clock signal (clk180_i), clk_r is the fifth rising edge trigger signal (pul_180_270), and clk_f is the sixth rising edge trigger signal (pul_270_000).

The working principle of the integrating circuit 3 is as follows:

before the integrating circuit 3 starts to work, the memory chip firstly sets the pre_n signal to be low level, and the first PMOS tube (pa) and the second PMOS tube (pb) charge cp and cp_n to the working voltage VDD potential of the memory chip.

After the integrating circuit 3 starts to operate, the memory chip turns the pre_n signal to high level, and the first PMOS transistor (pa) and the second PMOS transistor (pb) are turned off. clk_r and clk_f discharge cp and cp_n with respective high levels.

And clk_d is a signal that precharges v_com in order to make the voltage at the v_com point the same when the first high level of clk_r and clk_f discharges cp and cp_n.

After the discharge of the plurality of high-level pairs cp and cp_n is completed, the switch comp_n of the comparator circuit 4 is changed from the low level to the high level, and the comparator circuit 4 starts to compare the potentials of cp and cp_n.

After the comparison by the comparator circuit 4 is completed, both of the pre_n and comp_n become low, and the comparison of clk_r and clk_f at high level is completed once.

In this embodiment, a fourth NMOS transistor is further disposed in the integrating circuit 3, and a source electrode of the fourth NMOS transistor is connected to a drain electrode of the first NMOS transistor (na), a drain electrode of the second NMOS transistor (nb), and a drain electrode of the third NMOS transistor (nc), respectively; the drain electrode of the fourth NMOS tube is connected with a common ground terminal (VSS); and the source electrode of the fourth NMOS tube is connected with the third control end of the memory chip. So that the memory chip issues an en signal via the third control terminal to control the potential of v_com.

Referring to fig. 5, fig. 5 is a flowchart of a correction control method according to an embodiment of the present invention, where the method embodiment is applied to any one of the above circuits for correcting clock duty ratio, and specifically includes steps 11 to 13.

Step 11, the circuit controlling the correction clock duty cycle adjusts the delay of 180 phase correction clock signal (clk180_o) and performs 180 phase PLL loop locking operation.

Fig. 6 shows a schematic diagram of a 180-phase correction clock according to the present embodiment, which specifically includes:

In step 21, the pulse width generation circuit 2 is activated such that the pulse width generation circuit 2 generates a first rising edge trigger signal (pul_000_180) and a second rising edge trigger signal (pul_180_000) based on the 0-phase clock correction control signal and the 180-phase correction clock signal (clk180_o).

In step 22, the integrating circuit 3 is controlled to generate a first trigger voltage corresponding to the first rising edge trigger signal (pul_000_180) and a second trigger voltage corresponding to the second rising edge trigger signal (pul_180_000), so that the comparator circuit 4 generates a first comparison result of the first trigger voltage and the second trigger voltage, the state machine circuit 5 generates a corresponding 180-phase clock correction control signal based on the first comparison result, and the clock delay correction circuit 1 is controlled to adjust the delay of the 180-phase correction clock signal (clk180_o) and update the 180-phase correction clock signal (clk180_o).

Step 23, determining whether the 180-phase correction clock signal (clk180_o) meets a 180-phase PLL loop locking criterion.

Specifically, the 180-phase PLL loop locking criterion includes that the pulse widths of the first rising edge trigger signal (pul_000_180) and the second rising edge trigger signal (pul_180_000) are equal.

In step 12, the circuit controlling the corrected clock duty cycle adjusts the delay of the 90-phase corrected clock signal (clk 090_o) and performs the 90-phase PLL loop locking operation.

Fig. 7 shows a schematic diagram of a 90-phase correction clock according to the present embodiment, which specifically includes:

in step 31, the pulse width generation circuit 2 is activated such that the pulse width generation circuit 2 generates a third rising edge trigger signal (pul_000_090) and a fourth rising edge trigger signal (pul_090_180) based on the 0 phase clock correction control signal, the 180 phase correction clock signal (clk180_o), and the 90 phase correction clock signal (clk 090_o).

Step 32, controlling the integrating circuit 3 to generate a third trigger voltage corresponding to the third rising edge trigger signal (pul_000_090) and a fourth trigger voltage of the fourth rising edge trigger signal (pul_090_180), so that the comparator circuit 4 generates a second comparison result of the third trigger voltage and the fourth trigger voltage, the state machine circuit 5 generating a corresponding 90-phase clock correction control signal based on the second comparison result, controlling the clock delay correction circuit 1 to adjust the delay of the 90-phase correction clock signal (clk 090_o), and updating the 90-phase correction clock signal (clk 090_o);

Step 33, determining whether the 90 phase correction clock signal (clk 090_o) meets a 90 phase PLL loop locking criterion.

Specifically, the 90-phase PLL loop locking criterion includes that the pulse widths of the third rising edge trigger signal (pul_000_090) and the fourth rising edge trigger signal (pul_090_180) are equal.

Step 13, the circuit controlling the corrected clock duty cycle adjusts 270 the delay of the phase corrected clock signal (clk 270_o) and performs 270 phase PLL loop locking operations.

Fig. 8 shows a schematic diagram of a 90-phase correction clock according to the present embodiment, which specifically includes:

in step 41, the pulse width generation circuit 2 is activated such that the pulse width generation circuit 2 generates a fifth rising edge trigger signal (pul_180_270) and a sixth rising edge trigger signal (pul_270_000) based on the 0-phase clock correction control signal, the 180-phase correction clock signal (clk180_o), and the 270-phase correction clock signal (clk270_o).

In step 42, the integrating circuit 3 is controlled to generate a fifth trigger voltage corresponding to the fifth rising edge trigger signal (pul_180_270) and a sixth trigger voltage corresponding to the sixth rising edge trigger signal (pul_270_000), so that the comparator circuit 4 generates a third comparison result of the fifth trigger voltage and the sixth trigger voltage, the state machine circuit 5 generates a corresponding 270-phase clock correction control signal based on the third comparison result, and the clock delay correction circuit 1 is controlled to adjust the delay of the 270-phase correction clock signal (clk 270_o) and update the 270-phase correction clock signal (clk 270_o).

Step 43, determining whether said 270 phase corrected clock signal (clk 270_o) meets 270 phase PLL loop locking criteria.

Since the working principle of the embodiment of the method is similar to that of the circuit, the description is omitted here.

Based on the same inventive concept as the method, the embodiment of the present invention further provides a correction control device, as shown in fig. 9, which is a schematic structural diagram of an embodiment of the device, where the embodiment of the device is applied to any one of the circuits for correcting the clock duty cycle, and the device includes:

a first control module 51 for controlling a circuit for correcting a clock duty ratio to adjust a delay of a 180-phase correction clock signal (clk180_o) and perform a 180-phase PLL loop locking operation;

a second control module 52 for controlling the circuit of the correction clock duty cycle to adjust the delay of the 90 phase correction clock signal (clk 090_o) and to perform a 90 phase PLL loop locking operation;

The third control module 53 is configured to control the circuit for correcting the clock duty cycle to adjust 270 the delay of the phase correction clock signal (clk 270_o) and perform 270 the phase PLL loop locking operation.

In one possible embodiment, the first control module includes:

a first activating module for activating the pulse width generating circuit 2 to cause the pulse width generating circuit 2 to generate a first rising edge trigger signal (pul_000_180) and a second rising edge trigger signal (pul_180_000) based on a 0-phase clock correction control signal and a 180-phase correction clock signal (clk180_o);

a fourth control module for controlling the integrating circuit 3 to generate a first trigger voltage corresponding to the first rising edge trigger signal (pul_000_180) and a second trigger voltage corresponding to the second rising edge trigger signal (pul_180_000) so that the comparator circuit 4 generates a first comparison result of the first trigger voltage and the second trigger voltage, the state machine circuit 5 generating a corresponding 180-phase clock correction control signal based on the first comparison result, and controlling the clock delay correction circuit 1 to adjust the delay of the 180-phase correction clock signal (clk180_o) and update the 180-phase correction clock signal (clk180_o);

A first judging module for judging whether the 180-phase correction clock signal (clk180_o) meets 180-phase PLL loop locking criteria;

In one possible embodiment, the second control module includes:

a second activating module for activating the pulse width generating circuit 2 to cause the pulse width generating circuit 2 to generate a third rising edge trigger signal (pul_000_090) and a fourth rising edge trigger signal (pul_090_180) based on the 0-phase clock correction control signal, the 180-phase correction clock signal (clk180_o), and the 90-phase correction clock signal (clk 090_o);

a fifth control module, configured to control the integrating circuit 3 to generate a third trigger voltage corresponding to the third rising edge trigger signal (pul_000_090) and a fourth trigger voltage corresponding to the fourth rising edge trigger signal (pul_090_180), so that the comparator circuit 4 generates a second comparison result of the third trigger voltage and the fourth trigger voltage, and the state machine circuit 5 generates a corresponding 90-phase clock correction control signal based on the second comparison result, and controls the clock delay correction circuit 1 to adjust a delay of the 90-phase correction clock signal (clk 090_o) and update the 90-phase correction clock signal (clk 090_o);

A second judging module, configured to judge whether the 90-phase correction clock signal (clk 090_o) meets a 90-phase PLL loop locking criterion;

In one possible embodiment, the third control module includes:

a third activating module for activating the pulse width generating circuit 2 to cause the pulse width generating circuit 2 to generate a fifth rising edge trigger signal (pul_180_270) and a sixth rising edge trigger signal (pul_270_000) based on the 0-phase clock correction control signal, the 180-phase correction clock signal (clk180_o), and the 270-phase correction clock signal (clk270_o);

a sixth control module, configured to control the integrating circuit 3 to generate a fifth trigger voltage corresponding to the fifth rising edge trigger signal (pul_180_270) and a sixth trigger voltage corresponding to the sixth rising edge trigger signal (pul_270_000), so that the comparator circuit 4 generates a third comparison result of the fifth trigger voltage and the sixth trigger voltage, and the state machine circuit 5 generates a corresponding 270 phase clock correction control signal based on the third comparison result, and controls the clock delay correction circuit 1 to adjust a delay of the 270 phase correction clock signal (clk 270_o) and update the 270 phase correction clock signal (clk 270_o);

A sixth determining module, configured to determine whether the 270 phase correction clock signal (clk 270_o) meets a 270 phase PLL loop locking criterion;

Based on the same inventive concept as in the previous embodiments, embodiments of the present invention also provide a memory chip including any of the above circuits for correcting a clock duty cycle.

Based on the same inventive concept as in the previous embodiments, embodiments of the present invention also provide a computer system including a memory chip that performs the steps of any of the methods described above.

The technical scheme provided by the embodiment of the invention has at least the following technical effects or advantages:

the embodiment of the invention is characterized in that a pulse width generating circuit, an integrating circuit, a comparator circuit and a state machine circuit are connected in series between a correction output end and a correction control end of a clock delay correction circuit, two paths of rising edge trigger signals corresponding to correction four-phase clock signals output by the pulse width generating circuit are utilized, then two paths of voltage signals corresponding to the two paths of rising edge trigger signals are output by the integrating circuit, then the voltage of the two paths of voltage signals is compared by the comparator circuit, state quantity is input to the state machine circuit, and finally the state machine circuit outputs corresponding correction control signals to control the clock delay correction circuit to correct the original four-phase clock signals.

When the phase difference between the original four-phase clock signals is not standard 90 degrees, pulse widths of two paths of rising edge trigger signals generated according to a certain correction four-phase clock signal are not equal, so that trigger time of two paths of voltage signals triggered by the two paths of rising edge trigger signals as on-off control signals in one clock period is different, voltage detection values of the two paths of voltage signals detected by the comparator circuit are different, phase offset state quantity of the certain correction four-phase clock signal is detected, and a state machine circuit is enabled to output a corresponding correction control signal to control a clock delay correction circuit to carry out delay control on the original four-phase clock signal according to the state quantity, and therefore rapid and accurate clock duty ratio correction of a high-speed clock is achieved. It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (modules, systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

The present embodiment discloses: a1, a circuit for correcting a clock duty ratio, comprising: a clock delay correction circuit, a pulse width generation circuit, an integration circuit, a comparator circuit and a state machine circuit;

A2. the circuit for correcting a clock duty cycle according to claim A1, wherein the integrating circuit comprises: a first functional module, a second functional module and a third functional module;

A3. the circuit for correcting clock duty cycle according to claim A2, wherein the first functional module comprises a first branch, the second functional module comprises a second branch, and the third functional module comprises a third branch;

A4. the circuit for correcting a clock duty cycle according to claim A3, wherein the integrating circuit further comprises: a fourth NMOS tube;

A5. the circuit for correcting clock duty cycle according to claim A1, wherein the original four-phase clock signal comprises: a 0-phase clock signal, a 90-phase clock signal, a 180-phase clock signal and a 270-phase clock signal output by the frequency divider;

B1, a correction control method of a circuit based on the correction clock duty ratio according to any one of claims A1 to A5, characterized by comprising:

B2. the correction control method according to claim B1, characterized in that the step 11 includes:

step 22, controlling an integrating circuit to generate a first trigger voltage corresponding to the first rising edge trigger signal and a second trigger voltage of the second rising edge trigger signal, so that a comparator circuit generates a first comparison result of the first trigger voltage and the second trigger voltage, and a state machine circuit generates a corresponding 180-phase clock correction control signal based on the first comparison result, controls the clock delay correction circuit to adjust delay of the 180-phase correction clock signal and updates the 180-phase correction clock signal;

B3. the correction control method according to claim B1, characterized in that the step 12 includes:

B4. the correction control method according to claim B1, characterized in that the step 13 includes:

C1, a correction control apparatus based on a circuit for correcting a clock duty cycle according to any one of claims A1 to A5, characterized in that the apparatus comprises:

C2. the correction control apparatus according to claim C1, wherein the first control module includes:

C3. the correction control apparatus according to claim C1, wherein the second control module includes:

C4. the correction control apparatus according to claim C1, wherein the third control module includes:

D1, a memory chip, comprising: a circuit for correcting a clock duty ratio as claimed in any one of A1 to A5.

E1, a computer system comprising a memory chip, said memory chip performing the steps of the method of any of B1 to B4.

Claims

1. A circuit for correcting a clock duty cycle, comprising: a clock delay correction circuit, a pulse width generation circuit, an integration circuit, a comparator circuit and a state machine circuit;

the pulse width generation circuit, the integration circuit, the comparator circuit and the state machine circuit are sequentially connected in series between the correction output end and the correction control end; the pulse width generation circuit comprises an input end for inputting any two paths of signals in the correction four-phase clock signal as trigger signals and an output end for outputting pulse control signals with fixed clock cycles by utilizing rising edges of the trigger signals;

the integrating circuit comprises an input end for inputting the pulse control signal and an output end for outputting a voltage signal with the pulse control signal;

the comparator circuit includes an input terminal for inputting the voltage signal, and an output terminal for outputting a comparison result.

2. The circuit for correcting a clock duty cycle of claim 1, wherein the integrating circuit comprises: a first functional module, a second functional module and a third functional module;

3. The circuit for correcting a clock duty cycle of claim 2, wherein the first functional module comprises a first branch, the second functional module comprises a second branch, and the third functional module comprises a third branch;

4. A circuit for correcting a clock duty cycle as set forth in claim 3, wherein said integrating circuit further comprises: a fourth NMOS tube;

5. The circuit for correcting a clock duty cycle of claim 1, wherein the original four-phase clock signal comprises: a 0-phase clock signal, a 90-phase clock signal, a 180-phase clock signal and a 270-phase clock signal output by the frequency divider;

6. A correction control method based on the circuit of correcting a clock duty ratio according to any one of claims 1 to 5, characterized by comprising:

step 11, a circuit for controlling the duty ratio of the correction clock generates a first rising edge trigger signal and a second rising edge trigger signal by correcting the control signal based on the 0-phase clock and the 180-phase correction clock signal to adjust the delay of the 180-phase correction clock signal and perform 180-phase PLL loop locking operation;

Step 12, the circuit for controlling the duty ratio of the correction clock generates a third rising edge trigger signal and a fourth rising edge trigger signal by based on the 0 phase clock correction control signal, the 180 phase correction clock signal and the 90 phase correction clock signal to adjust the delay of the 90 phase correction clock signal and perform the 90 phase PLL loop locking operation;

in step 13, the circuit controlling the duty cycle of the correction clock generates a fifth rising edge trigger signal and a sixth rising edge trigger signal by based on the 0-phase clock correction control signal, the 180-phase correction clock signal, and the 270-phase correction clock signal to adjust the delay of the 270-phase correction clock signal and perform a 270-phase PLL loop locking operation.

7. The correction control method according to claim 6, characterized in that said step 11 includes:

8. The correction control method according to claim 6, characterized in that said step 12 includes:

9. The correction control method according to claim 6, characterized in that said step 13 includes:

10. A correction control apparatus based on a circuit for correcting a clock duty cycle according to any one of claims 1 to 5, characterized by comprising:

a first control module for controlling a circuit for correcting a duty ratio of a clock to generate a first rising edge trigger signal and a second rising edge trigger signal by correcting the control signal based on the 0-phase clock and the 180-phase correction clock signal to adjust a delay of the 180-phase correction clock signal and perform a 180-phase PLL loop locking operation;

a second control module for controlling the circuit of the corrected clock duty cycle to generate a third rising edge trigger signal and a fourth rising edge trigger signal by correcting the control signal based on the 0 phase clock, the 180 phase corrected clock and the 90 phase corrected clock signals to adjust the delay of the 90 phase corrected clock signal and perform a 90 phase PLL loop locking operation;

And a third control module for controlling the circuit of the corrected clock duty ratio to generate a fifth rising edge trigger signal and a sixth rising edge trigger signal by correcting the control signal based on the 0 phase clock, 180 phase correction clock and 270 phase correction clock signals to adjust the delay of the 270 phase correction clock signal and perform 270 phase PLL loop locking operation.

11. The correction control apparatus according to claim 10, wherein the first control module includes:

12. The correction control apparatus according to claim 10, characterized in that the second control module includes:

13. The correction control apparatus according to claim 10, characterized in that the third control module includes:

14. A memory chip, comprising: a circuit for correcting clock duty cycle as claimed in any one of claims 1 to 5.

15. A computer system comprising a memory chip, said memory chip performing the steps of the method of any of claims 6 to 9.