CN111600606A - A Multiphase Clock Generation Circuit for Time Interleaved Sampling ADC - Google Patents

Abstract

The invention relates to a multi-phase clock generation circuit for a time-interleaving sampling ADC, belonging to the technical field of clock generation and realizing low clock jitter, low time deviation and low power consumption on the premise of ensuring high speed. The circuit includes a ring voltage controlled oscillator, a phase tracking loop circuit and a calibration pulse generating circuit; the ring voltage controlled oscillator and the phase tracking loop circuit form a PLL loop; The clock signal of multiple phases is output under control; the calibration pulse generation circuit is connected with the ring voltage controlled oscillator, and is used to output the clock calibration signal to the ring voltage controlled oscillator, adjust the internal clock of the ring voltage controlled oscillator, and eliminate the clock jitter on the output. effect of the clock signal. The present invention generates a multi-phase clock with low jitter, low clock deviation and high precision, and has low power consumption and low hardware overhead.

Description

A Multiphase Clock Generation Circuit for Time Interleaved Sampling ADC

technical field

The invention relates to the technical field of clock generation, in particular to a multi-phase clock generation circuit for time-interleaving sampling ADC.

Background technique

Analog-to-Digital Converter (ADC) converts continuous time and amplitude signals to discrete time and quantized amplitude signals in digital processing systems. ADCs have been widely used in electronic systems such as voice and image processors, sonar radar processing systems, sensor networks, finite and infinite communication systems, biomedical systems, and test and measurement instruments. With the development of science and technology, the miniaturization, mobility, and wearability of electronic products have become the mainstream, and low power consumption has become an important indicator of electronic products. In addition, the continuous development of wireless communication systems and the rapid development of the Internet of Things have brought information explosion. The rapid growth has brought huge challenges to the processing speed and communication capability of the system. To sum up, the high-speed, high-precision, low-power ADC is usually the bottleneck of the overall system performance.

In recent years, multi-channel time-interleaving ADC has been the research focus of high-speed, high-precision and low-power consumption. Through the interleaving of multiple low-speed ADCs in the time domain, one high-speed ADC is synthesized, which breaks through the speed limitation of single-channel ADC under the same process. The accuracy and power consumption of the multi-channel time-interleaved ADC are also important indicators to measure the entire ADC. In terms of accuracy, it is mainly limited by the performance of the single-channel ADC, as well as the offset error, gain error, and time deviation caused by time interleaving. In terms of power consumption, it is mainly limited by the single-channel ADC, reference voltage drive circuit, high speed and high precision Multiphase clock generation circuit, etc. At present, a single-channel ADC can achieve good performance under low power consumption. The offset error, gain error, and time deviation caused by time interleaving can be solved by foreground or background calibration technology. The power consumption of the reference voltage driving circuit can be calibrated by DAC. There is no better solution for the multi-phase clock generation circuit of high speed, high precision and low power consumption at present. The currently known solutions are as follows:

First, as shown in Figure 1, the multi-phase clock is generated by dividing the frequency of the CML circuit through the external input high-frequency clock, and then the clock level is converted into the CMOS level through the CML-to-CMOS circuit, and then calibrated by the subsequent time offset adjustment circuit. , and finally a multiphase sampling clock is obtained. The obvious disadvantage of this scheme is that the performance of the high-speed clock input from the outside is relatively poor, and when the sampling clock frequency is high, the CML circuit needs a large current to achieve high-speed frequency division, which makes the power consumption of the clock circuit increase exponentially.

Second, as shown in Figure 2, a basic clock is generated by PLL, and then a multi-phase clock is delayed by multiple delay circuits, and then the clock level is converted into CMOS level by a CML-to-CMOS circuit, and finally after the subsequent time deviation The multi-phase sampling clock is obtained after adjusting the circuit calibration. The significant disadvantage of this scheme is that the high-speed clock will deteriorate the jitter of the clock through each delay circuit, thus limiting the accuracy of the ADC.

SUMMARY OF THE INVENTION

In view of the above analysis, the present invention aims to provide a multi-phase clock generation circuit for time-interleaved sampling ADC, which can achieve low clock jitter, low time deviation and low power consumption on the premise of ensuring high speed.

The invention discloses a multi-phase clock generation circuit for time interleaving sampling ADC, comprising a ring voltage controlled oscillator, a phase tracking loop circuit and a calibration pulse generation circuit;

The ring voltage-controlled oscillator and the phase tracking loop circuit form a PLL loop; the ring voltage-controlled oscillator outputs clock signals of multiple phases under the control of the first control voltage output by the phase tracking loop circuit; The clock signal is fed back to the phase tracking loop circuit for phase identification with the input reference clock signal, and the amplitude of the first control voltage is adjusted so that the frequency of the clock signals of multiple phases output by the ring voltage controlled oscillator is the same as that of the reference clock. the frequency is equal;

The calibration pulse generating circuit is connected with the ring voltage-controlled oscillator, and is used for outputting a clock calibration signal to the ring voltage-controlled oscillator, adjusting the internal clock of the ring voltage-controlled oscillator, and eliminating the influence of clock jitter on the output clock signal.

Further, the ring voltage controlled oscillator also adjusts the phase difference between the clock signals of multiple phases according to the input second control voltage.

Further, the ring voltage-controlled oscillator includes first, second, third and fourth delay units with the same structure connected in a ring, wherein the output terminals OP and ON of the fourth delay unit are respectively connected with the first delay unit. The input terminals IP and IN are connected; the output terminals OP and ON of the previous delay unit in the remaining sequentially connected delay units are respectively connected with the input terminals IN and IP of the next delay unit;

The phase difference between the signals at the input terminals IP and IN of each of the delay units is 180°, and the phase difference between the signals at the output terminals ON and OP is 180°; the phase difference between the signal at the output terminal OP and the signal at the input terminal IN is 45°, the phase difference between the signal at the output end ON and the signal at the input end IP is 45°.

Further, the delay unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first normally-on transmission gate, a second normally-on transmission gate, a first variable a capacitor bank and a second variable capacitor bank;

The output end of the first inverter is connected to the input end of the second inverter; the output end of the third inverter is connected to the input end of the fourth inverter; the input end of the first inverter is connected to the third inverter The first normally-on transmission gate is connected between the output terminals of the inverter; the second normally-on transmission gate is connected across the input terminal of the third inverter and the output terminal of the first inverter; the output terminal of the first inverter connecting the first variable capacitor bank and the second variable capacitor bank in parallel with the output end of the third inverter;

The input end of the first inverter is the input end IN of the delay unit, the input end of the third inverter is the input end IP of the delay unit; the output end of the second inverter is the output end OP of the delay unit, and the fourth The output terminal of the inverter is the output terminal of the delay unit ON;

The first variable capacitor group is a voltage-controlled capacitor group, the control terminal VC of which is connected to a control voltage, and the frequency of the output clock signal of the delay unit is controlled by controlling the capacitance of the first variable capacitor group;

The second variable capacitor group is a voltage-controlled capacitor group, the control terminal VT of which is connected to a control voltage, and the phase of the output clock signal from the delay unit is controlled by controlling the capacitance of the second variable capacitor group.

Further, the control terminal VC of each delay unit is connected to the first control voltage output by the phase tracking loop circuit, so that the frequency of the output clock signal of each delay unit is the same as the frequency of the reference clock signal;

The control terminals VT of the first, second, third and fourth delay units are respectively connected to the second control voltages VTS1 , VTS2 , VTS3 and VTS4 to adjust the phase of the clock signal output by each delay unit respectively.

Further, the ring voltage controlled oscillator also includes an NMOS tube, the source and drain of the NMOS tube are connected between the input terminals IN and IP of any delay unit, and the gate is connected to the calibration pulse generating circuit. output.

Further, the ring voltage controlled oscillator also includes four NMOS tubes, corresponding to the four delay units respectively, and the source and drain of each NMOS tube are connected across the input terminals IN and IP of the corresponding delay unit. The gate of any one of the four NMOS tubes is connected to the output end of the calibration pulse generating circuit, and the gates of the remaining three NMOS tubes are all grounded.

Further, the calibration pulse generation circuit is connected to the reference clock signal, and under the enable of the debounce enable signal, a clock calibration signal aligned with the rising edge of the reference clock signal is output to the gate of the NMOS transistor;

When the ring voltage controlled oscillator has clock jitter, the output potentials of the output terminals OP and ON of the delay unit connected by the NMOS tube are not equal, and the clock calibration pulse signal turns on the NMOS tube, and a current flows through the NMOS tube, making the output terminal The voltage difference between OP and ON is reduced to zero, and the zero-crossing point of the output clock signal of the ring voltage controlled oscillator is retimed at the arrival moment of the injected clock calibration pulse signal.

Further, the calibration pulse generating circuit includes a three-input AND gate and a delay inversion module;

The input end of the delay inversion module is connected to the reference clock signal, and the output end outputs the reference clock signal delayed by the set time and inverted;

The first input end of the three-input AND gate is connected to the debounce enable signal; the second input end is connected to the reference clock signal, and the third input end is connected to the reference clock signal delayed by the set time and inverted;

When the debounce enable signal is at a high level, the calibration pulse generating circuit outputs a clock calibration signal whose rising edge is aligned with the rising edge of the reference clock signal and whose pulse width is the set delay time.

Further, the delay inversion module includes three inverters connected in sequence; the input signal is a reference clock signal, and the output is a clock signal whose delay time is the sum of the delay times of the three inverters and is inverted from the reference clock signal.

The beneficial effects of the present invention are as follows:

The frequency of the external input clock signal adopted by the present invention is the same as that of the multi-phase sampling clock, and the CML frequency dividing circuit is not required, thereby greatly reducing the power consumption of the circuit. At the same time, a multi-phase clock with low jitter and low clock skew can be directly generated in the PLL (phase-locked loop), no additional delay circuit is required, hardware overhead is reduced, and low clock jitter is achieved to ensure the accuracy of the ADC.

Description of drawings

The drawings are for the purpose of illustrating specific embodiments only and are not to be considered limiting of the invention, and like reference numerals refer to like parts throughout the drawings.

Figure 1 is a schematic diagram of the composition and connection of a PLL-based clock generation circuit;

Fig. 2 is a schematic diagram of the composition and connection of a traditional clock generation circuit;

3 is a schematic diagram of the composition and connection of a multi-phase clock generation circuit in an embodiment of the invention;

4 is a schematic diagram of the composition and connection of a ring voltage-controlled oscillator in an embodiment of the invention;

5 is a schematic diagram of the composition and connection of the delay unit in the embodiment of the invention;

FIG. 6 is a schematic diagram of the composition and connection of the calibration pulse generating circuit in the embodiment of the invention.

Detailed ways

The preferred embodiments of the present invention are described below in detail with reference to the accompanying drawings, wherein the accompanying drawings constitute a part of the present application, and together with the embodiments of the present invention, serve to explain the principles of the present invention.

This embodiment discloses a multi-phase clock generation circuit for a time-interleaved sampling ADC, as shown in FIG. 3 , including a ring voltage controlled oscillator 301 (RVCO), a phase tracking loop circuit 302 and a calibration pulse generation circuit 303;

The ring voltage controlled oscillator 301 and the phase tracking loop circuit 302 form a PLL loop; the ring voltage controlled oscillator 301 outputs clocks of multiple phases under the control of the first control voltage VCTRL output by the phase tracking loop circuit 302 The clock signal of any phase is fed back to the phase tracking loop circuit 302 for phase identification with the input reference clock signal, and the amplitude of the first control voltage VCTRL is adjusted, so that the output voltage of the ring voltage controlled oscillator 301 is adjusted. The frequency of the clock signal for the multiple phases is equal to the reference clock frequency.

The ring voltage controlled oscillator 301 also adjusts the phase difference between clock signals of multiple phases according to the second control voltage VTS input from the outside.

The calibration pulse generating circuit 303 is connected to the ring voltage controlled oscillator 301 for outputting a clock calibration signal to the ring voltage controlled oscillator 301, adjusting the internal clock of the ring voltage controlled oscillator 301, and eliminating the influence of clock jitter on the output clock signal.

As shown in FIG. 4 , the ring voltage controlled oscillator 301 includes four delay units and four NMOS transistors with the same structure, which are a first delay unit 401 , a second delay unit 402 , a third delay unit 403 and a fourth delay unit, respectively. 404, and a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.

Each delay unit includes input terminals IN and IP, output terminals OP and ON, and control terminals VC and VT.

The output terminals OP and ON of the first delay unit 401 are respectively connected with the input terminals IN and IP of the second delay unit 402 ; the output terminals OP and ON of the second delay unit 402 are respectively connected with the input terminal IN of the third delay unit 403 . , IP connection; the output terminals OP and ON of the third delay unit 403 are respectively connected with the input terminals IN and IP of the fourth delay unit 404; the output terminals OP and ON of the fourth delay unit 404 are respectively connected with the input terminals of the first delay unit 401 End IP, IN connection.

The input terminals IN and IP of the first delay unit 401 are connected across the first NMOS transistor; the input terminals IN and IP of the second delay unit 402 are connected across the second NMOS transistor; the input terminals IN and IP of the third delay unit 403 are connected across the first NMOS transistor. Three NMOS transistors; the input terminals IN and IP of the fourth delay unit 404 are connected across the fourth NMOS transistor.

A clock calibration signal is injected into one of the gate terminals of the four NMOS transistors, and the gate terminals of the other three NMOS transistors are all grounded. For example, the clock calibration signal INJ is injected into the gate terminal of the third NMOS transistor. The debounce effect of injecting the clock calibration signal INJ into the gate terminal of any NMOS transistor in the ring VCO 301 is the same,

Of course, an NMOS transistor is connected between the input terminals IN and IP of any delay unit, and the output terminal of the calibration pulse generating circuit is connected to its gate; and the other three NMOS transistors are replaced by other alternative components or circuits to achieve The matching of parasitic effects can also achieve the corresponding side debounce effect.

The control terminal VC of each delay unit is connected to the first control voltage VCTRL output by the phase tracking loop circuit 302, and outputs a clock signal with the same frequency as the reference clock signal under the control of the first control voltage VCTRL. And the phase difference of the signals at the input terminals IN and IP is controlled to be 180°, the phase difference between the signal at the input terminal IN and the signal at the output terminal OP is controlled by 45°, and the phase difference between the signal at the input terminal IP and the signal at the output terminal ON is It is controlled by 45°, and the phase difference of the signals at the output terminals OP and ON is controlled by 180°. In this way, the ring voltage-controlled oscillator 301 can finally obtain 8 high-performance clock signals with a phase difference of 45°. Since the 8-phase high-performance clock signal is generated by a phase-locked loop loop, the time skew between multi-phase clocks is low.

The control terminals VT of the first, second, third and fourth delay units 404 are respectively connected to the second control voltages VTS1 , VTS2 , VTS3 and VTS4 to adjust the phase of the clock signal output by each delay unit respectively.

For example, when multi-channel time interleaving ADC is performed, the phase difference of the clock signals connected to each ADC module is strictly required to be 45°. Due to path delay or other reasons, the phase difference reaching each ADC module may be deviated. The second control voltages VTS1, VTS2, VTS3, and VTS4 are adjusted to change the phase of the clock signal output by each delay unit, so that the phase difference reaching each ADC module is 45°.

Specifically, the circuit schematic diagram of each delay unit is shown in FIG. 5 , including a first inverter 501 , a second inverter 502 , a third inverter 503 , and a fourth inverter 504 . The first normally-on Transmission gate 505 , second always-on transmission gate 506 , first variable capacitor bank 507 and second variable capacitor bank 508 .

The output end of the first inverter 501 is connected to the input end of the second inverter 502; the output end of the third inverter 503 is connected to the input end of the fourth inverter 504; the input end of the first inverter 501 is connected to the input end of the fourth inverter 504; The output terminal of the third inverter 503 is connected across the first normally-on transmission gate 505; the input terminal of the third inverter 503 and the output terminal of the first inverter 501 are connected across the second normally-on transmission gate 506; connect the first variable capacitor bank 507 and the second variable capacitor bank 508 in parallel between the output end of the first inverter 501 and the output end of the third inverter 503;

The input end of the first inverter 501 is the input end IN of the delay unit, the input end of the third inverter 503 is the input end IP of the delay unit; the output end of the second inverter 502 is the output end OP of the delay unit , the output terminal of the fourth inverter 504 is the output terminal ON of the delay unit;

The control terminal VC of the first variable capacitor bank 507 is connected to the first control voltage VCTRL, and under the control of the first control voltage VCTRL, the capacitance value of the first variable capacitor bank 507 is changed, so that the ring voltage controlled oscillator 301 outputs a clock signal The frequency is equal to the input reference clock frequency.

The control terminal VT of the second variable capacitor bank 508 of each delay unit is respectively connected to the corresponding second control voltage VTS. Under the control of the second control voltage VTS, the capacitance value of the second variable capacitor bank 508 is changed. The phase of each delay unit is finely controlled, so as to realize the phase deviation adjustment of each phase clock in the ring voltage controlled oscillator 301 .

The calibration pulse generation circuit 303 is connected to the reference clock signal, and under the enablement of the debounce enable signal, a clock calibration signal aligned with the rising edge of the reference clock signal is output and injected into the gate terminal of the third NMOS transistor. The frequency of the reference clock is very high, and the output potentials of the output terminals OP and ON of the second delay unit 402 are not equal due to clock jitter. When the clock calibration pulse signal arrives, the third NMOS transistor is turned on. If the output potentials of the output terminals OP and ON of the second delay unit 402 are not equal, a current flows through the third NMOS transistor, so that the output terminals OP and ON are connected to each other. The voltage difference between the two is reduced to zero, that is, the zero-crossing point of the output signal of the ring voltage controlled oscillator 301 is re-timed at the arrival time of the injected clock calibration pulse signal, which achieves the effect of reducing the signal jitter.

As shown in FIG. 6 , the calibration pulse generating circuit 303 includes a three-input AND gate 601 and a delay inversion module 602;

The input end of the delay inversion module 602 is connected to the reference clock signal, and the output end outputs the reference clock signal delayed by the set time and inverted;

The first input terminal of the three-input AND gate 601 is connected to the debounce enable signal; the second input terminal is connected to the reference clock signal, and the third input terminal is connected to the reference clock signal delayed by the set time and inverted;

When the debounce enable signal is at a high level, the calibration pulse generating circuit 303 outputs a clock calibration signal whose rising edge is aligned with the rising edge of the reference clock signal, and whose pulse width is the set delay time.

Specifically, the delay inversion module 602 includes three inverters connected in sequence; the input signal is a reference clock signal, and the output is a clock signal whose delay time is the sum of the delay times of the three inverters and is inverted from the reference clock signal .

The input terminal of the calibration pulse generation circuit 303 is connected to the reference clock signal, monitors the clock jitter of the reference clock signal, and outputs the clock calibration signal to the ring voltage controlled oscillator 301 under the enablement of the debounce enable signal, and adjusts the ring voltage controlled oscillator 301. The internal clock of the voltage controlled oscillator 301 eliminates the influence of the reference clock jitter on the output clock signal.

To sum up, the frequency of the external input reference clock signal used in this embodiment is the same as the frequency of the multi-phase sampling clock, and the CML frequency dividing circuit is not required, thereby greatly reducing the power consumption of the circuit. At the same time, a multi-phase clock with low jitter and low clock skew can be directly generated in the phase-locked loop, no additional delay circuit is required, hardware overhead is reduced, and low clock jitter is achieved to ensure the accuracy of the ADC.

The above description is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited to this. Substitutions should be covered within the protection scope of the present invention.

Claims (10)

1. A multi-phase clock generation circuit for a time-interleaved sampling ADC is characterized by comprising a ring voltage-controlled oscillator, a phase tracking loop circuit and a calibration pulse generation circuit;

the annular voltage-controlled oscillator and the phase tracking loop circuit form a PLL loop; the ring voltage controlled oscillator outputs clock signals of a plurality of phases under the control of a first control voltage output by the phase tracking loop circuit; feeding back a clock signal of one phase to the phase tracking loop circuit to perform phase discrimination with an input reference clock signal, and adjusting the amplitude of the first control voltage to enable the frequency of the clock signals of a plurality of phases output by the annular voltage-controlled oscillator to be equal to the frequency of the reference clock signal;

the calibration pulse generating circuit is connected with the annular voltage-controlled oscillator and used for outputting a clock calibration signal to the annular voltage-controlled oscillator, adjusting an internal clock of the annular voltage-controlled oscillator and eliminating the influence of clock jitter on an output clock signal.

2. The multi-phase clock generation circuit of claim 1, wherein the ring voltage controlled oscillator further adjusts a phase difference between the clock signals of the plurality of phases according to the input second control voltage.

3. The multi-phase clock generation circuit of claim 2,

the ring voltage-controlled oscillator comprises a first delay unit, a second delay unit, a third delay unit and a fourth delay unit which are connected IN a ring shape and have the same structure, wherein the output ends OP and ON of the fourth delay unit are respectively connected with the input ends IP and IN of the first delay unit; the output ends OP and ON of the previous delay unit IN the other sequentially connected delay units are respectively connected with the input ends IN and IP of the next delay unit;

the phase difference of the signals of the input ends IP and IN of each delay unit is 180 degrees, and the phase difference of the signals of the output ends ON and OP is 180 degrees; the phase difference between the signal at the output OP and the signal at the input IN is 45 deg., and the phase difference between the signal at the output ON and the signal at the input IP is 45 deg..

4. The multi-phase clock generation circuit of claim 3,

the delay unit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first normally-on transmission gate, a second normally-on transmission gate, a first variable capacitor bank and a second variable capacitor bank;

the output end of the first inverter is connected with the input end of the second inverter; the output end of the third inverter is connected with the input end of the fourth inverter; a first normally-on transmission gate is connected between the input end of the first inverter and the output end of the third inverter in a bridging manner; a second normally-on transmission gate is connected between the input end of the third inverter and the output end of the first inverter in a bridging manner; a first variable capacitor bank and a second variable capacitor bank which are connected in parallel are connected between the output end of the first inverter and the output end of the third inverter in a bridging manner;

the input end of the first phase inverter is the input end IN of the delay unit, and the input end of the third phase inverter is the input end IP of the delay unit; the output end of the second inverter is the output end OP of the delay unit, and the output end of the fourth inverter is the output end ON of the delay unit;

the first variable capacitor bank is a voltage-controlled capacitor bank, a control end VC of the first variable capacitor bank is connected with a control voltage, and the frequency of the clock signal output by the delay unit is controlled by controlling the capacitance of the first variable capacitor bank;

the second variable capacitor bank is a voltage-controlled capacitor bank, a control terminal VT of the second variable capacitor bank is connected with a control voltage, and the phase of the clock signal output by the delay unit is controlled by controlling the capacitance of the second variable capacitor bank.

5. The multi-phase clock generation circuit of claim 4,

the control end VC of each delay unit is connected with the first control voltage output by the phase tracking loop circuit, so that the frequency of the output clock signal of each delay unit is the same as that of the reference clock signal;

the control terminals VT of the first, second, third and fourth delay units are respectively connected to the second control voltages VTs1, VTs2, VTs3 and VTs4, and respectively adjust the phases of the clock signals output by the delay units.

6. The multiphase clock generation circuit of claim 3, wherein said ring-shaped voltage controlled oscillator further comprises an NMOS transistor, wherein the source and drain of said NMOS transistor are connected across the input terminals IN, IP of any one of the delay units, and the gate is connected to the output terminal of the calibration pulse generation circuit.

7. The multiphase clock generation circuit of claim 3, wherein the ring-shaped voltage controlled oscillator further comprises four NMOS transistors corresponding to the four delay units, respectively, and a source and a drain of each NMOS transistor are connected across the input terminals IN and IP of the corresponding delay unit; the grid electrode of any one of the four NMOS tubes is connected with the output end of the calibration pulse generating circuit, and the grid electrodes of the other three NMOS tubes are grounded.

8. The multi-phase clock generation circuit of claim 6 or 7,

the calibration pulse generating circuit is connected with a reference clock signal, and outputs a clock calibration signal aligned with the rising edge of the reference clock signal to the grid electrode of the NMOS tube under the enabling of a jitter removal enabling signal;

when the annular voltage-controlled oscillator generates clock jitter, the output potentials of the output ends OP and ON of the delay units bridged by the NMOS tubes are not equal, the clock calibration pulse signal enables the NMOS tubes to be conducted, current flows through the NMOS tubes, the voltage difference between the output ends OP and ON is reduced to zero, and the zero crossing point of the output clock signal of the annular voltage-controlled oscillator is retimed at the arrival time of the injected clock calibration pulse signal.

9. The multi-phase clock generation circuit of claim 8, wherein the calibration pulse generation circuit comprises a three-input and gate and a delay inverting module;

the input end of the delay inverting module is connected with a reference clock signal, and the output end of the delay inverting module outputs a reference clock signal which delays for a set time and is inverted;

a first input end of the three-input end AND gate is connected with a debounce enabling signal; the second input end is accessed to a reference clock signal, and the third input end is accessed to a reference clock signal which delays the set time and is in reverse phase;

when the jitter removal enabling signal is in a high level, the calibration pulse generation circuit outputs the clock calibration signal with the pulse width of the set delay time, wherein the rising edge of the clock calibration signal is aligned with the rising edge of the reference clock signal.

10. The multi-phase clock generation circuit of claim 9, wherein the delay inverting module comprises three inverters connected in sequence; the input signal is a reference clock signal, and the output is a clock signal with the delay time of the sum of the delay times of the three inverters and the phase opposite to the reference clock signal.

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