CN111600606A - Multiphase clock generation circuit for time-interleaved sampling ADC - Google Patents
Multiphase clock generation circuit for time-interleaved sampling ADC Download PDFInfo
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Abstract
The invention relates to a multi-phase clock generating circuit for a time-interleaved sampling ADC (analog to digital converter), which belongs to the technical field of clock generation and realizes low clock jitter, low time deviation and low power consumption on the premise of ensuring high speed. The circuit comprises a ring voltage-controlled oscillator, a phase tracking loop circuit and a calibration pulse generating circuit; the annular voltage-controlled oscillator and the phase tracking loop circuit form a PLL loop; the annular voltage-controlled oscillator outputs clock signals of a plurality of phases under the control of a first control voltage output by the phase tracking loop circuit; the calibration pulse generating circuit is connected with the annular voltage-controlled oscillator and used for outputting a clock calibration signal to the annular voltage-controlled oscillator, adjusting an internal clock of the annular voltage-controlled oscillator and eliminating the influence of clock jitter on an output clock signal. The invention generates the multi-phase clock with low jitter, low clock deviation and high precision, and has low power consumption and low hardware overhead.
Description
Technical Field
The invention relates to the technical field of clock generation, in particular to a multi-phase clock generation circuit for a time-interleaved sampling ADC (analog to digital converter).
Background
An Analog-to-Digital Converter (ADC) converts continuous-time and amplitude signals into discrete-time and quantized amplitude signals in a Digital processing system. ADCs have been widely used in electronic systems such as voice image processors, sonar radar processing systems, sensor networks, finite wireless communication systems, biomedical systems, test and measurement instruments, and the like. With the development of science and technology, the miniaturization, mobility and wearing of electronic products become mainstream, low power consumption becomes an important index of the electronic products, and in addition, the continuous development of wireless communication systems and the explosive increase of information caused by the rapid development of the internet of things bring huge challenges to the processing speed and the communication capacity of the systems. In summary, high-speed, high-precision and low-power ADC is usually a bottleneck of the performance of the whole system.
In recent years, multi-path time-interleaved ADCs are taken as the research focus of high speed, high precision and low power consumption, and one path of high speed ADC is synthesized by interleaving multi-path low speed ADCs in a time domain, so that the limit of single-path ADC speed under the same process is broken through. The precision and power consumption of the multi-path time-interleaved ADC are also important indexes for measuring the whole ADC. The precision is mainly limited by the performance of the single-path ADC, and offset error, gain error, time deviation and the like generated by time interleaving; the power consumption is mainly limited by a single-path ADC, a reference voltage driving circuit, a high-speed high-precision multi-phase clock generating circuit and the like. At present, a single-path ADC can ensure good performance under low power consumption, offset error, gain error and time deviation generated by time interleaving can be solved through a foreground or background calibration technology, the power consumption of a driving circuit of reference voltage can be reduced through incomplete error establishment of a calibration DAC, and a high-speed high-precision low-power-consumption multiphase clock generation circuit does not have a good solution at present. The currently known solutions are as follows:
firstly, as shown in fig. 1, a multiphase clock is generated by frequency division of a CML circuit through an externally input high frequency clock, then the clock level is converted into a CMOS level through a CML-to-CMOS circuit, and the multiphase sampling clock is finally obtained after subsequent calibration of a time deviation adjusting circuit. The significant disadvantage of this scheme is that the performance of the high-speed clock through external input is poor, and when the sampling clock frequency is high, the CML circuit needs a large current to realize high-speed frequency division, so that the power consumption of the clock circuit rises exponentially.
Secondly, as shown in fig. 2, a basic clock is generated through a PLL, then a multi-phase clock is delayed through a plurality of delay circuits, a clock level is converted into a CMOS level through a CML-to-CMOS circuit, and finally the multi-phase sampling clock is obtained through subsequent calibration of a time deviation adjusting circuit. A significant disadvantage of this scheme is that the high speed clock through each delay circuit degrades the clock jitter (jitter) and thus limits the accuracy of the ADC.
Disclosure of Invention
In view of the foregoing analysis, the present invention aims to provide a multi-phase clock generation circuit for a time-interleaved sampling ADC, which achieves low clock jitter, low time skew, and low power consumption while ensuring high speed.
The invention discloses a multi-phase clock generating circuit for a time-interleaved sampling ADC (analog to digital converter), which comprises an annular voltage-controlled oscillator, a phase tracking loop circuit and a calibration pulse generating circuit, wherein the annular voltage-controlled oscillator is connected with the phase tracking loop circuit;
the annular voltage-controlled oscillator and the phase tracking loop circuit form a PLL loop; the ring voltage controlled oscillator outputs clock signals of a plurality of phases under the control of a first control voltage output by the phase tracking loop circuit; feeding back a clock signal of one phase to the phase tracking loop circuit to perform phase discrimination with an input reference clock signal, and adjusting the amplitude of the first control voltage to enable the frequency of the clock signals of a plurality of phases output by the annular voltage-controlled oscillator to be equal to the frequency of the reference clock signal;
the calibration pulse generating circuit is connected with the annular voltage-controlled oscillator and used for outputting a clock calibration signal to the annular voltage-controlled oscillator, adjusting an internal clock of the annular voltage-controlled oscillator and eliminating the influence of clock jitter on an output clock signal.
Further, the ring voltage-controlled oscillator adjusts the phase difference between the clock signals of multiple phases according to the input second control voltage.
Further, the ring voltage-controlled oscillator comprises a first delay unit, a second delay unit, a third delay unit and a fourth delay unit which are connected IN a ring shape and have the same structure, wherein output ends OP and ON of the fourth delay unit are respectively connected with input ends IP and IN of the first delay unit; the output ends OP and ON of the previous delay unit IN the other sequentially connected delay units are respectively connected with the input ends IN and IP of the next delay unit;
the phase difference of the signals of the input ends IP and IN of each delay unit is 180 degrees, and the phase difference of the signals of the output ends ON and OP is 180 degrees; the phase difference between the signal at the output OP and the signal at the input IN is 45 deg., and the phase difference between the signal at the output ON and the signal at the input IP is 45 deg..
Further, the delay unit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first normally-on transmission gate, a second normally-on transmission gate, a first variable capacitor bank and a second variable capacitor bank;
the output end of the first inverter is connected with the input end of the second inverter; the output end of the third inverter is connected with the input end of the fourth inverter; a first normally-on transmission gate is connected between the input end of the first inverter and the output end of the third inverter in a bridging manner; a second normally-on transmission gate is connected between the input end of the third inverter and the output end of the first inverter in a bridging manner; a first variable capacitor bank and a second variable capacitor bank which are connected in parallel are connected between the output end of the first inverter and the output end of the third inverter in a bridging manner;
the input end of the first phase inverter is the input end IN of the delay unit, and the input end of the third phase inverter is the input end IP of the delay unit; the output end of the second inverter is the output end OP of the delay unit, and the output end of the fourth inverter is the output end ON of the delay unit;
the first variable capacitor bank is a voltage-controlled capacitor bank, a control end VC of the first variable capacitor bank is connected with a control voltage, and the frequency of the clock signal output by the delay unit is controlled by controlling the capacitance of the first variable capacitor bank;
the second variable capacitor bank is a voltage-controlled capacitor bank, a control terminal VT of the second variable capacitor bank is connected with a control voltage, and the phase of the clock signal output by the delay unit is controlled by controlling the capacitance of the second variable capacitor bank.
Furthermore, the control end VC of each delay unit is connected to the first control voltage output by the phase tracking loop circuit, so that the frequency of the output clock signal of each delay unit is the same as the frequency of the reference clock signal;
the control terminals VT of the first, second, third and fourth delay units are respectively connected to the second control voltages VTs1, VTs2, VTs3 and VTs4, and respectively adjust the phases of the clock signals output by the delay units.
Furthermore, the ring voltage-controlled oscillator also comprises an NMOS tube, the source electrode and the drain electrode of the NMOS tube are bridged between the input ends IN and IP of any delay unit, and the grid electrode of the NMOS tube is connected with the output end of the calibration pulse generating circuit.
Furthermore, the ring voltage-controlled oscillator further comprises four NMOS transistors respectively corresponding to the four delay units, and a source and a drain of each NMOS transistor are bridged between the input terminals IN and IP of the corresponding delay unit; the grid electrode of any one of the four NMOS tubes is connected with the output end of the calibration pulse generating circuit, and the grid electrodes of the other three NMOS tubes are grounded.
Furthermore, the calibration pulse generating circuit is connected with a reference clock signal, and outputs a clock calibration signal aligned with the rising edge of the reference clock signal to the grid electrode of the NMOS tube under the enabling of the jitter removal enabling signal;
when the annular voltage-controlled oscillator generates clock jitter, the output potentials of the output ends OP and ON of the delay units bridged by the NMOS tubes are not equal, the clock calibration pulse signal enables the NMOS tubes to be conducted, current flows through the NMOS tubes, the voltage difference between the output ends OP and ON is reduced to zero, and the zero crossing point of the output clock signal of the annular voltage-controlled oscillator is retimed at the arrival time of the injected clock calibration pulse signal.
Furthermore, the calibration pulse generation circuit comprises a three-input end AND gate and a delay inverting module;
the input end of the delay inverting module is connected with a reference clock signal, and the output end of the delay inverting module outputs a reference clock signal which delays for a set time and is inverted;
a first input end of the three-input end AND gate is connected with a debounce enabling signal; the second input end is accessed to a reference clock signal, and the third input end is accessed to a reference clock signal which delays the set time and is in reverse phase;
when the jitter removal enabling signal is in a high level, the calibration pulse generation circuit outputs the clock calibration signal with the pulse width of the set delay time, wherein the rising edge of the clock calibration signal is aligned with the rising edge of the reference clock signal.
Further, the delay inverting module comprises three inverters connected in sequence; the input signal is a reference clock signal, and the output is a clock signal with the delay time of the sum of the delay times of the three inverters and the phase opposite to the reference clock signal.
The invention has the following beneficial effects:
the frequency of the external input clock signal adopted by the invention is the same as the frequency of the multiphase sampling clock, and a CML frequency division circuit is not needed, so that the power consumption of the circuit is greatly increased. Meanwhile, a multi-phase clock with low jitter and low clock deviation can be directly generated in a Phase Locked Loop (PLL), an additional delay circuit is not needed, hardware overhead is reduced, low clock jitter is realized, and the precision of the ADC is ensured.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a schematic diagram of the connection of a PLL-based clock generation circuit;
FIG. 2 is a schematic diagram of the connection of a conventional clock generation circuit;
FIG. 3 is a schematic diagram of the connection of the multi-phase clock generating circuit according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of the connection of the components of the ring-shaped VCO in the embodiments of the present invention;
FIG. 5 is a schematic diagram of a delay cell connection according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the connection of the calibration pulse generating circuit according to the embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form a part hereof, and which together with the embodiments of the invention serve to explain the principles of the invention.
The present embodiment discloses a multi-phase clock generation circuit for a time-interleaved sampling ADC, as shown in fig. 3, including a ring voltage-controlled oscillator 301(RVCO), a phase tracking loop circuit 302, and a calibration pulse generation circuit 303;
the ring voltage-controlled oscillator 301 and the phase tracking loop circuit 302 form a PLL loop; the ring voltage controlled oscillator 301 outputs a plurality of phase clock signals under the control of the first control voltage VCTRL output by the phase tracking loop circuit 302; any one of the clock signals in the phase tracking loop circuit 302 is fed back to the phase tracking loop circuit 302 to perform phase discrimination with the input reference clock signal, and the amplitude of the first control voltage VCTRL is adjusted to make the frequency of the clock signal in multiple phases output by the ring-shaped voltage-controlled oscillator 301 equal to the frequency of the reference clock signal.
The ring-shaped voltage-controlled oscillator 301 also adjusts the phase difference between the clock signals of the plurality of phases according to the externally input second control voltage VTS.
The calibration pulse generating circuit 303 is connected to the ring-shaped voltage-controlled oscillator 301, and is configured to output a clock calibration signal to the ring-shaped voltage-controlled oscillator 301, adjust an internal clock of the ring-shaped voltage-controlled oscillator 301, and eliminate an influence of clock jitter on an output clock signal.
As shown in fig. 4, the ring-shaped voltage-controlled oscillator 301 includes 4 delay units and 4 NMOS transistors with the same structure, namely a first delay unit 401, a second delay unit 402, a third delay unit 403, and a fourth delay unit 404, and a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.
Each delay unit includes input terminals IN and IP, output terminals OP and ON, and control terminals VC and VT.
Wherein, the output terminals OP, ON of the first delay unit 401 are respectively connected with the input terminals IN, IP of the second delay unit 402; the output terminals OP, ON of the second delay unit 402 are connected to the input terminals IN, IP of the third delay unit 403, respectively; the output terminals OP, ON of the third delay unit 403 are connected to the input terminals IN, IP of the fourth delay unit 404, respectively; the output terminals OP, ON of the fourth delay unit 404 are connected to the input terminals IP, IN of the first delay unit 401, respectively.
The input ends IN and IP of the first delay unit 401 are connected across the first NMOS transistor; the input ends IN and IP of the second delay unit 402 are connected across the second NMOS transistor; the input ends IN and IP of the third delay unit 403 are connected across the third NMOS transistor; the input terminals IN and IP of the fourth delay unit 404 are connected across the fourth NMOS transistor.
And a clock calibration signal is injected into one gate terminal of the four NMOS tubes, and the gate terminals of the other three NMOS tubes are grounded. For example, the gate terminal of the third NMOS transistor injects the clock calibration signal INJ. The debounce effect of the gate-side injection clock calibration signal INJ using any one NMOS transistor in the ring-shaped voltage-controlled oscillator 301 is the same,
of course, an NMOS transistor is connected between the input terminals IN and IP of any one of the delay units, and the gate thereof is connected to the output terminal of the calibration pulse generating circuit; and other three NMOS tubes are replaced by other substitute elements or circuits to realize the matching of parasitic effects, and the corresponding side jitter removal effect can also be realized.
The control terminal VC of each delay cell is connected to the first control voltage VCTRL output by the phase tracking loop circuit 302, and outputs a clock signal having the same frequency as the reference clock signal under the control of the first control voltage VCTRL. And the phase difference of the signals of the input terminals IN, IP is controlled to 180 °, the phase difference of the signal of the input terminal IN and the signal of the output terminal OP is controlled to 45 °, the phase difference of the signal of the input terminal IP and the signal of the output terminal ON is controlled to 45 °, and the phase difference of the signals of the output terminals OP, ON is controlled to 180 °. Thus, the ring-shaped voltage-controlled oscillator 301 can finally obtain 8 high-performance clock signals with phase difference of 45 °. Since the 8-phase high performance clock signal is generated by a phase locked loop, the time skew between the multi-phase clocks is low.
The control terminals VT of the first, second, third and fourth delay units 404 are respectively connected to the second control voltages VTs1, VTs2, VTs3 and VTs4, and respectively adjust the phases of the clock signals output by the delay units.
For example, in the case of performing a multi-channel time-interleaved ADC, the phase difference of the clock signals connected to the respective ADC blocks is required to be strictly 45 °, and the phase difference reaching the respective ADC blocks may be varied due to a path delay or other reasons, and the phase difference reaching the respective ADC blocks may be adjusted to 45 ° by adjusting the second control voltages VTS1, VTS2, VTS3, and VTS4, respectively, to change the phase of the clock signal output from the respective delay units.
Specifically, the schematic circuit diagram of each delay unit is shown in fig. 5, and includes a first inverter 501, a second inverter 502, a third inverter 503, a fourth inverter 504, a first normally-on transmission gate 505, a second normally-on transmission gate 506, a first variable capacitor group 507, and a second variable capacitor group 508.
The output end of the first inverter 501 is connected with the input end of the second inverter 502; the output end of the third inverter 503 is connected to the input end of the fourth inverter 504; a first normally-on transmission gate 505 is connected between the input end of the first inverter 501 and the output end of the third inverter 503; a second normally-on transmission gate 506 is connected between the input end of the third inverter 503 and the output end of the first inverter 501 in a bridging way; a first variable capacitor group 507 and a second variable capacitor group 508 connected in parallel are connected between the output end of the first inverter 501 and the output end of the third inverter 503;
the input end of the first inverter 501 is the input end IN of the delay unit, and the input end of the third inverter 503 is the input end IP of the delay unit; the output end of the second inverter 502 is the output end OP of the delay unit, and the output end of the fourth inverter 504 is the output end ON of the delay unit;
the control terminal VC of the first variable capacitor group 507 is connected to a first control voltage VCTRL, and under the control of the first control voltage VCTRL, the capacitance value of the first variable capacitor group 507 is changed to make the frequency of the output clock signal of the ring-shaped voltage-controlled oscillator 301 equal to the frequency of the input reference clock.
The control terminal VT of the second variable capacitor group 508 of each delay unit is respectively connected to the corresponding second control voltage VTs, and under the control of the second control voltage VTs, the capacitance value of the second variable capacitor group 508 is changed, and the phase of each delay unit is finely controlled, thereby realizing the phase deviation adjustment of each phase clock in the ring-shaped voltage-controlled oscillator 301.
The calibration pulse generating circuit 303 receives a reference clock signal, outputs a clock calibration signal aligned with a rising edge of the reference clock signal under the enable of the debounce enable signal, and injects the clock calibration signal into a gate terminal of the third NMOS transistor, and when the input reference clock has a high frequency, clock jitter (jitter) causes an unequal output potential at the output terminal OP and ON of the second delay unit 402. When the clock calibration pulse signal arrives, the third NMOS transistor is turned ON, and if the output potentials of the output terminals OP and ON of the second delay unit 402 are not equal, a current flows through the third NMOS transistor, so that the voltage difference between the output terminals OP and ON is reduced to zero, that is, the zero-crossing point of the output signal of the ring-shaped voltage-controlled oscillator 301 is retimed to the arrival time of the injected clock calibration pulse signal, thereby achieving the effect of reducing signal jitter.
As shown in fig. 6, the calibration pulse generating circuit 303 includes a three-input and gate 601 and a delay inverting module 602;
the input end of the delay inverting module 602 is connected to a reference clock signal, and the output end outputs a reference clock signal which is delayed for a set time and is inverted;
a first input end of the three-input end and gate 601 is connected with a debounce enabling signal; the second input end is accessed to a reference clock signal, and the third input end is accessed to a reference clock signal which delays the set time and is in reverse phase;
when the debounce enable signal is at a high level, the calibration pulse generating circuit 303 outputs the clock calibration signal with a pulse width of a set delay time and a rising edge aligned with a rising edge of the reference clock signal.
Specifically, the delay inverting module 602 includes three inverters connected in sequence; the input signal is a reference clock signal, and the output is a clock signal with the delay time of the sum of the delay times of the three inverters and the phase opposite to the reference clock signal.
The input end of the calibration pulse generating circuit 303 is connected to a reference clock signal, the clock jitter of the reference clock signal is monitored, a clock calibration signal is output to the ring-shaped voltage-controlled oscillator 301 under the enable of a jitter removal enable signal, the internal clock of the ring-shaped voltage-controlled oscillator 301 is adjusted, and the influence of the reference clock jitter on the output clock signal is eliminated.
In summary, the frequency of the externally input reference clock signal adopted by the embodiment is the same as the frequency of the multiphase sampling clock, and a CML frequency division circuit is not needed, so that the power consumption of the circuit is increased greatly. Meanwhile, the multi-phase clock with low jitter and low clock deviation can be directly generated in the phase-locked loop, an additional delay circuit is not needed, the hardware overhead is reduced, the low clock jitter is realized, and the precision of the ADC is ensured.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A multi-phase clock generation circuit for a time-interleaved sampling ADC is characterized by comprising a ring voltage-controlled oscillator, a phase tracking loop circuit and a calibration pulse generation circuit;
the annular voltage-controlled oscillator and the phase tracking loop circuit form a PLL loop; the ring voltage controlled oscillator outputs clock signals of a plurality of phases under the control of a first control voltage output by the phase tracking loop circuit; feeding back a clock signal of one phase to the phase tracking loop circuit to perform phase discrimination with an input reference clock signal, and adjusting the amplitude of the first control voltage to enable the frequency of the clock signals of a plurality of phases output by the annular voltage-controlled oscillator to be equal to the frequency of the reference clock signal;
the calibration pulse generating circuit is connected with the annular voltage-controlled oscillator and used for outputting a clock calibration signal to the annular voltage-controlled oscillator, adjusting an internal clock of the annular voltage-controlled oscillator and eliminating the influence of clock jitter on an output clock signal.
2. The multi-phase clock generation circuit of claim 1, wherein the ring voltage controlled oscillator further adjusts a phase difference between the clock signals of the plurality of phases according to the input second control voltage.
3. The multi-phase clock generation circuit of claim 2,
the ring voltage-controlled oscillator comprises a first delay unit, a second delay unit, a third delay unit and a fourth delay unit which are connected IN a ring shape and have the same structure, wherein the output ends OP and ON of the fourth delay unit are respectively connected with the input ends IP and IN of the first delay unit; the output ends OP and ON of the previous delay unit IN the other sequentially connected delay units are respectively connected with the input ends IN and IP of the next delay unit;
the phase difference of the signals of the input ends IP and IN of each delay unit is 180 degrees, and the phase difference of the signals of the output ends ON and OP is 180 degrees; the phase difference between the signal at the output OP and the signal at the input IN is 45 deg., and the phase difference between the signal at the output ON and the signal at the input IP is 45 deg..
4. The multi-phase clock generation circuit of claim 3,
the delay unit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first normally-on transmission gate, a second normally-on transmission gate, a first variable capacitor bank and a second variable capacitor bank;
the output end of the first inverter is connected with the input end of the second inverter; the output end of the third inverter is connected with the input end of the fourth inverter; a first normally-on transmission gate is connected between the input end of the first inverter and the output end of the third inverter in a bridging manner; a second normally-on transmission gate is connected between the input end of the third inverter and the output end of the first inverter in a bridging manner; a first variable capacitor bank and a second variable capacitor bank which are connected in parallel are connected between the output end of the first inverter and the output end of the third inverter in a bridging manner;
the input end of the first phase inverter is the input end IN of the delay unit, and the input end of the third phase inverter is the input end IP of the delay unit; the output end of the second inverter is the output end OP of the delay unit, and the output end of the fourth inverter is the output end ON of the delay unit;
the first variable capacitor bank is a voltage-controlled capacitor bank, a control end VC of the first variable capacitor bank is connected with a control voltage, and the frequency of the clock signal output by the delay unit is controlled by controlling the capacitance of the first variable capacitor bank;
the second variable capacitor bank is a voltage-controlled capacitor bank, a control terminal VT of the second variable capacitor bank is connected with a control voltage, and the phase of the clock signal output by the delay unit is controlled by controlling the capacitance of the second variable capacitor bank.
5. The multi-phase clock generation circuit of claim 4,
the control end VC of each delay unit is connected with the first control voltage output by the phase tracking loop circuit, so that the frequency of the output clock signal of each delay unit is the same as that of the reference clock signal;
the control terminals VT of the first, second, third and fourth delay units are respectively connected to the second control voltages VTs1, VTs2, VTs3 and VTs4, and respectively adjust the phases of the clock signals output by the delay units.
6. The multiphase clock generation circuit of claim 3, wherein said ring-shaped voltage controlled oscillator further comprises an NMOS transistor, wherein the source and drain of said NMOS transistor are connected across the input terminals IN, IP of any one of the delay units, and the gate is connected to the output terminal of the calibration pulse generation circuit.
7. The multiphase clock generation circuit of claim 3, wherein the ring-shaped voltage controlled oscillator further comprises four NMOS transistors corresponding to the four delay units, respectively, and a source and a drain of each NMOS transistor are connected across the input terminals IN and IP of the corresponding delay unit; the grid electrode of any one of the four NMOS tubes is connected with the output end of the calibration pulse generating circuit, and the grid electrodes of the other three NMOS tubes are grounded.
8. The multi-phase clock generation circuit of claim 6 or 7,
the calibration pulse generating circuit is connected with a reference clock signal, and outputs a clock calibration signal aligned with the rising edge of the reference clock signal to the grid electrode of the NMOS tube under the enabling of a jitter removal enabling signal;
when the annular voltage-controlled oscillator generates clock jitter, the output potentials of the output ends OP and ON of the delay units bridged by the NMOS tubes are not equal, the clock calibration pulse signal enables the NMOS tubes to be conducted, current flows through the NMOS tubes, the voltage difference between the output ends OP and ON is reduced to zero, and the zero crossing point of the output clock signal of the annular voltage-controlled oscillator is retimed at the arrival time of the injected clock calibration pulse signal.
9. The multi-phase clock generation circuit of claim 8, wherein the calibration pulse generation circuit comprises a three-input and gate and a delay inverting module;
the input end of the delay inverting module is connected with a reference clock signal, and the output end of the delay inverting module outputs a reference clock signal which delays for a set time and is inverted;
a first input end of the three-input end AND gate is connected with a debounce enabling signal; the second input end is accessed to a reference clock signal, and the third input end is accessed to a reference clock signal which delays the set time and is in reverse phase;
when the jitter removal enabling signal is in a high level, the calibration pulse generation circuit outputs the clock calibration signal with the pulse width of the set delay time, wherein the rising edge of the clock calibration signal is aligned with the rising edge of the reference clock signal.
10. The multi-phase clock generation circuit of claim 9, wherein the delay inverting module comprises three inverters connected in sequence; the input signal is a reference clock signal, and the output is a clock signal with the delay time of the sum of the delay times of the three inverters and the phase opposite to the reference clock signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010564041.9A CN111600606B (en) | 2020-06-18 | 2020-06-18 | Multi-phase clock generation circuit for time interleaved sampling ADC |
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| CN202010564041.9A CN111600606B (en) | 2020-06-18 | 2020-06-18 | Multi-phase clock generation circuit for time interleaved sampling ADC |
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| CN111600606A true CN111600606A (en) | 2020-08-28 |
| CN111600606B CN111600606B (en) | 2023-05-23 |
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Cited By (5)
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| CN112787634A (en) * | 2020-12-30 | 2021-05-11 | 西安紫光国芯半导体有限公司 | Circuit for correcting clock duty ratio and correction control method and device thereof |
| CN114650058A (en) * | 2022-04-08 | 2022-06-21 | 福州大学 | BBPD module-based time-interleaved FLASH ADC circuit for realizing self-calibration |
| CN115334264A (en) * | 2022-08-17 | 2022-11-11 | 中国电子科技集团公司第四十四研究所 | CMOS image sensor on-chip clock generation circuit, module and method |
| WO2023087588A1 (en) * | 2021-11-16 | 2023-05-25 | 深圳市中兴微电子技术有限公司 | Sampling circuit, use method of sampling circuit, storage medium, and electronic device |
| CN117478130A (en) * | 2023-12-28 | 2024-01-30 | 南京美辰微电子有限公司 | Multiphase sampling clock generation circuit of time interleaving ADC |
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| CN112787634A (en) * | 2020-12-30 | 2021-05-11 | 西安紫光国芯半导体有限公司 | Circuit for correcting clock duty ratio and correction control method and device thereof |
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| CN114650058A (en) * | 2022-04-08 | 2022-06-21 | 福州大学 | BBPD module-based time-interleaved FLASH ADC circuit for realizing self-calibration |
| CN115334264A (en) * | 2022-08-17 | 2022-11-11 | 中国电子科技集团公司第四十四研究所 | CMOS image sensor on-chip clock generation circuit, module and method |
| CN115334264B (en) * | 2022-08-17 | 2024-04-09 | 中国电子科技集团公司第四十四研究所 | CMOS image sensor on-chip clock generation circuit, module and method |
| CN117478130A (en) * | 2023-12-28 | 2024-01-30 | 南京美辰微电子有限公司 | Multiphase sampling clock generation circuit of time interleaving ADC |
| CN117478130B (en) * | 2023-12-28 | 2024-04-02 | 南京美辰微电子有限公司 | Multiphase sampling clock generation circuit of time interleaving ADC |
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