CN109756104A - Two-phase dynamic synchronization clock generation circuit applied to charge pump system - Google Patents
Two-phase dynamic synchronization clock generation circuit applied to charge pump system Download PDFInfo
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Abstract
The present invention relates to a kind of two-phase dynamic synchronization clock generation circuits applied to charge pump system, including first via ring oscillator and No. second ring oscillator.Using the two-phase dynamic synchronization clock generation circuit applied to charge pump system in the invention, the ring oscillator structure to be interacted by two-way, it realizes when the nonsynchronous variation of phase occurs for clock signal when output by pushing acceleration to achieve the effect that dynamic synchronization mutually, it can be suitable for the occasion more demanding to frequency and Phase synchronization, there is better application value.
Description
Technical field
The present invention relates to digital chip technology field more particularly to Clock Synchronization Technology field, in particular to a kind of applications
In the two-phase dynamic synchronization clock generation circuit of charge pump system.
Background technique
In digit chip system, clock signal is in occupation of very important position.Such as digital analog converter ADC, data
Interface circuit, charge pump circuit etc. require an accurate clock signal.Clock signal is usually by external clock reference or crystalline substance
Vibration generates, but when the frequency required for external clock reference can not provide and phase, it is necessary to when portion designs one in the chip
Clock generation circuit generates clock signal.In standard CMOS process, generallys use ring oscillator and generate frequency of oscillation.
Refering to Figure 1, it is the electrical block diagram of prior art ring oscillator, this circuit structure phase
To simple, integrated level is high, and frequency of oscillation is codetermined by the series of the delay time of phase inverter, capacitance size and phase inverter,
Capacitor generallys use mos capacitance.
It please refers to shown in Fig. 2, is the electrical block diagram of two-phase dynamic synchronization clock generation circuit in the prior art,
In this two-phase dynamic synchronization clock generation circuit, by adding rest-set flip-flop, make all the way clock be converted to two-way inversion clock, but
It is that the two phase clock that this method generates can make Phase synchronization effect bad due to the delay of gate level circuit, especially in frequency
Rate is very fast, when synchronizing more demanding, just not applicable.
If the method using Fig. 1 and Fig. 2 generates two phase clock, since oscillator frequency is more demanding, the door of very little prolongs
Shi Keneng will make the offset of two-way clock signal phase more.And charge pump is more demanding to synchronizing for the not overlapping clock of two-phase,
Needing to reach another lateral capacitance of lateral capacitance opening will turn off in time, otherwise will appear current leakage problem, can not output circuit
Required high pressure.
Summary of the invention
The purpose of the present invention is overcoming at least one above-mentioned prior art, providing one kind can be realized clock
Synchronous effect is more preferably applied to the two-phase dynamic synchronization clock generation circuit of charge pump system.
To achieve the goals above, the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention has
There is following composition:
This is applied to the two-phase dynamic synchronization clock generation circuit of charge pump system, is mainly characterized by, the two-phase
Dynamic synchronization clock generation circuit includes:
First via ring oscillator is joined end to end by odd level oscillation module and is constituted, for generating synchronizing clock signals；
No. second ring oscillator, is joined end to end by odd level oscillation module and is constituted, and annular with the first via
Oscillator interaction, for generating synchronizing clock signals；
At least two phase inverters, the input terminal of at least two phase inverter are separately connected the two-phase dynamic synchronization clock
The output end of the same level-one oscillation module of generation circuit, for the output signal to the two-phase dynamic synchronization clock generation circuit
It is filtered, and the output end of at least two phase inverter exports the two-phase dynamic synchronization clock by output port and generates
The signal of circuit.
This is applied to the odd number of the first via ring oscillator of the two-phase dynamic synchronization clock generation circuit of charge pump system
Grade oscillation module output end respectively with the input of the odd level oscillation module of corresponding No. second ring oscillator
End is connected, and the output end of the odd level oscillation module of No. second ring oscillator is respectively with corresponding described
The input terminal of the odd level oscillation module of ring oscillator is connected all the way, the odd level vibration of the first via ring oscillator
The odd level oscillation module for swinging module and No. second ring oscillator includes starting of oscillation submodule and oscillation submodule.
The first via ring oscillator for being applied to the two-phase dynamic synchronization clock generation circuit of charge pump system includes the
Oscillator module, the first oscillation submodule, the second oscillation submodule, third oscillation submodule, the 4th oscillation submodule together, it is described
No. second ring oscillator includes the second starting of oscillation submodule, the 5th oscillation submodule, the 6th oscillation submodule, the 7th oscillation submodule
Block, the 8th oscillation submodule.
This is applied to the first defeated of the first oscillator module of the two-phase dynamic synchronization clock generation circuit of charge pump system
Enter one enable signal of end input, the second input terminal of the first oscillator module inputs the output of the 4th oscillation submodule
Signal, the third input terminal of the first oscillator module input it is described 5th oscillation submodule output signal, described first
The first input end of oscillation submodule inputs the output signal of the first oscillator module, and the of the first oscillation submodule
Two input terminals input the output signal of the second starting of oscillation submodule, the second oscillation submodule to the 4th oscillation submodule
First input end inputs the output signal of the first oscillation submodule to third oscillation submodule, the second oscillation respectively
Second input terminal of module to the 4th oscillation submodule inputs the 6th oscillation submodule to the 8th oscillation submodule respectively
Output signal,
The first input end of the 5th oscillation submodule inputs the output signal of the 8th oscillation submodule, and described the
Second input terminal of five oscillation submodules inputs the output signal of the first oscillator module, the second starting of oscillation submodule
First input end inputs an enable signal, the second input terminal input of the second starting of oscillation submodule the 5th oscillation submodule
Output signal, the third input terminal of the second starting of oscillation submodule input it is described first oscillation submodule output signal, institute
The first input end for stating the 6th oscillation submodule inputs the output signal of the second starting of oscillation submodule, the 6th oscillation submodule
The second output terminal of block inputs the output signal of the second oscillation submodule, the 7th oscillation submodule and the 8th oscillation
The first input end of module input respectively it is described 6th oscillation submodule and the 7th oscillation submodule output signal, the described 7th
Second input terminal of oscillation submodule and the 8th oscillation submodule inputs the 4th oscillation submodule and the 5th oscillation respectively
The output signal of module.
This is applied to the output end of the second oscillation submodule of the two-phase dynamic synchronization clock generation circuit of charge pump system
Third phase inverter is connected, the third phase inverter connects third output end, the output end connection of the 4th oscillation submodule
First phase inverter, first phase inverter connect the first output end, the output end connection the 4th of the 6th oscillation submodule
Phase inverter, the 4th phase inverter connect the 4th output end, and the output end of the 8th oscillation submodule connects the second phase inverter,
Second phase inverter connects second output terminal.
The oscillation submodule of two-phase dynamic synchronization clock generation circuit for being applied to charge pump system includes:
First order CMOS inverter, including the first PMOS tube and the first NMOS tube, the source electrode input of first PMOS tube
Supply voltage, the source electrode ground connection of first NMOS tube, the grid of the grid of first PMOS tube and first NMOS tube
It is connect with the second input terminal of the oscillation submodule；
Second level CMOS inverter, including the second PMOS tube and the second NMOS tube, the source electrode of second PMOS tube and institute
The drain electrode connection of the first PMOS tube is stated, the drain electrode of second PMOS tube is connected with the drain electrode of second NMOS tube, described
The source electrode of second NMOS tube is connect with the drain electrode of first NMOS tube, the drain electrode of second PMOS tube and the 2nd NMOS
The drain electrode of pipe is connect with the output end of the oscillation submodule, the grid of second PMOS tube and the grid of the second NMOS tube
It is connect with the first input end of the oscillation submodule；
Third level CMOS inverter, including third PMOS tube and third NMOS tube, the source electrode input of the third PMOS tube
Supply voltage, the source electrode ground connection of the third NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of third NMOS tube and institute
State the output end connection of oscillation submodule, the grid of the third PMOS tube and the grid of third NMOS tube and the oscillation submodule
The first input end of block connects.
The starting of oscillation submodule of two-phase dynamic synchronization clock generation circuit for being applied to charge pump system includes:
Fourth stage CMOS inverter, including the 4th PMOS tube and the 4th NMOS tube, the drain electrode of the 4th PMOS tube and institute
The drain electrode for stating the 4th NMOS tube is connect with the output end of the starting of oscillation submodule, the grid and the 4th NMOS of the 4th PMOS tube
The grid of pipe is connect with the first input end of the starting of oscillation submodule；
Level V CMOS inverter, including the 5th PMOS tube and the 5th NMOS tube, the drain electrode of the 5th PMOS tube and institute
The source electrode connection of the 4th PMOS tube is stated, the drain electrode of the 5th NMOS tube connect with the source electrode of the 4th NMOS tube, and described the
The source electrodes of five NMOS tubes is grounded, the grid of the grid of the 5th PMOS tube and the 5th NMOS tube with the starting of oscillation submodule
The connection of second input terminal；
6th grade of CMOS inverter, including the 6th PMOS tube and the 6th NMOS tube, the source electrode of the 6th PMOS tube and institute
The source electrode for stating the 5th PMOS tube is connected, the source electrode of the 6th NMOS tube ground connection, the drain electrode of the 6th PMOS tube and described
The drain electrode of 6th NMOS tube is connect with the output end of the starting of oscillation submodule, the grid and the 6th NMOS of the 6th PMOS tube
The grid of pipe is connect with the first input end of the starting of oscillation submodule；
The enabled pipe of 7th PMOS and the enabled pipe of the 7th NMOS, the 7th PMOS enable the enabled letter of grid input one of pipe
Number, the 7th PMOS enables the source electrode input supply voltage of pipe, and the 7th PMOS enables the drain electrode and the described 5th of pipe
The source electrode of PMOS tube and the connection of the source electrode of the 6th PMOS tube, the 7th NMOS enable the enabled letter of grid input one of pipe
Number, the 7th NMOS enables the source electrode ground connection of pipe, and it is defeated with the starting of oscillation submodule that the 7th NMOS enables draining for pipe
Outlet connection.
This is applied to the odd number of the first via ring oscillator of the two-phase dynamic synchronization clock generation circuit of charge pump system
The output end of the odd level oscillation module of grade oscillation module and No. second ring oscillator is all connected with capacitor, for changing clock frequency
Rate.
The capacitor for being applied to the two-phase dynamic synchronization clock generation circuit of charge pump system is mos capacitance.
It is mutual by two-way using the two-phase dynamic synchronization clock generation circuit applied to charge pump system in the invention
The ring oscillator structure of phase separation realizes when the nonsynchronous variation of phase occurs for clock signal when output by pushing mutually
Acceleration achievees the effect that dynamic synchronization, can be suitable for the occasion more demanding to frequency and Phase synchronization, has better
Application value.
Detailed description of the invention
Fig. 1 is the electrical block diagram of prior art ring oscillator.
Fig. 2 is the electrical block diagram of two-phase dynamic synchronization clock generation circuit in the prior art.
Fig. 3 is that the circuit structure of the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention is illustrated
Figure.
Fig. 4 is another circuit structure of the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
Schematic diagram.
Fig. 5 is the oscillation submodule of the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
Electrical block diagram.
Fig. 6 is the starting of oscillation submodule of the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
Electrical block diagram.
Fig. 7 is the two-way ring oscillation of the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
The electrical block diagram of any level oscillating unit of device.
Fig. 8 is the advanced timing of phase in the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
Figure.
Specific embodiment
It is further to carry out combined with specific embodiments below in order to more clearly describe technology contents of the invention
Description.
It please refers to shown in Fig. 3, is the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
Electrical block diagram.This is applied to the two-phase dynamic synchronization clock generation circuit of charge pump system, is mainly characterized by, institute
The two-phase dynamic synchronization clock generation circuit stated includes:
First via ring oscillator is joined end to end by odd level oscillation module and is constituted, for generating synchronizing clock signals；
No. second ring oscillator, is joined end to end by odd level oscillation module and is constituted, and annular with the first via
Oscillator interaction, for generating synchronizing clock signals；
At least two phase inverters, the input terminal of at least two phase inverter are separately connected the two-phase dynamic synchronization clock
The output end of the same level-one oscillation module of generation circuit, for the output signal to the two-phase dynamic synchronization clock generation circuit
It is filtered, and the output end of at least two phase inverter exports the two-phase dynamic synchronization clock by output port and generates
The signal of circuit.The difference of starting of oscillation submodule and oscillation submodule is whether there is enable signal, when making for starting of oscillation submodule
When energy signal ENL is high, it should not work applied to the two-phase dynamic synchronization clock generation circuit of charge pump system, when ENL is drawn
It is low, should be enabled applied to the starting of oscillation submodule in the two-phase dynamic synchronization clock generation circuit of charge pump system, start to generate vibration
Swing signal.The wherein input of every level-one oscillation module is the output of previous stage oscillation module, while output signal all the way being made
It is inputted for the feedback control of another way, accelerates overturning each other for pushing.
This is applied to the odd number of the first via ring oscillator of the two-phase dynamic synchronization clock generation circuit of charge pump system
Grade oscillation module output end respectively with the input of the odd level oscillation module of corresponding No. second ring oscillator
End is connected, and the output end of the odd level oscillation module of No. second ring oscillator is respectively with corresponding described
The input terminal of the odd level oscillation module of ring oscillator is connected all the way, the odd level vibration of the first via ring oscillator
The odd level oscillation module for swinging module and No. second ring oscillator includes starting of oscillation submodule and oscillation submodule.Its
In, first via ring oscillator includes the first oscillator module, the first oscillation submodule, the second oscillation submodule, third oscillation
Submodule, the 4th oscillation submodule, No. second ring oscillator include the second starting of oscillation submodule, the 5th oscillation submodule,
6th oscillation submodule, the 7th oscillation submodule, the 8th oscillation submodule, the first input end input one of the first oscillator module
Enable signal, the second input terminal of the first oscillator module inputs the output signal of the 4th oscillation submodule, described
The third input terminal of the first oscillator module inputs the output signal of the 5th oscillation submodule, the first oscillation submodule
First input end input the output signal of the first oscillator module, the second input terminal of the first oscillation submodule is defeated
Enter the output signal of the second starting of oscillation submodule, the first input end of the second oscillation submodule to the 4th oscillation submodule
The output signal of the first oscillation submodule to third oscillation submodule, the second oscillation submodule to the 4th are inputted respectively
Second input terminal of oscillation submodule inputs the output signal of the 6th oscillation submodule to the 8th oscillation submodule, institute respectively
The first input end for stating the 5th oscillation submodule inputs the output signal of the 8th oscillation submodule, the 5th oscillation submodule
Second input terminal of block inputs the output signal of the first oscillator module, the first input end of the second starting of oscillation submodule
An enable signal is inputted, the second input terminal of the second starting of oscillation submodule inputs the output letter of the 5th oscillation submodule
Number, the third input terminal of the second starting of oscillation submodule inputs the output signal of the first oscillation submodule, the 6th vibration
The first input end of vagrant's module inputs the output signal of the second starting of oscillation submodule, and the described 6th vibrates the second of submodule
Output end inputs the output signal of the second oscillation submodule, and the of the 7th oscillation submodule and the 8th oscillation submodule
One input terminal inputs the output signal of the 6th oscillation submodule and the 7th oscillation submodule, the 7th oscillation submodule respectively
Second input terminal of block and the 8th oscillation submodule inputs the 4th oscillation submodule and the 5th respectively and vibrates the defeated of submodule
Signal out.
In practical applications, it please refers to shown in Fig. 3, is the two-phase dynamic synchronization applied to charge pump system of the invention
The electrical block diagram of clock generation circuit.This is applied to the of the two-phase dynamic synchronization clock generation circuit of charge pump system
The output ends of two oscillation submodules connect third phase inverter, and the third phase inverter connects third output end OUT3, and described the
The output ends of four oscillation submodules connect the first phase inverter, first phase inverter the first output end of connection OUT1, and described the
The output ends of six oscillation submodules connect the 4th phase inverter, and the 4th phase inverter connects the 4th output end OUT4, and the described 8th
The output end for vibrating submodule connects the second phase inverter, and second phase inverter connects second output terminal OUT2, wherein due to this
The third output end OUT3 of first via ring oscillator and the first output end OUT1 is the different node with ring oscillator all the way
Place, therefore the clock of out of phase can be exported, and electricity is generated in the two-phase dynamic synchronization clock for being applied to charge pump system
It, such as should be applied to the two-phase dynamic synchronization clock generation circuit of charge pump system in road at the node of the identical series of two-way oscillator
In, the first output end OUT1 of the first via ring oscillator and the second output terminal OUT2 of No. second ring oscillator.In reality
In the application of border, the defeated of the two-phase dynamic synchronization clock generation circuit for being applied to charge pump system can be set according to specific requirements
Outlet number.
It please refers to shown in Fig. 5, is the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
Oscillation submodule electrical block diagram.The oscillation submodule includes:
First order CMOS inverter, including the first PMOS tube P1 and the first NMOS tube N1, the source of the first PMOS tube P1
Pole input supply voltage, the source electrode ground connection of the first NMOS tube N1, the grid and described first of the first PMOS tube P1
The grid of NMOS tube N1 is connect with the second input terminal of the oscillation submodule；
Second level CMOS inverter, including the second PMOS tube P2 and the second NMOS tube N2, the source of the second PMOS tube P2
Pole is connect with the drain electrode of the first PMOS tube P1, the drain electrode and the drain electrode of the second NMOS tube N2 of the second PMOS tube P2
It is connected, the source electrode of the second NMOS tube N2 is connect with the drain electrode of the first NMOS tube N1, the second PMOS tube P2's
Drain electrode and the drain electrode of the second NMOS tube N2 are connect with the output end of the oscillation submodule, the second PMOS tube P2's
The grid of grid and the second NMOS tube N2 are connect with the first input end of the oscillation submodule；
Third level CMOS inverter, including third PMOS tube P3 and third NMOS tube N3, the source of the third PMOS tube P3
Pole input supply voltage, the source electrode ground connection of the third NMOS tube N3, the drain electrode and third NMOS tube of the third PMOS tube P3
The drain electrode of N3 is connect with the output end of the oscillation submodule, the grid of the third PMOS tube P3 and third NMOS tube N3's
Grid is connect with the first input end of the oscillation submodule.
It please refers to shown in Fig. 6, is the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
Starting of oscillation submodule electrical block diagram.The starting of oscillation submodule includes:
Fourth stage CMOS inverter, including the 4th PMOS tube P4 and the 4th NMOS tube N4, the leakage of the 4th PMOS tube P4
The drain electrode of pole and the 4th NMOS tube N4 is connect with the output end of the starting of oscillation submodule, the grid of the 4th PMOS tube P4
The grid of pole and the 4th NMOS tube N4 are connect with the first input end of the starting of oscillation submodule；
Level V CMOS inverter, including the 5th PMOS tube P5 and the 5th NMOS tube N5, the leakage of the 5th PMOS tube P5
Pole is connect with the source electrode of the 4th PMOS tube P4, the drain electrode of the 5th NMOS tube N5 and the source electrode of the 4th NMOS tube N4
Connection, the source electrode ground connection of the 5th NMOS tube N5, the grid of the 5th PMOS tube P5 and the grid of the 5th NMOS tube N5 are equal
It is connect with the second input terminal of the starting of oscillation submodule；
6th grade of CMOS inverter, including the 6th PMOS tube P6 and the 6th NMOS tube N6, the source of the 6th PMOS tube P6
Pole is connected with the source electrode of the 5th PMOS tube P5, the source electrode ground connection of the 6th NMOS tube N6, the 6th PMOS tube P6
Drain electrode and the drain electrode of the 6th NMOS tube N6 connect with the output end of the starting of oscillation submodule, the 6th PMOS tube P6
Grid and the grid of the 6th NMOS tube N6 connect with the first input end of the starting of oscillation submodule；
7th PMOS enables pipe P7 and the 7th NMOS and enables pipe N7, and the grid input one that the 7th PMOS enables pipe P7 makes
It can signal, the source electrode input supply voltage of the enabled pipe P7 of the 7th PMOS, the drain electrode of the enabled pipe P7 of the 7th PMOS and institute
The source electrode connection of the source electrode and the 6th PMOS tube P6 of the 5th PMOS tube P5 is stated, the 7th NMOS enables the grid of pipe N7
An enable signal is inputted, the 7th NMOS enables the source electrode ground connection of pipe N7, and the 7th NMOS enables drain electrode and the institute of pipe N7
State the output end connection of starting of oscillation submodule.
It in practical applications, should be applied to the oscillation submodule of the two-phase dynamic synchronization clock generation circuit of charge pump system
In (refering to Fig. 5), when the first input end A1 and the second input terminal A2 input signal that vibrate submodule are synchronous, the first PMOS tube
Breadth length ratio is identical as third PMOS tube P3 after P1 and the second PMOS tube P2 series connection, the first NMOS tube N1 and the second NMOS tube N2 series connection
Breadth length ratio is identical as third NMOS tube N3 afterwards, i.e., corresponding driving is identical, therefore the circuit can be reduced to a CMOS inverter,
Ring oscillator stablizes output clock signal, and operating rate can reach most fast at this time.
It in practical applications, should be applied to the starting of oscillation submodule of the two-phase dynamic synchronization clock generation circuit of charge pump system
In (refering to Fig. 6), when the first input end A1 of starting of oscillation submodule and the second input terminal A2 input signal are synchronous, the 4th PMOS tube
Breadth length ratio is identical as the 6th PMOS tube P6 after P4 and the 5th PMOS tube P5 series connection, the 4th NMOS tube N4 and the 5th NMOS tube N5 series connection
Breadth length ratio is identical as the 6th NMOS tube N6 afterwards, i.e., corresponding driving is identical, therefore the circuit can be reduced to a CMOS inverter,
Ring oscillator stablizes output clock signal, and operating rate can reach most fast at this time.
When the first input end A1 of oscillation submodule (or starting of oscillation submodule), the second input terminal A2 input signal are asynchronous
When, the driving for the phase inverter that the first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1, the second NMOS tube N2 are formed will be weak
In the phase inverter of third PMOS tube P3, third NMOS tube N3 composition.4th PMOS tube P4, the 5th PMOS tube P5, the 4th NMOS tube
The driving of the phase inverter of N4, the 5th NMOS tube N5 composition will be weaker than the phase inverter of the 6th PMOS tube P6, the 6th NMOS tube N6 composition.
Driving reduces, and the time of phase inverter overturning will lag so that the delayed phase of output signal, operating rate will it is slow under
Come.
When the signal of first input end A1, the second input terminal A2 input of oscillation submodule (or starting of oscillation submodule) is asynchronous
When, it please refers to shown in Fig. 7, is the two-way of the two-phase dynamic synchronization clock generation circuit applied to charge pump system of the invention
The electrical block diagram of any level oscillating unit of ring oscillator.The circuit structure by No. 2 ring oscillators same level-one
It vibrates submodule to constitute, wherein the first input end and No. second ring oscillator of the oscillation submodule of first via ring oscillator
The first input end of oscillation submodule input UP_n moment and the signal of DOWN_n respectively, the vibration of the first via ring oscillator
The output end of the oscillation submodule of the output end of vagrant's module and No. second ring oscillator export respectively the UP_n+1 moment and
The signal at DOWN_n+1 moment, while the signal at the UP_n+1 moment and DOWN_n+1 moment is respectively as the second road ring oscillation
The feedback signal of the oscillation submodule of the oscillation submodule and first via ring oscillator of device, in practical applications, it is assumed that UP_n
The failing edge of failing edge ratio DOWN_n of phase advanced DOWN_n, UP_n shift to an earlier date Δ t, the delay of phase inverter is T, and UP_n+1 is turned over
Turn, and advanced DOWN_n+1 Δ t ' (please referring to Fig. 8).When DOWN_n overturning is height, if without the work of feedback signal UP_n+1
With it is low that DOWN_n+1, which is and then overturn, after phase inverter is delayed T；But under the action of feedback signal UP_n+1, due to UP_n+
1 advanced DOWN_n+1 Δ t ' overturning, N1, N2 pipe are connected at this time, and in parallel with N3 pipe, whole breadth length ratio increases, and load charging current
Increase, DOWN_n+1, which is pushed, accelerates overturning, leading time Δ t > Δ t '.It is recycled by n times, Δ t ' will be drawn increasingly
Small, so that UP_n+1 is more and more synchronous with DOWN_n+1, delayed phase is similarly.
This is applied to the odd number of the first via ring oscillator of the two-phase dynamic synchronization clock generation circuit of charge pump system
The output end of the odd level oscillation module of grade oscillation module and No. second ring oscillator is all connected with capacitor (refering to Fig. 4), is used for
Change clock frequency.In practical applications, clock frequency is also determined by the delay of oscillating unit and series.
The capacitor for being applied to the two-phase dynamic synchronization clock generation circuit of charge pump system can be mos capacitance.
It is mutual by two-way using the two-phase dynamic synchronization clock generation circuit applied to charge pump system in the invention
The ring oscillator structure of phase separation realizes when the nonsynchronous variation of phase occurs for clock signal when output by pushing mutually
Acceleration achievees the effect that dynamic synchronization, can be suitable for the occasion more demanding to frequency and Phase synchronization, has better
Application value.
In this description, the present invention is described with reference to its specific embodiment.But it is clear that can still make
Various modifications and alterations are without departing from the spirit and scope of the invention.Therefore, the description and the appended drawings should be considered as illustrative
And not restrictive.
Claims (9)
1. a kind of two-phase dynamic synchronization clock generation circuit applied to charge pump system, which is characterized in that the two-phase is dynamic
State synchronous clock generation circuit includes:
First via ring oscillator is joined end to end by odd level oscillation module and is constituted, for generating synchronizing clock signals；
No. second ring oscillator, is joined end to end by odd level oscillation module and is constituted, and with the first via ring oscillation
Device interaction, for generating synchronizing clock signals；
At least two phase inverters, the input terminal of at least two phase inverter are separately connected the two-phase dynamic synchronization clock and generate
The output end of the same level-one oscillation module of circuit is carried out for the output signal to the two-phase dynamic synchronization clock generation circuit
Filtering, and the output end of at least two phase inverter exports the two-phase dynamic synchronization clock generation circuit by output port
Signal.
2. the two-phase dynamic synchronization clock generation circuit according to claim 1 applied to charge pump system, feature exist
In, the output end of the odd level oscillation module of the first via ring oscillator respectively with the corresponding second road ring
The input terminal of the odd level oscillation module of shape oscillator is connected, the odd level oscillation module of No. second ring oscillator
Output end be connected respectively with the input terminal of the odd level oscillation module of the corresponding first via ring oscillator, institute
The odd level oscillation module of the odd level oscillation module for the first via ring oscillator stated and No. second ring oscillator
It include starting of oscillation submodule and oscillation submodule.
3. the two-phase dynamic synchronization clock generation circuit according to claim 2 applied to charge pump system, feature exist
In, the first via ring oscillator include the first oscillator module, the first oscillation submodule, the second oscillation submodule, the
Three oscillation submodules, the 4th oscillation submodule, No. second ring oscillator include the second starting of oscillation submodule, the 5th oscillation
Module, the 6th oscillation submodule, the 7th oscillation submodule, the 8th oscillation submodule.
4. the two-phase dynamic synchronization clock generation circuit according to claim 3 applied to charge pump system, feature exist
In the first input end of the first oscillator module inputs an enable signal, the second input of the first oscillator module
The output signal of end input the 4th oscillation submodule, the third input terminal input the described 5th of the first oscillator module
The output signal of submodule is vibrated, the first input end of the first oscillation submodule inputs the defeated of the first oscillator module
Signal out, the second input terminal of the first oscillation submodule input the output signal of the second starting of oscillation submodule, and described the
The first input end of two oscillation submodules to the 4th oscillation submodule inputs the first oscillation submodule to third respectively and vibrates
Second input terminal of the output signal of submodule, the second oscillation submodule to the 4th oscillation submodule inputs described the respectively
The output signal of six oscillation submodules to the 8th oscillation submodule,
The first input end of the 5th oscillation submodule inputs the output signal of the 8th oscillation submodule, the 5th vibration
Second input terminal of vagrant's module inputs the output signal of the first oscillator module, and the first of the second starting of oscillation submodule
Input terminal inputs an enable signal, and the second input terminal of the second starting of oscillation submodule inputs the defeated of the 5th oscillation submodule
Signal out, the third input terminal of the second starting of oscillation submodule input the output signal of the first oscillation submodule, and described the
The first input end of six oscillation submodules inputs the output signal of the second starting of oscillation submodule, the 6th oscillation submodule
Second output terminal inputs the output signal of the second oscillation submodule, the 7th oscillation submodule and the 8th oscillation submodule
First input end input respectively it is described 6th oscillation submodule and the 7th oscillation submodule output signal, it is described 7th oscillation
Second input terminal of submodule and the 8th oscillation submodule inputs the 4th oscillation submodule and the 5th oscillation submodule respectively
Output signal.
5. the two-phase dynamic synchronization clock generation circuit according to claim 4 applied to charge pump system, feature exist
In the output end of the second oscillation submodule connects third phase inverter, and the third phase inverter connects third output end, institute
The output end for the 4th oscillation submodule stated connects the first phase inverter, and first phase inverter connects the first output end, described
The output end of 6th oscillation submodule connects the 4th phase inverter, and the 4th phase inverter connects the 4th output end, the 8th vibration
The output end of vagrant's module connects the second phase inverter, and second phase inverter connects second output terminal.
6. the two-phase dynamic synchronization clock generation circuit according to claim 4 applied to charge pump system, feature exist
In the oscillation submodule includes:
First order CMOS inverter, including the first PMOS tube (P1) and the first NMOS tube (N1), first PMOS tube (P1)
Source electrode input supply voltage, the source electrode ground connection of first NMOS tube (N1), the grid of first PMOS tube (P1) and described
The grid of first NMOS tube (N1) is connect with the second input terminal of the oscillation submodule；
Second level CMOS inverter, including the second PMOS tube (P2) and the second NMOS tube (N2), second PMOS tube (P2)
Source electrode is connect with the drain electrode of first PMOS tube (P1), the drain electrode and second NMOS tube of second PMOS tube (P2)
(N2) drain electrode is connected, and the source electrode of second NMOS tube (N2) is connect with the drain electrode of first NMOS tube (N1), described
The drain electrode of second PMOS tube (P2) and the drain electrode of second NMOS tube (N2) are connect with the output end of the oscillation submodule,
The first input end of the grid of second PMOS tube (P2) and the grid of the second NMOS tube (N2) with the oscillation submodule
Connection；
Third level CMOS inverter, including third PMOS tube (P3) and third NMOS tube (N3), the third PMOS tube (P3)
Source electrode input supply voltage, the source electrode ground connection of the third NMOS tube (N3), the drain electrode and third of the third PMOS tube (P3)
The drain electrode of NMOS tube (N3) is connect with the output end of the oscillation submodule, the grid and third of the third PMOS tube (P3)
The grid of NMOS tube (N3) is connect with the first input end of the oscillation submodule.
7. the two-phase dynamic synchronization clock generation circuit according to claim 4 applied to charge pump system, feature exist
In the starting of oscillation submodule includes:
Fourth stage CMOS inverter, including the 4th PMOS tube (P4) and the 4th NMOS tube (N4), the 4th PMOS tube (P4)
Drain electrode and the drain electrode of the 4th NMOS tube (N4) are connect with the output end of the starting of oscillation submodule, the 4th PMOS tube
(P4) grid of grid and the 4th NMOS tube (N4) is connect with the first input end of the starting of oscillation submodule；
Level V CMOS inverter, including the 5th PMOS tube (P5) and the 5th NMOS tube (N5), the 5th PMOS tube (P5)
Drain electrode is connect with the source electrode of the 4th PMOS tube (P4), the drain electrode and the 4th NMOS tube of the 5th NMOS tube (N5)
(N4) source electrode connection, the source electrode ground connection of the 5th NMOS tube (N5), the grid and the 5th of the 5th PMOS tube (P5)
The grid of NMOS tube (N5) is connect with the second input terminal of the starting of oscillation submodule；
6th grade of CMOS inverter, including the 6th PMOS tube (P6) and the 6th NMOS tube (N6), the 6th PMOS tube (P6)
Source electrode is connected with the source electrode of the 5th PMOS tube (P5), the source electrode ground connection of the 6th NMOS tube (N6), and the described 6th
The drain electrode of PMOS tube (P6) and the drain electrode of the 6th NMOS tube (N6) are connect with the output end of the starting of oscillation submodule, described
The grid of 6th PMOS tube (P6) and the grid of the 6th NMOS tube (N6) are connect with the first input end of the starting of oscillation submodule；
The enabled pipe (P7) of 7th PMOS and the enabled pipe (N7) of the 7th NMOS, the grid input one of the enabled pipe (P7) of the 7th PMOS
Enable signal, the source electrode input supply voltage of the enabled pipe (P7) of the 7th PMOS, the leakage of the enabled pipe (P7) of the 7th PMOS
Pole is connect with the source electrode of the source electrode of the 5th PMOS tube (P5) and the 6th PMOS tube (P6), and the 7th NMOS is enabled
The grid for managing (N7) inputs an enable signal, and the source electrode of the enabled pipe (N7) of the 7th NMOS is grounded, and the 7th NMOS is enabled
The drain electrode of pipe (N7) is connect with the output end of the starting of oscillation submodule.
8. the two-phase dynamic synchronization clock generation circuit according to claim 1 applied to charge pump system, feature exist
In the odd level oscillation module of the odd level oscillation module of the first via ring oscillator and No. second ring oscillator
Output end is all connected with capacitor, for changing clock frequency.
9. the two-phase dynamic synchronization clock generation circuit according to claim 8 applied to charge pump system, feature exist
In the capacitor is mos capacitance.
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