CN105097752B - 一种半导体封装结构 - Google Patents

一种半导体封装结构 Download PDF

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Publication number
CN105097752B
CN105097752B CN201410790717.0A CN201410790717A CN105097752B CN 105097752 B CN105097752 B CN 105097752B CN 201410790717 A CN201410790717 A CN 201410790717A CN 105097752 B CN105097752 B CN 105097752B
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bare chip
pad
row
semiconductor package
area
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CN105097752A (zh
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刘兴治
杨家豪
陈盈志
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供一种半导体封装结构，包含基底；第一裸芯片，安装在基底，包含布置于第一排的具有第一焊盘面积的多个第一焊盘；以及布置于第二排的具有第二焊盘面积的多个第二焊盘；以及第二裸芯片，安装于基底，包含具有第一焊盘面积的多个第三焊盘，以及具有第二焊盘面积的多个第四焊盘，交替布置于第三排；第一接合导线，具有两个端，分别耦合到第一焊盘的一个和第四焊盘的一个；以及第二接合导线，具有两个端，分别耦合到第三焊盘的一个和第二焊盘的一个。通过上述技术方案，可以减少焊盘间距和焊盘占据面积从而有效地减少芯片大小。

Description

一种半导体封装结构
【技术领域】
本发明涉及半导体封装结构，且特别地涉及用于多裸芯片半导体封装结构的紧凑的裸芯片到裸芯片的引线接合焊盘布置设计。
【背景技术】
多裸芯片(multi-die)半导体封装由于对于多个功能的需求而变得越来越流行。为了降低产品成本，紧凑的封装大小和小的裸芯片大小是必要的。裸芯片到裸芯片引线接合技术(die-to-die wire bonding technology)在封装承包商是可用的。而且，应用裸芯片到裸芯片引线接合技术以减少封装大小和封装成本。为了减少成本，铜(Cu)导线在裸芯片到裸芯片引线接合技术中的使用很流行。然而，现有的裸芯片到裸芯片引线接合设计要求特定的裸芯片焊盘或封装面积用于引线接合要求。
因此，希望提供一种用于半导体封装结构的紧凑的裸芯片到裸芯片引线接合焊盘布置设计。
【发明内容】
有鉴于此，本发明特提供以下技术方案：
本发明提供一种半导体封装结构，包含基底；第一裸芯片，安装在基底，包含布置于第一排的具有第一焊盘面积的多个第一焊盘；以及布置于第二排的具有第二焊盘面积的多个第二焊盘；以及第二裸芯片，安装于基底，包含具有第一焊盘面积的多个第三焊盘，以及具有第二焊盘面积的多个第四焊盘，交替布置于第三排；第一接合导线，具有两个端，分别耦合到第一焊盘的一个和第四焊盘的一个；以及第二接合导线，具有两个端，分别耦合到第三焊盘的一个和第二焊盘的一个。
本发明还提供一种半导体封装结构，包含基底；安装于基底的第一裸芯片和第二裸芯片，每个第一和第二裸芯片包含：布置于第一排和第二排的焊盘，其中布置于第一排的焊盘的面积小于布置于第二排的焊盘的面积；第一接合导线，具有两个端，分别耦合到第一裸芯片的第一排的焊盘的一个和第二裸芯片的第二排的焊盘的一个；以及第二接合导线，具有两个端，分别耦合到布置于第一裸芯片的第二排的焊盘的一个和布置于第二裸芯片的第一排的焊盘的一个。
本发明还提供一种半导体封装结构，包含基底；第一裸芯片和第二裸芯片，安装在基底，每个第一和第二裸芯片包含：布置于第一排的具有第一焊盘面积的多个第一焊盘和具有第二焊盘面积的多个第二焊盘；导电指，位于基底，在第一和第二裸芯片之间；第一接合导线，具有两个端，分别耦合到第一裸芯片的第一焊盘的一个以及第二裸芯片的第二焊盘的一个；以及第二接合导线，分割成两个片段，其中两个片段，分别耦合到第一裸芯片的另一第一焊盘以及第二裸芯片的第一焊盘的一个，以及其中导电指耦合到两个片段。
通过上述技术方案，可以减少焊盘间距和焊盘占据面积从而有效地减少芯片大小。
【附图说明】
通过参考附图阅读后续详细描述和示例可以充分地理解本发明，其中：
图1A是显示半导体封装结构的一个示范性实施例的上视图，明确地显示用于半导体封装结构的紧凑的裸芯片到裸芯片引线接合焊盘布置设计的一个示范性实施例。
图1B是如图1A所示的半导体封装结构的一个示范性实施例的侧视图。
图2A是显示半导体封装结构的另一示范性实施例的上视图，明确地显示半导体封装结构的紧凑的裸芯片到裸芯片引线接合焊盘布置设计的另一示范性实施例。
图2B是如图2A所示的半导体封装结构的另一示范性实施例的侧视图。
图3A是显示半导体封装结构的又一示范性实施例的上视图，明确地显示半导体封装结构的紧凑的裸芯片到裸芯片引线接合焊盘布置设计的又一示范性实施例。
图3B是如图3A所示的半导体封装结构的又一示范性实施例的侧视图。
图4A是显示半导体封装结构的又一示范性实施例的上视图，明确地显示半导体封装结构的紧凑的裸芯片到裸芯片引线接合焊盘布置设计的又一示范性实施例。
图4B是如图4A所示的半导体封装结构的又一示范性实施例的侧视图。
【具体实施方式】
下文的描述是用于实施本发明的模式。此描述是为了图示本发明的一般原理且不应该被视为有限制意义。本发明的范围最好通过参考所附的权利要求来确定。在任何可能的情况下，相同的参考标号用在附图和描述中以指代相同或相似部分。
本发明将相对于特定实施例并参考某些附图来描述，但本发明不限于此且仅仅由权利要求来限制。所描述的附图仅仅是示意且非限制性的。在附图中，为了说明性的目的一些元件的大小可以放大且没有按比例绘制。大小和相对大小不对应于实际大小以实践本发明。
图1A是显示半导体封装结构500a的一个示范性实施例的上视图，明确地显示用于半导体封装结构500a的紧凑的裸芯片到裸芯片引线接合焊盘布置设计的一个示范性实施例。图1B是如图1A所示的半导体封装结构500a的一个示范性实施例的侧视图。在一个实施例中，半导体封装结构可以是倒装芯片封装，使用连接若干半导体裸芯片到基底的导电结构。而且，半导体封装结构可以是使用引线接合技术以彼此连接若干半导体裸芯片或连接半导体裸芯片到基底的封装结构。请参考图1A，半导体封装结构500a包含具有装置连接表面201的基底200。在一个实施例中，基底200，例如印刷电路板(Print Circuit Board，简称PCB)，可以由聚丙烯(Polypropylene，简称PP)形成。还应该注意基底200可以是单排或多排结构。多个导电线(未示出)可以嵌入在基底200中。在一个实施例中，导电线可包括信号线路片段或接地线路片段，其用于直接安装在基底200上的半导体裸芯片的输入/输出(I/O)连接。
如图1A和图1B所示，第一裸芯片202和第二裸芯片204通过接合过程分别安装在基底200的装置连接表面201上。在本实施例中，第一裸芯片202和第二裸芯片204彼此间隔距离A1，其可以等于或大于设计规则的裸芯片之间的最小间隔。在本实施例中，在第一裸芯片202和第二裸芯片204之间没有设计指。第一裸芯片202和第二裸芯片204的电路与基底200的电路经由位于接近第一裸芯片202的底面203和第二裸芯片204的底面205的多个导电结构(未示出)互连。在本实施例中，第一裸芯片202可包括位于其顶面207的焊盘，以及第二裸芯片204可包括位于其顶面209的焊盘，用于裸芯片到裸芯片信号连接。而且，位于第一裸芯片202和第二裸芯片204上的焊盘可具有至少两个焊盘面积尺寸。在本实施例中，具有多个第一焊盘面积的第一焊盘210和具有第二焊盘面积的多个第二焊盘212位于第一裸芯片202的顶面207。第一焊盘210布置在第一排(tier)206，以及第二焊盘212布置在第二排208。在一个实施例中，第一裸芯片202的第一排206和第二排208是彼此平行且彼此接近。在一个实施例中，第一裸芯片202的第一排206和第二排208平行于第一裸芯片202的边缘222，边缘222接近于第二裸芯片204，且第二排208比第一排206更接近于边缘222。就是说，没有焊盘横向地位于第二排208中的焊盘(第二焊盘212)和第一裸芯片202的边缘222之间。在本实施例中，第一焊盘210的第一焊盘面积设计为小于第二焊盘212的第二焊盘面积。就是说，具有较大焊盘面积的第二焊盘212布置为比具有较小焊盘面积的第一焊盘210更接近于边缘222。在本实施例中，第一焊盘210以第一间距P1布置于第一排，以及第二焊盘212以大于第一间距P1的第二间距P2布置于第二排。
而且，具有至少两个焊盘面积尺寸的焊盘位于第二裸芯片204上的单排中。在一个实施例中，如在图1A和1B中显示的，具有第一焊盘面积的多个第三焊盘214和具有大于第一焊盘面积的第二焊盘面积的多个第四焊盘216布置在第三排213。在本实施例中，第三焊盘214和第四焊盘216交替布置在第三排213。在本实施例中，第三焊盘214和第四焊盘216布置在接近于第二裸芯片204的边缘224。就是说，没有焊盘横向地位于在第三排213的焊盘(第三焊盘214和第四焊盘216)和第二裸芯片204的边缘224之间。
另外，裸芯片到裸芯片接合导线设计为耦合一个裸芯片的具有小焊盘面积的焊盘和另一裸芯片的具有大焊盘面积的另一焊盘。在一个实施例中，具有小焊盘面积的焊盘可用作用于第一接合的焊盘，以及具有大焊盘面积的焊盘可用作用于第二接合的焊盘。在金(Au)或Cu引线接合过程中，通过熔化接合导线的末端形成的银(Ag)/Cu球可使用压力、热和超声力来接触一个接合焊盘，以形成第一接合(1st接合)。接合导线然后到达对应接合焊盘，在不同的接合焊盘之间形成平缓的弧线或“环”。应用压力和超声力到接合导线以形成第二接合(2nd接合)(已知为楔形接合、针脚式接合或鱼尾接合)。通常对于Au或Cu引线接合过程，具有2nd接合的焊盘开口大小和焊盘间隔设计为比具有1st接合的焊盘开口要大的多。在本实施例中，如在图1A和1B中所显示，第一接合导线218的两端设计为分别耦合到在第一裸芯片202上具有第一焊盘面积的一个第一焊盘210和第二裸芯片204上具有大于第一焊盘面积的第二焊盘面积的一个第四焊盘216。在本实施例中，具有小焊盘面积的每个第一焊盘210可用作用于第一接合的焊盘，以及具有大焊盘面积的每个第四焊盘216可用作用于第二接合的焊盘。因此，第一接合导线218以第一角度B1接合第一焊盘210的一个，以及第一接合导线218以小于第一角度B1的第二角度B2接合第四焊盘216的一个。而且，第二接合导线220具有两个端，分别耦合到第二裸芯片204上的具有第一焊盘面积的一个第三焊盘214和第一裸芯片202上具有大于第一焊盘面积的第二焊盘面积的一个第二焊盘212。在本实施例中，具有小焊盘面积的每个第三焊盘214可用作用于第一接合的焊盘，以及具有大焊盘面积的每个第二焊盘212可用作用于第二接合的焊盘。因此，第二接合导线220以第一角度C1接合第三焊盘214的一个，以及第二接合导线220以小于第一角度C1的第二角度C2接合第二焊盘212的一个。在一些实施例中，为了避免交叉问题，第二接合导线220先于第一接合导线218的接合过程而接合。
半导体封装结构500a的一个示范性实施例提供了具有下文优点的紧凑的裸芯片到裸芯片引线接合焊盘布置设计。位于第一裸芯片和第二裸芯片的焊盘可具有至少两个焊盘面积尺寸用于第一接合和第二接合。对于第一裸芯片(例如，第一裸芯片202)，第一裸芯片的焊盘布置在两排，其中具有小焊盘面积的焊盘布置在第一排以及具有大焊盘面积的焊盘布置在第二排，第二排比第一排更接近第一裸芯片的边缘。因此，第一排的焊盘的间距比第二排的焊盘的间距小。相邻焊盘之间的间隔以及第一裸芯片的第一和第二排的焊盘占据面积可减小。此外，对于第二裸芯片(例如，第二裸芯片204)，具有至少两个焊盘面积尺寸的焊盘位于第二裸芯片的单排。仅仅对于第二接合与具有焊盘的传统的裸芯片相比，第二裸芯片的焊盘开口面积可减小。因此，芯片成本可减小。而且，由于没有指位于第一裸芯片和第二裸芯片之间，裸芯片到裸芯片间隔可以减少且使基板设计更简单以及帮助减少封装大小(成本)。
备选地，布置于第一裸芯片的第一排的具有第一焊盘面积的第一焊盘可具有灵活的焊盘间距以减少裸芯片接合焊盘面积。图2A是显示半导体封装结构500b的另一示范性实施例的上视图，明确地显示半导体封装结构500b的紧凑的裸芯片到裸芯片引线接合焊盘布置设计的另一示范性实施例。图2B是如图2A所示的半导体封装结构500b的另一示范性实施例的侧视图。与参考图1A和1B描述的那些相同或类似的实施例的元件，在下文中不再重复。在本实施例中，第一裸芯片202和第二裸芯片204彼此间隔距离A1，其可以等于或大于设计规则的裸芯片之间的最小间隔。在本实施例中，在本实施例中，在第一裸芯片202和第二裸芯片204之间没有设计指。而且，位于第一裸芯片202和第二裸芯片204的焊盘可具有至少两个焊盘面积尺寸。半导体封装结构500b的第二裸芯片204的焊盘布置与半导体封装结构500a的第二裸芯片204的焊盘布置相同。在图2A和2B中显示的半导体封装结构500b和在图1A和1B中显示的半导体封装结构500a之间的一个差别是半导体封装结构500b的第一裸芯片202的第一焊盘210a以小于半导体封装结构500a的第一焊盘210的第一间距P1的第三间距P3布置在第一排206。
除了半导体封装结构500a的优点，半导体封装结构500b还具有第一裸芯片的第一排的进一步减少的焊盘间距的优点。
备选地，用于裸芯片到裸芯片引线接合的两个裸芯片的焊盘可以设计为布置在多排以减少裸芯片宽度。图3A是显示半导体封装结构500c的又一示范性实施例的上视图，明确地显示半导体封装结构500c的紧凑的裸芯片到裸芯片引线接合焊盘布置设计的又一示范性实施例。图3B是如图3A所示的半导体封装结构500c的又一示范性实施例的侧视图。与参考图1A、1B、2A和2B描述的那些相同或类似的实施例的元件，为了简明起见在下文中不再重复。在本实施例中，第一裸芯片202和第二裸芯片204彼此间隔距离A1，其可以等于或大于设计规则的裸芯片之间的最小间隔。在本实施例中，在第一裸芯片202和第二裸芯片204之间没有设计指。而且，位于第一裸芯片202和第二裸芯片204的焊盘可具有至少两个焊盘面积尺寸。半导体封装结构500c第一裸芯片202的焊盘布置与半导体封装结构500a的第一裸芯片202的焊盘布置相同。如在图3A和3B中显示的半导体封装结构500c和如在图1A和1B中显示的半导体封装结构500a之间的一个差别是半导体封装结构500c的第一裸芯片202和第二裸芯片304都包含布置在两排的焊盘。在本实施例中，如在图3A和3B中显示的，具有第一焊盘面积的多个第三焊盘314和具有第二焊盘面积的多个第四焊盘316位于第二裸芯片304的顶面309。第三焊盘314位于第一排306，以及第四焊盘316位于第二排308。因此，如图3A所示的第二裸芯片304的裸芯片宽度W2可以以小于如图1A所示的第二裸芯片204的裸芯片宽度W1来设计。在一个实施例中，第二裸芯片304的第一排306和第二排308彼此平行且彼此接近。在一个实施例中，第二裸芯片304的第一排306和第二排308平行于第二裸芯片304的边缘324，边缘324接近于第一裸芯片202，以及第二排308比第一排306更接近于第二裸芯片304的边缘324。就是说，没有焊盘横向地位于第二排308中的焊盘(第四焊盘316)和第二裸芯片304的边缘324之间。在本实施例中，第三焊盘314的第一焊盘面积设计为小于第四焊盘316的第二焊盘面积。就是说，具有大焊盘面积的第四焊盘316布置为比具有小焊盘面积的第三焊盘314更接近于边缘324。
另外，裸芯片到裸芯片接合导线设计为耦合一个裸芯片的具有小焊盘面积的一个焊盘和另一裸芯片的具有大焊盘面积的另一焊盘。在一个实施例中，具有小焊盘面积的焊盘可用作用于第一接合的焊盘，以及具有大焊盘面积的焊盘可用作用于第二接合的焊盘。在本实施例中，如在图3A和3B中显示的，第一接合导线318具有两个端，设计为分别耦合到第一裸芯片202的第一排206的具有第一焊盘面积的第一焊盘210的一个和第二裸芯片304的第二排306的具有大于第一焊盘面积的第二焊盘面积的第四焊盘316的一个。因此，第一接合导线318可跨过第一裸芯片202的第二焊盘212而不连接第二焊盘212。在本实施例中，具有小焊盘面积的每个第一焊盘210可用作用于第一接合的焊盘，以及具有大焊盘面积的每个第四焊盘316可用作用于第二接合的焊盘。因此，第一接合导线318以第一角度B1接合第一焊盘210的一个，以及第一接合导线318以小于第一角度B1的第二角度B2接合第四焊盘316的一个。而且，第二接合导线320具有两个端，分别耦合到第二裸芯片304的第一排306的具有第一焊盘面积的第三焊盘314的一个和第一裸芯片202的第二排208的具有大于第一焊盘面积的第二焊盘面积的第二焊盘212的一个。因此，第二接合导线320可跨过第二裸芯片304的第四焊盘316而不连接第四焊盘316。在本实施例中，每个具有小焊盘面积的第三焊盘314可用作用于第一接合的焊盘，以及每个具有大焊盘面积的第二焊盘212可用作用于第二接合的焊盘。因此，第二接合导线320以第一角度C1接合第三焊盘314的一个，以及第二接合导线320以小于第一角度C1的第二角度C2接合第二焊盘212的一个。在一些实施例中，第一排206的第一焊盘210需要具有更大间距以避免交叉问题。第二排208的第二焊盘212、第一排306的第三焊盘314以及第二排308的第四焊盘316也是。
在本实施例中，半导体封装结构500c的第一接合导线318和相邻第二接合导线320之间的最小间距可减小到小于半导体封装结构500a的第一接合导线218和相邻第二接合导线220之间的最小间距，但是应该遵守引线接合规则。
半导体封装结构500c为紧凑的裸芯片到裸芯片引线接合焊盘布置设计提供下文的优点。位于第一裸芯片和第二裸芯片的焊盘可具有至少两个焊盘面积尺寸用于第一接合和第二接合。半导体封装结构500c的第一裸芯片202和第二裸芯片304都包含布置在两排的焊盘。具有小焊盘面积的焊盘(对于第一接合)布置在第一排以及具有大焊盘面积的焊盘(对于第二接合)布置在第二排，第二排比第一排更接近于第一裸芯片的边缘。因此，第一排的焊盘的间距比第二排的焊盘的间距小。而且，布置在多排的焊盘可导致减少了的裸芯片宽度。用于具有多排布置的焊盘的裸芯片的引线接合是允许的。因此，芯片成本可减小。而且，由于没有指位于第一裸芯片和第二裸芯片之间，裸芯片到裸芯片间隔可以减少且使基板更容易设计以及帮助减少封装大小(成本)。
备选地，指可以添加到基底用于裸芯片到裸芯片连接以扩大设计选择。图4A是显示半导体封装结构500d的又一示范性实施例的上视图，明确地显示半导体封装结构500d的紧凑的裸芯片到裸芯片引线接合焊盘布置设计的又一示范性实施例。图4B是如图4A所示的半导体封装结构500d的又一示范性实施例的侧视图。与参考图1A、1B、2A、2B、3A和3B描述的那些相同或类似的实施例的元件，在下文中不再重复。如在图4A和4B中显示，至少一个指428可以设计为位于基底200上，在第一裸芯片402和第二裸芯片404之间。在本实施例中，第一裸芯片402和第二裸芯片404彼此间隔距离A2，其大于或等于设计规则的裸芯片之间的最小间隔。例如，如图4A所示的半导体封装结构500d的第一裸芯片402和第二裸芯片404之间的距离A2可以大于或等于如图1A所示的半导体封装结构500a的第一裸芯片202和第二裸芯片204之间的距离A1。
在本实施例中，如在图4A和4B中所显示，第一裸芯片402可包含位于其顶面407的焊盘，以及第二裸芯片404可包含位于其顶面409的焊盘，用于裸芯片到裸芯片引线接合。而且，位于第一裸芯片402和第二裸芯片404的焊盘可具有至少两个焊盘面积尺寸。在本实施例中，具有第一焊盘面积的多个第一焊盘410，具有第二焊盘面积的多个第二焊盘412以及具有第一焊盘面积的多个第三焊盘419位于第一裸芯片402的顶面407。如图4A所示，第一焊盘410位于第一排406。而且，具有第二焊盘面积的第二焊盘412和具有小于第二焊盘面积的第一焊盘面积的第三焊盘419交替布置于第二排408。在一个实施例中，第一裸芯片402的第一排406和第二排408彼此平行且彼此接近。在一个实施例中，第一裸芯片402的第一排406和第二排408平行于第一裸芯片402的边缘422，边缘422接近于第二裸芯片404，且第二排408比第一排406更接近于边缘422。就是说，没有焊盘横向地位于第二排408的焊盘(第二焊盘412和第三焊盘419)与第一裸芯片402的边缘422之间。
而且，具有至少两个焊盘面积尺寸的焊盘位于第二裸芯片404的单排中。因此，如图4A所示的第二裸芯片404的裸芯片宽度W3可以以小于如图1A所示的第二裸芯片204的裸芯片宽度W1来设计。在本实施例中，如在图4A和4B中显示，具有第一焊盘面积的多个第四焊盘414和具有大于第一焊盘面积的第二焊盘面积的多个第五焊盘416布置在第三排413。在本实施例中，第四焊盘414和第五焊盘416布置于接近第二裸芯片404的边缘424。就是说，没有焊盘横向地位于第三排413的焊盘(第四焊盘414和第五焊盘416)和第二裸芯片404的边缘424之间。
另外，裸芯片到裸芯片接合导线设计为耦合一个裸芯片的具有小焊盘面积的一个焊盘和另一裸芯片的具有大焊盘面积的另一焊盘。在一个实施例中，具有小焊盘面积的焊盘可用作用于第一接合的焊盘，以及具有大焊盘面积的焊盘可用作用于第二接合的焊盘。在本实施例中，如在图4A和4B中显示的，第一接合导线418具有两个端，设计为分别耦合到第一裸芯片402上的具有第一焊盘面积的第一焊盘410的一个和第二裸芯片404上的具有大于第一焊盘面积的第二焊盘面积的第五焊盘416的一个。在本实施例中，具有小焊盘面积的每个第一焊盘410可用作用于第一接合的焊盘，以及具有大焊盘面积的每个第五焊盘416可用作用于第二接合的焊盘。因此，第一接合导线418以第一角度B1接合第一焊盘410的一个，以及第一接合导线418以小于第一角度B1的第二角度B2接合第五焊盘416的一个。
而且，第二接合导线220具有两个端，分别耦合到第二裸芯片404上具有第一焊盘面积的第四焊盘的414的一个以及第一裸芯片402上具有大于第一焊盘面积的第二焊盘面积的第二焊盘412的一个。在本实施例中，具有小焊盘面积的一些第四焊盘414可用作用于第一接合的焊盘，以及具有大焊盘面积的每个第二焊盘412可用作用于第二接合的焊盘。因此，第二接合导线420以第一角度C1接合第四焊盘414的一个，以及第二接合导线420以小于第一角度C1的第二角度C2接合第二焊盘412的一个。
在本实施例中，如在图4A和4B中显示，半导体封装结构500d还可包含另一接合导线以通过连接位于基底200上且在第一裸芯片402和第二裸芯片404之间的导电指428来耦合第一裸芯片402和第二裸芯片404。而且，连接导电指428的接合导线可设计为耦合第一裸芯片402的用于第一接合的焊盘和第二裸芯片404的用于第一接合的另一焊盘。另外，导电指428可用作用于第二接合的指。如在图4A和4B中显示的，第三接合导线426可分割为两个片段426a和426b。两个片段426a和426b分别耦合到第一裸芯片402的第三焊盘419的一个和第二裸芯片404的第四焊盘414的一个。第一裸芯片402的第三焊盘419的裸芯片焊盘开口面积小于第一裸芯片402的第二焊盘412的开口面积。第四焊盘414的裸芯片焊盘开口面积也小于第二裸芯片404的第五焊盘416的开口面积。因此，第一裸芯片402和第二裸芯片404的裸芯片焊盘开口面积可以进一步减少。而且，导电指428耦合到两个片段426a和426b。
半导体封装结构500d也为紧凑的裸芯片到裸芯片引线接合焊盘布置设计提供下文的优点。位于第一裸芯片和第二裸芯片可具有至少两个焊盘面积尺寸用于第一接合和第二接合。对于第一裸芯片(例如，第一裸芯片402)，第一裸芯片的焊盘布置在两排，其中具有小焊盘面积的焊盘布置于第一排以及具有小和大焊盘面积的焊盘布置于第二排，第二排比第一排更接近于第一裸芯片的边缘。因此，第一排的焊盘可具有比第二排的焊盘减少了的间距。第一裸芯片的第一和第二排的相邻焊盘之间的间隔和焊盘占据面积可减小。此外，对于第二裸芯片(例如，第二裸芯片404)，具有至少两个焊盘面积尺寸的焊盘位于第二裸芯片的单排。仅仅对于第二接合与具有焊盘的传统的裸芯片相比，第二裸芯片的焊盘开口面积可减小。因此，芯片成本可减小。尽管本发明已经以示例的方式以及依据优选实施例来描述，要理解，本发明不限于所公开的实施例。相反，其意于覆盖各种修改和类似布置(如对本领域技术人员是显而易见的)。因此，所附的权利要求的范围应该给予最广的解释以便包含所有这样的修改和类似布置。

Claims (19)

1.一种半导体封装结构，其特征在于：包含：
基底；
第一裸芯片，安装在所述基底上，包含：
布置于第一排的具有第一焊盘面积的多个第一焊盘；以及
布置于第二排的具有第二焊盘面积的多个第二焊盘；所述第一焊盘面积小于所述第二焊盘面积；
第二裸芯片，安装于所述基底上，包含：
具有所述第一焊盘面积的多个第三焊盘，以及具有所述第二焊盘面积的多个第四焊盘，所述多个第三焊盘和所述多个第四焊盘交替布置于第三排；
第一接合导线，具有两个端，分别耦合到所述多个第一焊盘中的一个和所述多个第四焊盘中的一个；以及
第二接合导线，具有两个端，分别耦合到所述多个第三焊盘的一个和所述多个第二焊盘的一个。
2.如权利要求1所述的半导体封装结构，其特征在于，所述第一裸芯片的所述第一排和所述第二排彼此平行且彼此接近。
3.如权利要求1所述的半导体封装结构，其特征在于，所述第一裸芯片的所述第一排和所述第二排平行于所述第一裸芯片的边缘，所述第一裸芯片的边缘接近所述第二裸芯片，以及所述第二排比所述第一排更接近所述边缘。
4.如权利要求1所述的半导体封装结构，其特征在于，所述第一焊盘以第一间距布置于所述第一排，以及所述第二焊盘以大于所述第一间距的第二间距布置于所述第二排。
5.如权利要求1所述的半导体封装结构，其特征在于，所述第一接合导线以第一角度接合所述多个第一焊盘的一个，以及所述第一接合导线以小于所述第一角度的第二角度接合所述多个第四焊盘的一个。
6.如权利要求1所述的半导体封装结构，其特征在于，所述第二接合导线以第三角度接合所述多个第三焊盘的一个，以及所述第二接合导线以小于所述第三角度的第四角度接合所述多个第二焊盘的一个。
7.如权利要求1所述的半导体封装结构，其特征在于，还包含：
导电指，位于所述基底上，在所述第一和第二裸芯片之间；以及
第三接合导线，分割为两个片段，其中所述两个片段分别耦合到所述多个第一焊盘中的另一个和所述多个第三焊盘中的另一个，以及其中所述导电指耦合到所述两个片段。
8.如权利要求1所述的半导体封装结构，其特征在于，所述第一裸芯片包含布置于所述第二排具有所述第一焊盘面积的第五焊盘。
9.如权利要求8所述的半导体封装结构，其特征在于，还包括：
导电指，位于所述基底，在所述第一和第二裸芯片之间；以及
第三接合导线，分割成两个片段，其中所述两个片段分别耦合到所述第五焊盘和另一所述第三焊盘，以及其中所述导电指耦合到所述两个片段。
10.一种半导体封装结构，其特征在于，包含：
基底；
安装于所述基底上的第一裸芯片和第二裸芯片，每个所述第一和第二裸芯片包含：布置于第一排和第二排的多个焊盘，其中布置于所述第一排的焊盘的面积小于布置于所述第二排的焊盘的面积；
第一接合导线，具有两个端，分别耦合到所述第一裸芯片的所述第一排的所述多个焊盘中的一个和所述第二裸芯片的所述第二排的所述多个焊盘中的一个；以及
第二接合导线，具有两个端，分别耦合到布置于所述第一裸芯片的所述第二排的所述焊盘的一个和布置于所述第二裸芯片的所述第一排的所述焊盘的一个。
11.如权利要求10所述的半导体封装结构，其特征在于，所述第一裸芯片或所述第二裸芯片的所述第一排和所述第二排彼此平行且彼此接近。
12.如权利要求10所述的半导体封装结构，其特征在于，布置于所述第一排的所述焊盘具有第一间距，以及布置于所述第二排的焊盘布置以具有所述第一间距的第二间距。
13.如权利要求10所述的半导体封装结构，其特征在于，所述第一接合导线以第一角度接合布置于所述第一裸芯片的所述第一排的所述多个焊盘的一个，以及所述第一接合导线以小于所述第一角度的第二角度接合布置于所述第二裸芯片的所述第二排的所述多个焊盘的一个。
14.如权利要求10所述的半导体封装结构，其特征在于，所述第二接合导线以第三角度接合布置于所述第一裸芯片的所述第二排的所述多个焊盘的一个，以及所述第二接合导线以小于所述第三角度的第四角度接合布置于所述第二裸芯片的所述第一排的所述多个焊盘的一个。
15.如权利要求10所述的半导体封装结构，其特征在于，所述第一裸芯片的所述第一排和所述第二排平行于所述第一裸芯片的边缘，所述第一裸芯片的边缘接近于所述第二裸芯片，以及所述第二排比所述第一排更接近所述边缘。
16.如权利要求10所述的半导体封装结构，其特征在于，所述第二裸芯片的所述第一排和所述第二排平行于所述第二裸芯片的边缘，所述第二裸芯片的边缘接近于所述第一裸芯片，且所述第二排比所述第一排更接近于所述边缘。
17.一种半导体封装结构，其特征在于，包含：
基底；
第一裸芯片和第二裸芯片，安装在所述基底上，每个所述第一和第二裸芯片包含：布置于第一排的具有第一焊盘面积的多个第一焊盘和具有第二焊盘面积的多个第二焊盘；所述第一焊盘面积小于所述第二焊盘面积；
导电指，位于所述基底，在所述第一和第二裸芯片之间；
第一接合导线，具有两个端，分别耦合到所述第一裸芯片的所述多个第一焊盘的一个以及所述第二裸芯片的所述多个第二焊盘的一个；以及
第二接合导线，分割成两个片段，其中所述两个片段，分别耦合到所述第一裸芯片的另一所述第一焊盘以及所述第二裸芯片的所述多个第一焊盘的一个，以及其中所述导电指耦合到所述两个片段。
18.如权利要求17所述的半导体封装结构，其特征在于，所述第一裸芯片包含布置于第二排具有所述第一焊盘面积的多个第三焊盘，以及其中所述第三焊盘的一个通过第三接合导线耦合到所述第二裸芯片的所述多个第二焊盘的一个。
19.如权利要求18所述的半导体封装结构，其特征在于，所述第一裸芯片的所述第一排和所述第二排平行于所述第一裸芯片的边缘，其接近于所述第二裸芯片，且所述第一排比所述第二排更接近于所述边缘。
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