CN105071798B

CN105071798B - Low-power consumption phase accumulator applied to digital PLL

Info

Publication number: CN105071798B
Application number: CN201510511188.0A
Authority: CN
Inventors: 潘少辉; 胡胜发
Original assignee: Anyka Guangzhou Microelectronics Technology Co Ltd
Current assignee: Guangzhou Ankai Microelectronics Co.,Ltd.
Priority date: 2015-08-19
Filing date: 2015-08-19
Publication date: 2018-06-26
Anticipated expiration: 2035-08-19
Also published as: CN105071798A

Abstract

The invention discloses the low-power consumption phase accumulators applied to digital PLL, include asynchronous counter, coincidence counter, delay acquisition module and synchronous output module, the output terminal of the asynchronous counter is connected to the input terminal of step counter, the delay acquisition module is used to acquire the signal of asynchronous counter and coincidence counter, and the synchronous output module is for the collected signal synchronism output of acquisition module that will be delayed.The present invention realizes phase-accumulated tally function using asynchronous counter and coincidence counter, reduces delay power consumption；And it is delayed to sample asynchronous, coincidence counter output not at the same level respectively using sampled signal, power consumption is further reduced, and sample again using synchronizing relay signal, so as to fulfill synchronism output.The present invention can be widely applied to electronic circuit field as the low-power consumption phase accumulator applied to digital PLL.

Description

Low-power consumption phase accumulator applied to digital PLL

Technical field

The present invention relates to electronic circuit fields, are particularly applied to the low-power consumption phase accumulator of digital PLL.

Background technology

Digital PLL（ADPLL）With the reduction of chip technology size, with its area and the advantage of power consumption, gradually take The trend of generation tradition PLL.Wherein, phase accumulator is used to judge that reference clock and the frequency multiple exported between high frequency clock close System（Integer part) because phase accumulator needs to count the number that high frequency output clock is overturn in reference clock cycle, institute Can be very high with the power consumption of its work, become a key factor of limitation system performance.

Fig. 1 is common phase accumulator circuit structure, i.e., counting is done to DCO_CLK and is added up, and CKR clocks go to sample, two The difference of secondary sampling is exactly the overturning periodicity of DCO_CLK in a CKR clock cycle.The frequency of DCO_CLK can be very high, such as blue The application of tooth/wifi, may be in 2.5G, and the adder that works in this frequency, power consumption is quite big, and considers more bit, may Adder, which is delayed, has been above the period of 2.5GHZ, it is impossible to ensure to complete correct plus coujnt.Practical application may Some changes are done on this structure, which is divided into two-stage, for example say a 8bit adder, are divided into a 2bit and one The working frequency of a 6bit, 6bit adder is the 1/4 of DCO_CLK, nevertheless, the power consumption of the structure is still very big.

Fig. 2 is the phase accumulator circuit of another structure, and the phase accumulator is by level-one grade asynchronous counter and finally What adder is formed, a specific high position how many grades of synchronous addition devices of how many grades of asynchronous counters and low level, depending on design technology With the frequency of DCO_CLK.The general structure, before what working frequency it is high, but be only merely asynchronous technique, power consumption can connect By, behind what synchronous addition device working frequency it is very low, realize circuit and power consumption it is also all relatively good.But there are one problems Be, before what output result because of asynchronous relationship step by step, can and the output of right-hand adder have a delay inequality, the first order The time difference of asynchronous counter is most, in order to which CKR samplings below can accurately sample phase accumulator output, generally requires The output of what asynchronous counter of front is delayed, wherein first order output delay is most, but first order output frequency is also very Height, in bluetooth, DCO_CLK 2.4, first order output still has 1.2G, and 1.2G signals are delayed by multistage（The asynchronous meter of level-one Number device delay may have 200ps, generally might have 4 to 6 grades), power consumption also can be very big；The second level exports 0.6GHZ, also What it is delayed by.So the structure phase accumulator circuit, although lower power consumption some, due to needing these delays single Member, power consumption be still difficult accomplish it is ultimate attainment.

Invention content

In order to solve the above-mentioned technical problem, the purpose of the present invention is：One kind is provided and overcome thes problems, such as that asynchronous counter is asynchronous The low-power consumption phase accumulator applied to digital PLL.

The technical solution adopted in the present invention is：Applied to the low-power consumption phase accumulator of digital PLL, include asynchronous Counter, coincidence counter, delay acquisition module and synchronous output module, the output terminal of the asynchronous counter are connected to synchronization The input terminal of counter, the delay acquisition module are used to acquire the signal of asynchronous counter and coincidence counter, the synchronization Output module is for the collected signal synchronism output of acquisition module that will be delayed.

Further, the asynchronous counter be N grade asynchronous counters, the coincidence counter be M grades of coincidence counters, institute The value for stating N and M is at least 1.

Further, the delay acquisition module includes N+M collecting unit and N+M-1 delay unit of series connection, The N+M collecting unit acquires the output signal of N grades of asynchronous counters and M grades of coincidence counters successively；The N+M acquisition The pulse input end of first collecting unit is triggered by sampled signal in unit, the N+M-1 that the sampled signal passes through series connection A delay unit generates N+M-1 delay sampled signal and sequentially inputs to the pulse input of corresponding N+M-1 collecting unit End.

Further, the synchronous output module includes synchronizing relay unit and N+M output unit, the sampled signal Synchronizing relay signal is generated by synchronizing relay unit, the synchronizing relay signal is separately input into the arteries and veins of N+M output unit Input terminal is rushed, the N+M output unit is successively read the output signal of corresponding N+M collecting unit.

Further, the synchronizing relay unit is phase inverter or delay circuit.

Further, it is used in the asynchronous counter, coincidence counter, N+M collecting unit and N+M output unit D type flip flop.

The beneficial effects of the invention are as follows：The present invention realizes phase-accumulated counting work(using asynchronous counter and coincidence counter Can, reduce delay power consumption；And it is delayed to sample asynchronous, coincidence counter output not at the same level respectively using sampled signal, Power consumption is further reduced, and is sampled again using synchronizing relay signal, so as to fulfill synchronism output.

Description of the drawings

Fig. 1 is common phase accumulator circuit schematic diagram；

Fig. 2 is the phase accumulator circuit schematic diagram that asynchronous counter is combined with coincidence counter in the prior art；

The physical circuit that Fig. 3 is Fig. 2 realizes figure；

Fig. 4 is circuit structure block diagram of the present invention；

Fig. 5 is circuit structure schematic diagram of the present invention；

Fig. 6 is one specific embodiment of circuit of the present invention.

Specific embodiment

The specific embodiment of the present invention is described further below in conjunction with the accompanying drawings：

With reference to Fig. 4, applied to the low-power consumption phase accumulator of digital PLL, include asynchronous counter, synchronous counting Device, delay acquisition module and synchronous output module, the output terminal of the asynchronous counter are connected to the input terminal of step counter, The delay acquisition module is used to acquire the signal of asynchronous counter and coincidence counter, and the synchronous output module is used to prolong When the collected signal synchronism output of acquisition module.

With reference to Fig. 5, preferred embodiment is further used as, the asynchronous counter is N grades of asynchronous counters, described same Step counter is M grades of coincidence counters, and the value of the N and M are at least 1.

With reference to Fig. 6, preferred embodiment is further used as, the delay acquisition module includes N+M collecting unit And N+M-1 delay unit of series connection, the N+M collecting unit acquire N grades of asynchronous counters and M grades of synchronous countings successively The output signal of device；The pulse input end of first collecting unit is triggered by sampled signal in the N+M collecting unit, institute Sampled signal is stated to generate N+M-1 delay sampled signal by N+M-1 delay unit of series connection and sequentially input to corresponding N The pulse input end of+M-1 collecting units.

Therefore sampled signal and sampled signal are generated respectively by N+M-1 delay unit of series connection N+M-1 prolong When sampled signal trigger the signal acquisition of corresponding N+M collecting unit to asynchronous counter and coincidence counter.

With reference to Fig. 6, be further used as preferred embodiment, the synchronous output module include synchronizing relay unit and N+M output unit, the sampled signal generate synchronizing relay signal, the synchronizing relay signal point by synchronizing relay unit It is not input to the pulse input end of N+M output unit, it is single that the N+M output unit is successively read corresponding N+M acquisition The output signal of member.

Preferred embodiment is further used as, the synchronizing relay unit is phase inverter or delay circuit.

With reference to Fig. 6, it is further used as preferred embodiment, the asynchronous counter, coincidence counter, N+M acquisition D type flip flop is used in unit and N+M output unit.

Fig. 3 of Fig. 5, Fig. 6 and the prior art referring to the present invention are as detailed description：

The present invention proposes a kind of phase accumulator circuit of new construction, consistent with the basic structure of Fig. 3, but last sampling It is not to do the output of asynchronous counter to be delayed step by step, but sampled signal CKR is done and is delayed step by step, in different moments sampling not The output of asynchronous counter at the same level and adder, and synchronizing relay signal CKR_B is used again（CKR_B can be the reverse phase letter of CKR Number or CKR pass through enough delay) primary sampling remake to the sampled result of front make finally to export and synchronize, so as to save Fall the power consumption that asynchronous counter high frequency output passes through delay unit, realize the reduction of phase accumulator circuit power consumption.

By taking Fig. 5 principles road as an example, before 2 grades be asynchronous counter, the first order is to DCO_CLK (if input signal is bluetooth Using then corresponding to 2.4GHZ) overturning is counted, 1.2G is exported, the second level counts overturning to the output of the first order, exports 600M signals. Assume that CKR is 26MHZ below, then 2.4G is compared to 26M, maximum count 93, so the output of K=6, i.e. up counter has altogether 7bit, maximum output 128.5bit is synchronous addition device below, and working frequency is in 600MHZ.

Real work circuit, design can also front be 4 grades (or even 6 grades can, herein only using 2 grades as illustrating), So 3 adders below are operated in 150MHZ.Illustrated with 2 grades of asynchronous count, Q<1>Output can compare Q<0>Evening, one D was touched Send out the transmission time of device, Q<K:2>Output can compare Q<1>The response time of a late synchronous addition device；So according to this paper's Method, CKR rising edges directly take sampling Q<0>, CKR be delayed a DFF transmission delay go again sampling Q<1>, while CKR is delayed One d type flip flop transmission delay and gone again after the coincidence counter response time sampling Q<K:2>, obtain PHQ<K:0>Signal, most Afterwards sampling PHQ is removed using CKR_B signals<K:0>Obtain the PHQF of synchronism output<K:0>Signal, last output is fully synchronized, It avoids because of asynchronous problem caused by asynchronous counter, while in turn avoids asynchronous counter high frequency output and be directly over prolonging Power problems caused by Shi Danyuan.

With reference to Fig. 6,3 grades of asynchronous countings herein before, behind 1 grade of synchronous addition device realize；4 collecting units sample respectively The pulse CKR and sampling pulse CKRD by delay<3:1>Control；And synchronous output module is then controlled by CKRB signals, CKRB signals are generated for sampling pulse CKR by reverse phase or by enough delay.

It is that the preferable of the present invention is implemented to be illustrated, but the invention is not limited to the implementation above Example, those skilled in the art can also make various equivalents under the premise of without prejudice to spirit of the invention or replace It changes, these equivalent deformations or replacement are all contained in the application claim limited range.

Claims

1. the low-power consumption phase accumulator applied to digital PLL, it is characterised in that：Include asynchronous counter, synchronous counting Device, delay acquisition module and synchronous output module, the output terminal of the asynchronous counter are connected to the input terminal of step counter, The delay acquisition module is used to acquire the signal of asynchronous counter and coincidence counter, and the synchronous output module is used to prolong When the collected signal synchronism output of acquisition module；The asynchronous counter is N grades of asynchronous counters, and the coincidence counter is The value of M grades of coincidence counters, the N and M are at least 1；

The delay acquisition module includes N+M collecting unit and N+M-1 delay unit of series connection, and the N+M are adopted Collection unit acquires the output signal of N grades of asynchronous counters and M grades of coincidence counters successively；First in the N+M collecting unit The pulse input end of a collecting unit is triggered by sampled signal, the N+M-1 delay unit that the sampled signal passes through series connection It generates N+M-1 delay sampled signal and sequentially inputs to the pulse input end of corresponding N+M-1 collecting unit；

The synchronous output module includes synchronizing relay unit and N+M output unit, and the sampled signal is prolonged by synchronizing Shi Danyuan generates synchronizing relay signal, and the synchronizing relay signal is separately input into the pulse input end of N+M output unit, institute State the output signal that N+M output unit is successively read corresponding N+M collecting unit.

2. the low-power consumption phase accumulator according to claim 1 applied to digital PLL, it is characterised in that：It is described same It is phase inverter or delay circuit to walk delay unit.

3. the low-power consumption phase accumulator according to claim 1 applied to digital PLL, it is characterised in that：It is described different D type flip flop is used in step counter, coincidence counter, N+M collecting unit and N+M output unit.