FI120524B - Phase battery for digital phase locked loop - Google Patents

Description

Phase battery for digital phase locked loop

The application is entirely concerned with digital phase-locked loops, and enhances their performance.

A radio transceiver consists of three main blocks: a transmitter, a receiver, and a frequency synthesizer. These blocks can be found, for example, on every mobile phone or WLAN card. The functions of the first two blocks are self-explanatory, but the frequency synthesizer is actually just as important. Its function is to produce a high quality RF signal (local oscillator or LO, local oscillator) which determines the frequency of the channel. Clearly, it is very important that the transmitter and receiver use exactly the same LO frequency. For example, in a GSM radio, it is necessary to produce an LO signal having a frequency between 935 and 960 MHz and a resolution of 15 200 kHz, which is a channel spacing. The absolute LO accuracy requirement is, of course, much stricter, in the order of a few kilohertz. Also, in a tightly packed frequency range, it is also important not to interfere with other receivers, which happens if the transmission frequency is not correct.

An embodiment of a typical phase locked loop frequency synthesizer is illustrated in Figure 1. The output frequency is provided by a voltage controlled oscillator (VCO). The output frequency is compared to a reference frequency (very stable crystal) by a phase-frequency detector (PFD). The difference is integrated and used to drive the VCO control via the charge pump and the loop filters so that the frequency difference is eliminated. In fact, the comparison is made for the phases of the signals instead of the frequencies because when two signals have the same phase difference, their frequencies are exactly the same. The output signal is split lower for phase comparison because the reference is typically at a much lower frequency (hundreds of kHz to tens of MHz) than the output frequency (to the GHz range in person-to-person communications). The output frequency is thus simply the reference frequency multiplied by the division ratio.

Traditionally, frequency synthesizers have been implemented using many application-specific analog blocks (VCO, charge pump, pre-splitter, and loop filter). On the other hand, for more than a decade, there has been a continuing trend to perform functions digitally 2 whenever possible. There are many motivations for this, but the most important one is probably the flexibility it offers. New, more advanced generations of integrated digital circuits (ICs) are being developed every 1-2 years. year. Transferring the digital circuitry plan to the new environment is relatively straightforward and low-risk, while the analogue circuitry needs to be largely redesigned. Furthermore, current state-of-the-art IC technology is always purely digital. Waiting for analogue alternatives always leads one generation behind advanced technology.

A particularly successful approach for implementing a fully digital implemented frequency synthesizer is described in [1]: "High-speed digital circuits for a 2.4 GHz all-digital RF" by Robert B. Staszewski, Jonh Wal-ber, Jinseok Koh, Poras T. Balsara frequency synthesizer in 130nm CMOS "IEEE, 2004. There are a few analog blocks remaining in the Digital Frequency Locked Loop (ADPLL), but they function over time, not in amplitude information, and are essentially composed of logic ports. As a result, they are fully compatible with digital technology.

The prior art and the invention will be described with reference to the figures and tables:

Figure 1 shows a continuous envelope of a fractional N PLL in a transmitter.

Figure 2 shows a related ADPLL architecture with variable phase accumulator (VPA)

Fig. 3 shows a rail implementation of the conventional adjustable phase battery (VPA) of Fig. 2 (see [1]).

Fig. 4 shows a prior art phase incrementer (uplink) having separate counting of the most significant and least significant bits (see [1]).

FIG. 5 is a prior art adjustable phase encoder having a re-timing of the 30 most significant bits (see [1]).

Figure 6 shows an example of an adjustable phase battery according to the invention.

Fig. 7 shows a support table of the encoder logic logic of the application example 4 to 2 of Fig. 6.

Fig. 8 shows descriptions of the signal names used in Figs. 6 and 7.

35 3

Figure 1 shows the conventional PLL described above. A state-of-the-art ADPLLon is illustrated in Figure 2. The voltage-controlled oscillator used in conventional PLL has been replaced by a digitally controlled oscillator (DCO), which digitally controls a large number of varactors instead of continuous analog voltage. The phase-5 format is fed back in digital format. Since the output stage of the DCO is only available as an analog signal, it must be digitized. This is accomplished by a digital battery that reads full RF cycles and a time-to-digital converter (TDC) which digitizes the fractional part of each phase. Because the DCO phase information is available in digital form and the DCO input is digital, the 10 analog PLL phase-frequency detector, charge pump, and loop filter can all be replaced by digital circuits. This offers many advantages such as low silicon area and the possibility of higher order active loop filtering and broadband phase modulation.

15 Problem to be solved

As an architecture, ADPLL relies on ultra-fast nanoscale CMOS technology. The highest operating frequency is at the output of the DCO, where the phase battery forms the bottleneck of the entire architecture. The phase accumulator is basically a modulo uplink (or las-20 discipline) operating at the RF frequency and its output is sampled at a much lower frequency or clock frequency. For example, the instantaneous DCO frequency of a 2.4 GHz mid-frequency system may be as high as 3 GHz. Conventional counters would not operate at such a high frequency because they have too many logical functions that should be completed within one RF signal period. In a conventional PLL, the 25 VCO output associated block is usually a very simple splitter that can always be designed to operate at a much higher frequency than the battery. As a result, ADPLL operating on current circuit solutions is limited to frequencies much lower than current conventional PLLs. All improvements in battery speed allow for the highest RF frequency maximum frequency to be generated by ADPLL.

30

State of the art and technology background

A linear implementation of the phase battery VPA is shown in Figure 3, where the counter is followed by samples. [1] basically discloses two solutions for speeding up the operation of the counter. The first solution uses the separate computation shown in Figure 4 for the least significant bits Rv [i] <l: 0> and the most significant bits Rv [i] <7: 2>, and the second solution re-schedules the most significant bits according to Figure 5. The first solution converts the 8-bit counter into two smaller counters and thus shortens the critical path. Like pipeline technology, the second solver-5 sun splits a critical path for two clock cycles by using wait logic. Document [1] describes these known solutions in detail.

These techniques take advantage of the predictability of modulo counter output, which is determined by the input clock only, and these techniques allow the counter to operate at a higher frequency. The disadvantage of these techniques is that they only consider the counter and do not take advantage of the fact that sampling is performed at a much lower frequency. As a result, the load and logic of the critical paths are not minimized, thus providing room for new improvements.

15

Description of the Invention

It is an object of the invention to further improve the frequency characteristics of the prior art phase battery and to enable frequency or pulse computation at high frequency.

The invention takes advantage of the fact that the ADPLL phase battery output need only be available at a reference frequency much lower than the input RF frequency. Summing can be done at a lower frequency for the word with the most significant 25 bits. The few least significant bits can be generated from the state information of the combination logic when the output needs to be generated. The status information is stored in a shift register which operates at full RF frequency.

The invention is characterized in what is disclosed in the independent claims 30 and the dependent claims describe the preferred embodiments of the invention.

The invention will now be described in detail with reference to Figures 6-8. Figure 6 illustrates one preferred embodiment of the phase battery of the invention. Figure 7 is a truth table of the 4 to 2 encoders shown in Figure 6. The table in Figure 8 shows the signal names of the figures 35 and this description.

5

One preferred topology of the device according to the invention is shown in the example of Figure 6. The phase accumulator includes a counter for the most significant bits CN2, a counter for the least significant bits CN1, a sampling means S for sampling at a lower clock frequency CKR.

5

The most significant bit counter CN2 comprises a 6-bit module counter which is clocked by the signal CKVD4. The least significant bit counter comprises a shift register clocked by the signal CKV, and the sampling is done by flip-flops acting as a sampling medium S clocked by a low-frequency clock CKR, and a com-10 binary codec 4 to 2 . The 4 to 2 encoder truth table is shown in Figure 7.

To form the top 6 bits of the 8-bit phase battery output, there is a 6-bit module counter clocked in CKVD4 (CKV divided by 4 clock). This counter 15 performs a summation operation on each CKVD4 cycle, i.e. every fourth CKV cycle. Therefore, the output corresponds to the top six bits of the 8-bit counter clocked at CKV. This same function is performed in the counter shown in the published topology (Figure 5), in which the counter is clocked by CKV, but the summing is done only every four cycles. The output of the six-bit module counter is sampled at 20 CKR, as it should.

The most significant feature of the inventive topology relates to the generation of the 2 lowest bits. Unlike the published topology of Figure 4, the topology of the invention does not explicitly include a counter of two lower bits. Instead, it uses a 25K CKV clocked shift register and a combination of 4 to 2 encoders as a counter CN1 and a number system converter EN. The following describes the logic that makes up the 2 lowest bits.

It should be obvious that any number of least significant bits of the modulo counter is also a modulo counter, and the regularity of the counter output allows derivation of the least significant bit waveform from the most significant bit waveform. For example, the output of the 3-bit module counter should ideally have waveforms like Rv [i] <2>, Rv [i] <l> and Rv [i] <0> in Fig. 7 (b) where we can determine the waveforms Rv [i] < l> and Rv [i] <0> logically, as long as tun-35 is not the waveform Rv [i] <2>. The Rv [i] <2> related status information required in this topology is provided in the delayed versions of the shift register Rv [i] <2> with the non-delayed signal Rv [i] <2>. When the shift register samples and delays Rv [i] <2>, we also obtain the waveforms Rv [i] <2> _d <2>, Rv [i] <2> _d <2> and Rv [ i] <2> _d <3> which with Rv [i] <2> provide enough in-5 information to derive Rv [i] <l> and Rv [i] <0> at any moment by simple logic such as The pattern can be seen. However, the crux of the matter here is that there is no need to derive the two lowest bits Rv [i] <l> and Rv [i] <0> for each CKV clock cycle, since the phase battery input only needs to be updated for each low-frequency clock CKR cycle. Therefore, CKR state information stored at Rv [i] <2> _d <3>, Rv [i] <2> _d <2> can first be sampled at low frequency clock-10,

Rv [i] <2> _d <l> and Rv [i] <2> and performs logical operations afterwards to derive the two least significant bits. Doing so can shift the logic from a high clock to a low clock. As shown in Fig. 6, the combinatorial 15 to 4 to 2 encoder EN following the sampling CKR clocked flip flops S calculates the final output value of the least significant bits. Figure 7 shows a 4 to 2 encoder truth table. The encoder can be easily synthesized by any HDL program in a straightforward manner. There is a lot of time for counting because CKR is a low frequency clock.

In summary, the proposed topology for improving the phase battery speed reduces logic operations in the fast clock frequency to shift register by shifting logical functions into the low clock frequency domain, thereby minimizing the length of critical timing paths.

In this example, the four to two encoder gets input from the shift register and the least significant bit counter from the least significant bit. It is easy to modify the implementation by changing the length of the shift register to compute the least significant bits. The encoder can only receive its input from the sampled shift register, as long as the encoder logic is changed accordingly. Claims 30 illustrate the scope of the invention and the invention is not limited to the topology of Figure 6.

It should be noted that Fig. 6 is an exemplary topology only, and various variations of the topology are possible as required. First, the most and least significant bits can have different subdivisions, and each phase battery word length is also scalable. Second, topology does not exclude the possibility of using different techniques in the 7 most significant bit counter, although in most cases it is not necessary. For example, the counter of most significant bits may employ any technique useful in counter optimization, such as those disclosed in [1].

5

At the same time, it is noted that a separate circuit for forming a clock divided by 4 is not really necessary for CKVD4. Since the clock divided by 4 is also used in the sigma-delta modulator in the ADPLL architecture, the same clock can be shared in this context, although one clock splitting circuit adds little cost when needed.

Advantages and Disadvantages The main advantage of the invention is a much higher speed than prior art, which allows the frequency at which the ADPLL architecture can be used to be increased. In addition, the invention has shown that it is possible to substantially reduce power consumption and to some extent reduce the silicon area of a phase battery. No obvious harm has been noted.

For comparison, two batteries were designed using the topology of the invention and the state of the art (Figure 5). The designs were first written on VHDL and then synthesized using the Synopsis Design Compiler using 65nm CMOS technology. The design of the invention could be synthesized for a clock frequency of 3.7 GHz without timing failure, whereas the prior art could only be synthesized for a clock frequency of 2.3 GHz. At an operating frequency of 2.3 GHz (the highest frequency allowed by the prior art), the design of our invention had a power consumption of 148 pW, while the prior art used 304 pW of power. Further, the cell size of the design of the invention was 226 pm 2 and the cell size of the prior art was 254 pm 2. It should be noted that the percentage increase in operating frequency when using the invention (about 60% according to the example above) would be even greater if the batteries were optimized by a customized design method instead of the digital design method used above.

A phase accumulator is useful for any calculation purpose, provided that the counter is sampled at a frequency much lower than the frequency of the counter input signal. Any frequency counter can use an invented topology, including frequency modulation detectors and high-speed pulse counters.

9

List of abbreviations used ADPLL: All digital phase locked loop = DCO Digitally controlled oscillator = Digitally controlled oscillator 5 GSM Global system for mobile communications = GSM phone system HDL Hardware description language = LSB Least significant bit = least significant bit PLL Phase locked loop = Phase lock RF Radio frequency = Radio Frequency, High Frequency 10

References [1] Robert B. Staszewski, Jonh Walber, Jinseok Koh, Poras T. Balsara, "Highspeed Digital Circuits for a 2.4 GHz RF Transmitter at 130nm 15 CMOS" IEEE, 2004

Claims (7)

1. Digital phase accumulator especially for use in a digital mode read, comprising at least two counters (CN1, CN2) to calculate the output frequency of a high frequency oscillator (CKV), using a first counter (CN1) for calculating the least significant bit and a second counter (CN2) for calculating the most significant bit, and the input frequencies are below a lower high frequency than said high frequency (CKV), characterized in that at least the least significant bit counter part (CN1) works in another number system, 10 and the number system change (EN) is performed after the sampling (S1) of the two counters (EN1, EN2) with a lower reference frequency (CRK). Digital phase accumulator for a digital mode read according to claim 1, characterized in that the least significant bit counters (CN1) are reset or synchronized with a signal from a common source coming from the input of the most significant bits counter (CN2). . Digital phase accumulator for a digital mode read according to claim 1 or 2, characterized in that the most significant bit counter (CN2) operates at a lower frequency (CKVD4), which is derived from the higher frequency (CKV). 4. A readout for a digital phase accumulator according to claim 3, characterized in that the input signal of the most significant bits is generated by dividing from the frequency of the calculated oscillator (CKV). 25 5. Model read for a digital phase accumulator according to which, as claimed by the preceding patent claims, characterized in that the least significant bit counter (CN1) contains a transfer register. 6. Model read for a digital phase accumulator according to claim 5, characterized in that the least significant bit counters (CN1) operate without feedback. A method for calculating a high frequency signal (CKV) with a much smaller sample collection frequency (CKR), which method comprises calculating the least significant bit with a counter (CN2) which operates at a lower frequency than the calculated signal (CKV). ), and calculating the less significant bit with a second counter (CN1), which works with the calculated higher frequency (CKV), characterized in that the calculation (CN1) of the least significant bit is performed with a different numbering system and the change of the numbering system is performed after sampling (S) of the low frequency signal (CKR) of both counters (CN1, CN2).