CN105047819B - A kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method - Google Patents
A kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 32
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- MVPPADPHJFYWMZ-UHFFFAOYSA-N chlorobenzene Chemical compound ClC1=CC=CC=C1 MVPPADPHJFYWMZ-UHFFFAOYSA-N 0.000 claims description 14
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/10—Deposition of organic active material
- H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
- H10K77/10—Substrates, e.g. flexible substrates
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/549—Organic PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The present invention relates to a kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method, utilize lift off technologies, spin-coating film technology and capillary percolation technology, on silicon/silicon dioxide substrate, it is sequentially prepared out sacrifice layer ZnO stripe arrays, the photoresist layer of the channel pore array of wire containing nanometer, organic semiconductor layer containing organic nano-wire array, metal electrode is formed respectively in organic semiconductor layer surface and the silicon chip substrate back side, draw corresponding source electrode, drain and gate, so as to prepare organic semiconductor nanowires arrays of conductive channel thin-film transistor.Preparation method of the present invention is novel, low manufacture cost, preparation technology is simple, controllable precise, the organic semiconductor nanowires arrays of conductive channel thin-film transistor has special organic nano line conductive array layer, effectively the threshold voltage of reduction organic semiconductor nanowires arrays of conductive channel thin-film transistor, will have very important application value in Novel Optoelectronic Device.
Description
Technical field
The present invention relates to semiconductor nano material and devices field, particularly a kind of organic semiconductor nanowires arrays of conductive
Channel thin-film transistor preparation method.
Background technology
With the development and the progress of society of science and technology, degree of dependence day of the people for information storage, transmission and its processing
Benefit increase.And semiconductor devices and technology be as the main carriers and material base of the storage, transmission and its processing of information,
The focus that numerous scientists fall over each other research is turned into.Thin film transistor (TFT), as a kind of very important semiconductor devices, in letter
The fields such as breath storage, transmission and processing play vital effect.However, up to now, existing large-scale use is thin
Film transistor, is a kind of semiconductor devices based on microelectronics silicon technology.It is this traditional based on silicon microelectronic technique thin film field
Effect transistor exists high to equipment requirement, and preparation technology is complicated, and cost is higher and device overall performance is limited, sensitivity, opens
The problems such as closing frequency and limited speed.Also, as people are for stepping up that high performance thin film transistor is required, based on micro-
The TFT of electronics silicon technology has been difficult to meet current information-intensive society to high sensitivity, high switching frequency and switch
The demand of the TFT of speed.
In recent years, nano material and nanostructured have the electricity of uniqueness, quantum optics dimensional effect because of it, for control material
Expect that performance provides another effective means in addition to its chemical composition is controlled.Especially by lift-off technologies, rotation
Film-forming process technology and capillary percolation technology are applied, the preparation of the organic semiconductor layer containing organic nano-wire array is realized.By
In nanometer wire organic conductive array layer in the special distribution of conducting channel, using boundary effect, make to be formed needed for inversion layer
The quantity of electric charge is reduced, so as to largely can effectively reduce this organic semiconductor nanowires arrays of conductive channel thin-film crystal
The threshold voltage of pipe, therefore, this is the novel TFT preparation based on organic semiconductor nanowires arrays of conductive raceway groove
There is provided one kind may and new approaches.
The content of the invention
It is an object of the invention to provide a kind of preparation of organic semiconductor nanowires arrays of conductive channel thin-film transistor
Method, to overcome defect present in prior art.
To achieve the above object, the technical scheme is that：A kind of organic semiconductor nanowires arrays of conductive raceway groove is thin
Film transistor preparation method, it is characterised in that：Utilize lift-off technologies, spin-coating film technology and capillary percolation work
Skill technology, on a silicon/silicon dioxide substrate, is sequentially prepared out sacrifice layer ZnO stripe arrays, wire containing nanometer channel pore array
Photoresist layer and the organic semiconductor layer containing organic nano-wire array, and in the organic semiconductor layer containing organic nano-wire array
Metal electrode is formed on surface and substrate back respectively, and draws corresponding source electrode, drain and gate, so as to complete organic half
The preparation of nanowires arrays of conductive channel thin-film transistor.
In an embodiment of the present invention, it is further comprising the steps of：
Step S1：HIGH TEMPERATURE PURGE is carried out to the silicon/silicon dioxide substrate using sulfuric acid/hydrogen peroxide solution；Using spin coating
Technique coats one layer of photoresist in the silicon/silicon dioxide substrate surface；Strip light is etched using electron beam lithography photoetching technique
Photoresist array；One ZnO layer is grown in the bar shaped photoresist array surface by magnetron sputtering technique, and uses lift-off
Technology prepares sacrifice layer ZnO stripe arrays；
Step S2：One thickness photoresist is coated on the sacrifice layer ZnO stripe arrays using spin coating proceeding, using electronics
Beam etching photoetching technique etches the thick photoresist layer containing pores array, and with sacrifice layer ZnO described in acid solution erosion removal
The ZnO stripe arrays of uncoated thick photoresist on stripe array, to be formed mutually in the channel region covered with thick photoresist layer
The nanometer wire channel pore array photoresist layer of isolation；
Step S3：Drop is covered with machine semiconductor precursor on the silicon/silicon dioxide print surface obtained through the step S2
Solution, and cause organic semiconductor precursor aqueous solution to penetrate into the nanometer wire channel pore array light using capillary percolation technology
In the pores array of photoresist layer, then using organic semiconductor spin coating proceeding and heat treatment for solidification, prepare and contain organic nano-wire array
Organic semiconductor layer；
Step S4：Evaporation process technology is covered using pattern mask partly to lead in organic containing organic nano-wire array respectively
The surface of body layer and silicon/silicon dioxide substrate back formation Cr/Au clad metal electrodes, and respectively to should be used as organic partly leading
Source electrode, the drain and gate of body nano-wire array conducting channel thin film transistor (TFT).
In an embodiment of the present invention, in the step S1, the silicon/silicon dioxide Substrate Area is 1cm × 1cm；
The silicon dioxide layer as thin film transistor (TFT) insulating barrier, and thickness be 30nm to 300nm；ZnO layer thickness be 20nm extremely
500nm；Single 1 μm to 5 μm of ZnO stripe arrays width；Adjacent single ZnO bar shapeds gap width is 1 μm to 2 μm；ZnO bar shapeds
100 μm of array region length；5 μm to 50 μm of ZnO stripe arrays peak width.
In an embodiment of the present invention, in the step S2, the thick photoresist is SU8 glue；The acid solution is
4mol/L to 6mol/L dilute hydrochloric acid solution；The thick photoresist thickness degree is 1 μm to 10 μm, and thick photoresist covering
Channel region length is 1 μm to 20 μm, and the channel region width of thick photoresist covering is 5 μm to 50 μm.
In an embodiment of the present invention, in the step S3, the organic semiconductor precursor solution includes pentacene
Or PEDOT/PSS chlorobenzene solution；The organic semiconductor spin coating proceeding revolution is 1000 rpm to 3000rpm；At the heat
The temperature of reason is：80 DEG C to 150 DEG C；The time of the heat treatment is：0.5 h to 3.0h；The organic semiconductor layer thickness is
5 nm to 30nm.
In an embodiment of the present invention, in the step S4, the pattern mask covering evaporation process technology is to adopt
Sample surfaces are covered with patterned metal mask, are then deposited in sample surfaces；The source electrode, the drain electrode and described
Gate area is 300 μm of 200 μ m, and the source electrode and the drain electrode spacing are 10 μm to 50 μm.
Compared to prior art, the invention has the advantages that：A kind of organic semiconductor proposed by the invention is received
The preparation method of nanowire arrays conducting channel thin film transistor (TFT) is a kind of based on low cost, large area solution preparation skill there is provided having given
Art, based on conventional spin-coating film technology, photoresist lift-off technologies and capillary percolation technology, is prepared
The photoresist layer of channel pore array containing nano wire, and further realized by spin coating organic semiconductor precursor solution containing organic nano wire
The preparation of the organic semiconductor layer of array, so as to prepare new organic semiconductor nanowires arrays of conductive channel thin-film crystal
Pipe, realizes the controllable preparation on silicon/silicon dioxide substrate surface of organic semiconductor nanowires arrays of conductive channel layer.The present invention
The preparation method proposed is novel, and low manufacture cost, preparation technology is simple, and device performance is flexibly controllable, prepared transistor
With special organic semiconductor nanowires arrays of conductive channel layer, therefore, boundary effect can be made full use of, effectively reduce organic half
The threshold voltage of nanowires arrays of conductive channel transistor, therefore, will have very important in Novel Optoelectronic Device
Application prospect.
Brief description of the drawings
Fig. 1 is silicon/silicon dioxide substrat structure schematic diagram in the present invention.
Fig. 2 is the silicon/silicon dioxide substrat structure schematic diagram of sacrifice layer ZnO stripe arrays in the present invention.
Fig. 3 is the silicon/silicon dioxide substrat structure top view of sacrifice layer ZnO stripe arrays in the present invention.
Fig. 4 is the silicon/silicon dioxide substrat structure schematic diagram of the photoresist containing channel region in the present invention.
Fig. 5 is the silicon/silicon dioxide substrat structure top view of the photoresist containing channel region in the present invention.
Fig. 6 is the silicon/silicon dioxide substrat structure schematic diagram of the channel pore array photoresist of wire containing nanometer in the present invention.
Fig. 7 is the silicon/silicon dioxide substrat structure top view of the channel pore array photoresist of wire containing nanometer in the present invention.
Fig. 8 is the silicon/silicon dioxide substrat structure schematic diagram of the organic semiconductor layer containing organic nano wire in the present invention.
Fig. 9 is the silicon/silicon dioxide substrat structure top view of the organic semiconductor layer containing organic nano wire in the present invention.
Figure 10 is the organic semiconductor layer containing organic nano wire in the present invention and the silicon/silicon dioxide substrate knot after plated electrode
Structure schematic diagram.
【Drawing reference numeral】：1- substrate silicons；2- silicon face silicon dioxide films；3-ZnO layers；4- thick photoresists layer；5- nano wires
Shape channel pore array；6- organic semiconductor nanowires arrays；The organic semiconductor layer of 7- coatings；8- source electrodes；9- drain electrodes；10-
Gate electrode.
Embodiment
Below in conjunction with the accompanying drawings, technical scheme is specifically described.
The present invention provides a kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method, utilizes
Lift-off technologies, spin-coating film technology and capillary percolation technology, on a silicon/silicon dioxide substrate, according to
It is secondary to prepare sacrifice layer ZnO stripe arrays, the photoresist layer of the channel pore array of wire containing nanometer and containing organic nano-wire array
Organic semiconductor layer, the organic semiconductor layer in organic nano linear array lead and substrate back on form metal electrode respectively,
And corresponding source electrode, drain and gate are drawn, so as to complete organic semiconductor nanowires arrays of conductive channel thin-film transistor
Prepare.
Further, in the present embodiment, it is further comprising the steps of：
Step S1：It is prepared by sacrifice layer ZnO stripe arrays：Silicon/silicon dioxide substrate is carried out using sulfuric acid/hydrogen peroxide solution
HIGH TEMPERATURE PURGE；One layer of photoresist is coated in the silicon/silicon dioxide substrate surface using spin coating proceeding；Using electron beam lithography light
Lithography etches bar shaped photoresist array；One ZnO is grown in the bar shaped photoresist array surface by magnetron sputtering technique
Layer, and sacrifice layer ZnO stripe arrays are prepared using lift-off technologies；
Step S2：Preparation containing nanometer wire channel pore array photoresist：Using spin coating proceeding in the sacrifice layer ZnO bars
A thickness photoresist is coated on shape array, the thick photoresist containing pores array is etched using electron beam lithography photoetching technique
Layer, and with described in acid solution erosion removal on sacrifice layer ZnO stripe arrays uncoated thick photoresist ZnO stripe arrays, with
Channel region covered with thick photoresist layer forms mutually isolated nanometer wire channel pore array photoresist layer；
Step S3：It is prepared by the organic semiconductor layer containing organic nano-wire array：In the silicon/dioxy obtained by the step S2
Drop is covered with machine semiconductor precursor solution on SiClx print surface, and is caused using capillary percolation technology before organic semiconductor
Solution is driven to penetrate into the hole of the nanometer wire channel pore array photoresist, then using organic semiconductor spin coating proceeding and Re Chu
Reason solidification, prepares the organic semiconductor layer containing organic nano-wire array；
Step S4：The formation of metal electrode：Evaporation process technology is covered respectively containing organic nano using pattern mask
The surface of the organic semiconductor layer of linear array and silicon/silicon dioxide substrate back formation Cr/Au clad metal electrodes, and respectively
Source electrode, drain and gate to should be used as organic semiconductor nanowires arrays of conductive channel thin-film transistor.
Further, in the present embodiment, in the step S1, the silicon/silicon dioxide Substrate Area be 1cm ×
1cm；The silicon dioxide layer as thin film transistor (TFT) insulating barrier, and thickness be 30nm to 300nm；ZnO layer thickness is 20nm
To 500nm；Single 1 μm to 5 μm of ZnO stripe arrays width；Adjacent single ZnO bar shapeds gap width is 1 μm to 2 μm；ZnO bars
100 μm of shape array region length；5 μm to 50 μm of ZnO stripe arrays peak width.
Further, in the present embodiment, in the step S2, the thick photoresist is SU8 glue；The acid solution is
4mol/L to 6mol/L dilute hydrochloric acid solution；The thick photoresist thickness degree is 1 μm to 10 μm, and thick photoresist covering
Channel region length is 1 μm to 20 μm, and the channel region width of thick photoresist covering is 5 μm to 50 μm.
Further, in the present embodiment, in the step S3, the organic semiconductor precursor solution includes simultaneously five
The chlorobenzene solution of benzene or PEDOT/PSS；The organic semiconductor spin coating proceeding revolution is 1000 rpm to 3000rpm；The heat
The temperature of processing is：80 DEG C to 150 DEG C；The time of the heat treatment is：0.5 h to 3.0h；The organic semiconductor layer thickness
For 5 nm to 30nm.
Further, in the present embodiment, in the step S4, the pattern mask covering evaporation process technology is
Sample surfaces are covered using patterned metal mask, are then deposited in sample surfaces；The source electrode, the drain electrode and institute
It is 300 μm of 200 μ m to state gate area, and the source electrode and the drain electrode spacing are 10 μm to 50 μm.
Further, in the present embodiment, organic semiconductor nanowires arrays of conductive is specifically prepared by the way of following
Channel thin-film transistor：
Step S1：The silicon/silicon dioxide substrate that 1cm × 1cm sizes, oxidated layer thickness are 30nm-300nm is taken, Fig. 1 is
Silicon/silicon dioxide substrat structure schematic diagram, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film.The silicon/silicon dioxide is served as a contrast
Bottom uses spin coating proceeding will be in silicon/silicon dioxide substrate table in the concentrated sulfuric acid/a small amount of hydrogen peroxide solution high temperature cleaning 30min
Face coats one layer of photoresist, and bar shaped photoresist array is etched using electron beam lithography photoetching technique, and Fig. 2 is to prepare sacrifice layer
The silicon/silicon dioxide substrat structure schematic diagram of ZnO stripe arrays, Fig. 3 is the silicon/titanium dioxide for preparing sacrifice layer ZnO stripe arrays
Silicon substrate structure top view, wherein 1 be substrate silicon, 2 silicon face silicon dioxide films, 3 be ZnO layer；And pass through magnetron sputtering skill
Art grows one layer of 20nm-500nm ZnO on print, and will then grown ZnO print lift-off techniques and be made has sacrifice
The silicon/silicon dioxide print of layer ZnO stripe arrays, graphical rear adjacent bar ZnO gap widths are 1 μm -2 μm, ZnO bar shapeds
100 μm of array region length, 5 μm -50 μm of ZnO stripe arrays peak width.
Step S2：One layer is coated on the silicon/silicon dioxide print with sacrifice layer ZnO stripe arrays using spin coating proceeding
Thick photoresist, etches the thick photoresist layer containing pores array using photoetching technique, forms thick photoresist thickness degree for 1 μm
- 10 μm, thick photoresist covering channel region length is 1 μm -20 μm, and thick photoresist covering channel region width is 5 μm of -50 μ
m.Fig. 4 is prepares the silicon/silicon dioxide substrat structure schematic diagram of the layer of thick photoresist containing channel region, and Fig. 5 contains channel region to prepare
The silicon/silicon dioxide substrat structure top view of domain thick photoresist layer, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 3 are
ZnO layer, 4 be thick photoresist；Finally, the ZnO strips battle array on print is fallen with 4mol/L-6mol/L hydrochloric acid solution erosion removal
Row, will form the channel pore array photoresist of wire containing nanometer on print, and Fig. 6 is preparation wire containing nanometer duct photoresist
Silicon/silicon dioxide substrat structure schematic diagram, Fig. 7 is the silicon/silicon dioxide substrat structure for preparing the duct of wire containing nanometer photoresist
Top view, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist, and 5 be nanometer wire channel pore array.
Step S3：First the chlorobenzene solution of organic semiconductor precursor aqueous solution such as pentacene or PEDOT/PSS is dropped in containing receiving
On the silicon/silicon dioxide print of rice noodles shape pores array thick photoresist, solution is set to penetrate into thickness using capillary percolation technology
In photoresist pores array, then organic semiconductor is spun to and is coated with organic semiconductor by use 1000rpm-3000rpm rotating speeds
On the silicon/silicon dioxide substrate print of array, and 0.5 h -3.0h are heat-treated under 80 DEG C of -150 DEG C of temperature conditionss, i.e., in sample
One layer of organic semiconductor layer containing organic nano line array is formed on piece, Fig. 8 has containing organic nano-wire array to prepare
The silicon/silicon dioxide substrat structure schematic diagram of organic semiconductor layer, Fig. 9 contains the organic semiconductor of organic nano-wire array to prepare
The silicon/silicon dioxide substrat structure top view of layer, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist
Layer, 6 be organic semiconductor nanowires array, 7 organic semiconductor layer to coat.
Step S4：It is being prepared for using on the silicon/silicon dioxide substrate print of the organic semiconductor layer containing organic nano wire
Pattern mask covering evaporation process formation Cr/Au clad metal electrodes, respectively as organic semiconductor nanowires arrays of conductive
Source electrode, the drain and gate of channel thin-film transistor；Wherein source electrode, drain and gate area be 300 μm of 200 μ m, source electrode with
The spacing that drains is 10 μm -50 μm；Figure 10 is to be prepared for silicon/bis- after the organic semiconductor layer containing organic nano wire and plated electrode
Silicon oxide substrate structural representation, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist layer, and 6 be organic
Conductor nano tube/linear array, 7 organic semiconductor layer to coat, 8 be source electrode, and 9 be drain electrode, and 10 be gate electrode.
In order to allow those skilled in the art to further appreciate that a kind of organic semiconductor nanowires array proposed by the invention
Conducting channel film crystal tube preparation method, is specifically described with reference to specific embodiment.
Embodiment 1
Step S1：The silicon/silicon dioxide substrate that 1cm × 1cm sizes, oxidated layer thickness are 30nm is taken, Fig. 1 is silicon/dioxy
Silicon substrate structural representation, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film.By the silicon/silicon dioxide substrate dense
Sulfuric acid/a small amount of hydrogen peroxide solution high temperature cleaning 30min, and will be coated using spin coating proceeding in silicon/silicon dioxide substrate surface
One layer of photoresist, bar shaped photoresist array is etched using electron beam lithography photoetching technique, and Fig. 2 is to prepare sacrifice layer ZnO bar shapeds
The silicon/silicon dioxide substrat structure schematic diagram of array, Fig. 3 is the silicon/silicon dioxide substrate knot for preparing sacrifice layer ZnO stripe arrays
Structure top view, wherein 1 be substrate silicon, 2 silicon face silicon dioxide films, 3 be ZnO layer；And by magnetron sputtering technique in print
One layer of 20nm-500nm ZnO of upper growth, will then grown ZnO print lift-off techniques and be made has sacrifice layer ZnO bar shapeds
The silicon/silicon dioxide print of array, graphical rear adjacent bar ZnO gap widths are 1 μm, ZnO stripe arrays zone length 100
μm, 5 μm of ZnO stripe arrays peak width.
Step S2：One layer is coated on the silicon/silicon dioxide print with sacrifice layer ZnO stripe arrays using spin coating proceeding
Thick photoresist, etches the thick photoresist layer containing pores array using photoetching technique, forms thick photoresist thickness degree for 1 μ
M, thick photoresist covering channel region length is 1 μm, and thick photoresist covering channel region width is 5 μm.Fig. 4 contains raceway groove to prepare
The silicon/silicon dioxide substrat structure schematic diagram of region thick photoresist layer, Fig. 5 for prepare the silicon of the layer of thick photoresist containing channel region/
Silicon dioxide substrates structure top view, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 3 be ZnO layer, and 4 be thick photoetching
Glue；Finally, the ZnO strip arrays on print are fallen with 4mol/L hydrochloric acid solution erosion removal, will be formed to contain on print and received
Rice noodles shape channel pore array photoresist, Fig. 6 illustrates to prepare the silicon/silicon dioxide substrat structure of the duct of wire containing nanometer photoresist
Figure, Fig. 7 is prepares the silicon/silicon dioxide substrat structure top view of the duct of wire containing nanometer photoresist, wherein 1 is substrate silicon, 2 are
Silicon face silicon dioxide film, 4 be thick photoresist, and 5 be nanometer wire channel pore array.
Step S3：First the chlorobenzene solution of organic semiconductor precursor aqueous solution such as pentacene or PEDOT/PSS is dropped in containing receiving
On the silicon/silicon dioxide print of rice noodles shape pores array thick photoresist, solution is set to penetrate into thickness using capillary percolation technology
In photoresist pores array, then using 1000rpm rotating speeds organic semiconductor is spun to be coated with the silicon of organic semiconductor array/
On silicon dioxide substrates print, and 0.5 h is heat-treated under 80 DEG C of temperature conditionss, i.e., one layer is formed on print and is received containing organic
The organic semiconductor layer of rice line array, Fig. 8 has silicon/titanium dioxide of the organic semiconductor layer containing organic nano-wire array to prepare
Silicon substrate structure schematic diagram, Fig. 9 contains the silicon/silicon dioxide substrat structure of the organic semiconductor layer of organic nano-wire array for preparation
Top view, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist layer, and 6 be organic semiconductor nanowires battle array
Row, 7 organic semiconductor layer to coat.
Step S4：It is being prepared for using on the silicon/silicon dioxide substrate print of the organic semiconductor layer containing organic nano wire
Pattern mask covering evaporation process formation Cr/Au clad metal electrodes, respectively as organic semiconductor nanowires arrays of conductive
Source electrode, the drain and gate of channel thin-film transistor；Wherein source electrode, drain and gate area be 300 μm of 200 μ m, source electrode with
The spacing that drains is 10 μm；Figure 10 is to be prepared for the silicon/silicon dioxide after the organic semiconductor layer containing organic nano wire and plated electrode
Substrat structure schematic diagram, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist layer, and 6 be organic semiconductor
Nano-wire array, 7 organic semiconductor layer to coat, 8 be source electrode, and 9 be drain electrode, and 10 be gate electrode.
Embodiment 2
Step S1：The silicon/silicon dioxide substrate that 1cm × 1cm sizes, oxidated layer thickness are 150nm is taken, Fig. 1 is silicon/dioxy
Silicon substrate structural representation, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film.By the silicon/silicon dioxide substrate dense
Sulfuric acid/a small amount of hydrogen peroxide solution high temperature cleaning 30min, and will be coated using spin coating proceeding in silicon/silicon dioxide substrate surface
One layer of photoresist, bar shaped photoresist array is etched using electron beam lithography photoetching technique, and Fig. 2 is to prepare sacrifice layer ZnO bar shapeds
The silicon/silicon dioxide substrat structure schematic diagram of array, Fig. 3 is the silicon/silicon dioxide substrate knot for preparing sacrifice layer ZnO stripe arrays
Structure top view, wherein 1 be substrate silicon, 2 silicon face silicon dioxide films, 3 be ZnO layer；And by magnetron sputtering technique in print
One layer of 300nm ZnO of upper growth, will then grown ZnO print lift-off techniques and be made has sacrifice layer ZnO stripe arrays
Silicon/silicon dioxide print, it is graphical after adjacent bar ZnO gap widths be 1.5 μm, the μ of ZnO stripe arrays zone length 100
30 μm of m, ZnO stripe array peak width.
Step S2：One layer is coated on the silicon/silicon dioxide print with sacrifice layer ZnO stripe arrays using spin coating proceeding
Thick photoresist, etches the thick photoresist layer containing pores array using photoetching technique, forms thick photoresist thickness degree for 5 μ
M, thick photoresist covering channel region length is 10 μm, and thick photoresist covering channel region width is 30 μm.Fig. 4 contains ditch to prepare
The silicon/silicon dioxide substrat structure schematic diagram of road region thick photoresist layer, Fig. 5 is the preparation layer of thick photoresist containing channel region
Silicon/silicon dioxide substrat structure top view, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 3 be ZnO layer, and 4 be thick light
Photoresist；Finally, the ZnO strip arrays on print are fallen with 5mol/L hydrochloric acid solution erosion removal, will be formed and contained on print
Nanometer wire channel pore array photoresist, Fig. 6 illustrates to prepare the silicon/silicon dioxide substrat structure of the duct of wire containing nanometer photoresist
Figure, Fig. 7 is prepares the silicon/silicon dioxide substrat structure top view of the duct of wire containing nanometer photoresist, wherein 1 is substrate silicon, 2 are
Silicon face silicon dioxide film, 4 be thick photoresist, and 5 be nanometer wire channel pore array.
Step S3：First the chlorobenzene solution of organic semiconductor precursor aqueous solution such as pentacene or PEDOT/PSS is dropped in containing receiving
On the silicon/silicon dioxide print of rice noodles shape pores array thick photoresist, solution is set to penetrate into thickness using capillary percolation technology
In photoresist pores array, then using 2000rpm rotating speeds organic semiconductor is spun to be coated with the silicon of organic semiconductor array/
On silicon dioxide substrates print, and 2.0h is heat-treated under 100 DEG C of temperature conditionss, i.e., one layer is formed on print and is received containing organic
The organic semiconductor layer of rice line array, Fig. 8 has silicon/titanium dioxide of the organic semiconductor layer containing organic nano-wire array to prepare
Silicon substrate structure schematic diagram, Fig. 9 contains the silicon/silicon dioxide substrat structure of the organic semiconductor layer of organic nano-wire array for preparation
Top view, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist layer, and 6 be organic semiconductor nanowires battle array
Row, 7 organic semiconductor layer to coat.
Step S4：It is being prepared for using on the silicon/silicon dioxide substrate print of the organic semiconductor layer containing organic nano wire
Pattern mask covering evaporation process formation Cr/Au clad metal electrodes, respectively as organic semiconductor nanowires arrays of conductive
Source electrode, the drain and gate of channel thin-film transistor；Wherein source electrode, drain and gate area be 300 μm of 200 μ m, source electrode with
The spacing that drains is 30 μm；Figure 10 is to be prepared for the silicon/silicon dioxide after the organic semiconductor layer containing organic nano wire and plated electrode
Substrat structure schematic diagram, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist layer, and 6 be organic semiconductor
Nano-wire array, 7 organic semiconductor layer to coat, 8 be source electrode, and 9 be drain electrode, and 10 be gate electrode.
Embodiment 3
Step S1：The silicon/silicon dioxide substrate that 1cm × 1cm sizes, oxidated layer thickness are 300nm is taken, Fig. 1 is silicon/dioxy
Silicon substrate structural representation, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film.By the silicon/silicon dioxide substrate dense
Sulfuric acid/a small amount of hydrogen peroxide solution high temperature cleaning 30min, and will be coated using spin coating proceeding in silicon/silicon dioxide substrate surface
One layer of photoresist, bar shaped photoresist array is etched using electron beam lithography photoetching technique, and Fig. 2 is to prepare sacrifice layer ZnO bar shapeds
The silicon/silicon dioxide substrat structure schematic diagram of array, Fig. 3 is the silicon/silicon dioxide substrate knot for preparing sacrifice layer ZnO stripe arrays
Structure top view, wherein 1 be substrate silicon, 2 silicon face silicon dioxide films, 3 be ZnO layer；And by magnetron sputtering technique in print
One layer of 500nm ZnO of upper growth, will then grown ZnO print lift-off techniques and be made has sacrifice layer ZnO stripe arrays
Silicon/silicon dioxide print, it is graphical after adjacent bar ZnO gap widths be 2 μm, 100 μm of ZnO stripe arrays zone length,
50 μm of ZnO stripe arrays peak width.
Step S2：One layer is coated on the silicon/silicon dioxide print with sacrifice layer ZnO stripe arrays using spin coating proceeding
Thick photoresist, etches the thick photoresist layer containing pores array using photoetching technique, forms thick photoresist thickness degree for 10 μ
M, thick photoresist covering channel region length is 20 μm, and thick photoresist covering channel region width is 50 μm.Fig. 4 contains ditch to prepare
The silicon/silicon dioxide substrat structure schematic diagram of road region thick photoresist layer, Fig. 5 is the preparation layer of thick photoresist containing channel region
Silicon/silicon dioxide substrat structure top view, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 3 be ZnO layer, and 4 be thick light
Photoresist；Finally, the ZnO strip arrays on print are fallen with 6mol/L hydrochloric acid solution erosion removal, will be formed and contained on print
Nanometer wire channel pore array photoresist, Fig. 6 illustrates to prepare the silicon/silicon dioxide substrat structure of the duct of wire containing nanometer photoresist
Figure, Fig. 7 is prepares the silicon/silicon dioxide substrat structure top view of the duct of wire containing nanometer photoresist, wherein 1 is substrate silicon, 2 are
Silicon face silicon dioxide film, 4 be thick photoresist, and 5 be nanometer wire channel pore array.
Step S3：First the chlorobenzene solution of organic semiconductor precursor aqueous solution such as pentacene or PEDOT/PSS is dropped in containing receiving
On the silicon/silicon dioxide print of rice noodles shape pores array thick photoresist, solution is set to penetrate into thickness using capillary percolation technology
In photoresist pores array, then using 3000rpm rotating speeds organic semiconductor is spun to be coated with the silicon of organic semiconductor array/
On silicon dioxide substrates print, and 3.0h is heat-treated under 150 DEG C of temperature conditionss, i.e., one layer is formed on print and is received containing organic
The organic semiconductor layer of rice line array, Fig. 8 has silicon/titanium dioxide of the organic semiconductor layer containing organic nano-wire array to prepare
Silicon substrate structure schematic diagram, Fig. 9 contains the silicon/silicon dioxide substrat structure of the organic semiconductor layer of organic nano-wire array for preparation
Top view, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist layer, and 6 be organic semiconductor nanowires battle array
Row, 7 organic semiconductor layer to coat.
Step S4：It is being prepared for using on the silicon/silicon dioxide substrate print of the organic semiconductor layer containing organic nano wire
Pattern mask covering evaporation process formation Cr/Au clad metal electrodes, respectively as organic semiconductor nanowires arrays of conductive
Source electrode, the drain and gate of channel thin-film transistor；Wherein source electrode, drain and gate area be 300 μm of 200 μ m, source electrode with
The spacing that drains is 50 μm；Figure 10 is to be prepared for the silicon/silicon dioxide after the organic semiconductor layer containing organic nano wire and plated electrode
Substrat structure schematic diagram, wherein 1 is substrate silicon, 2 be silicon face silicon dioxide film, and 4 be thick photoresist layer, and 6 be organic semiconductor
Nano-wire array, 7 organic semiconductor layer to coat, 8 be source electrode, and 9 be drain electrode, and 10 be gate electrode.
Above is presently preferred embodiments of the present invention, all changes made according to technical solution of the present invention, produced function is made
During with scope without departing from technical solution of the present invention, protection scope of the present invention is belonged to.
Claims (5)
1. a kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method, it is characterised in that：Utilize lift-
Off technologies, spin-coating film technology and capillary percolation technology, on a silicon/silicon dioxide substrate, are sequentially prepared
Go out sacrifice layer ZnO stripe arrays, the photoresist layer of the channel pore array of wire containing nanometer and containing organic nano-wire array organic half
Conductor layer, and metal electrode is formed respectively in organic semiconductor layer surface and substrate back containing organic nano-wire array,
And corresponding source electrode, drain and gate are drawn, so as to complete organic semiconductor nanowires arrays of conductive channel thin-film transistor
Prepare；
It is further comprising the steps of：
Step S1：HIGH TEMPERATURE PURGE is carried out to the silicon/silicon dioxide substrate using sulfuric acid/hydrogen peroxide solution；Using spin coating proceeding
One layer of photoresist is coated in the silicon/silicon dioxide substrate surface；Bar shaped photoresist is etched using electron beam lithography photoetching technique
Array；One ZnO layer is grown in the bar shaped photoresist array surface by magnetron sputtering technique, and uses lift-off techniques
Technology prepares sacrifice layer ZnO stripe arrays；
Step S2：One thickness photoresist is coated on the sacrifice layer ZnO stripe arrays using spin coating proceeding, carved using electron beam
Erosion photoetching technique etches the thick photoresist layer containing pores array, and with sacrifice layer ZnO bar shapeds described in acid solution erosion removal
The ZnO stripe arrays of uncoated thick photoresist on array, to form mutually isolated in the channel region covered with thick photoresist layer
Nanometer wire channel pore array photoresist layer；
Step S3：Drop is covered with machine semiconductor precursor solution on the silicon/silicon dioxide print surface obtained through the step S2,
And cause organic semiconductor precursor aqueous solution to penetrate into the nanometer wire channel pore array photoresist using capillary percolation technology
In the pores array of layer, then using organic semiconductor spin coating proceeding and heat treatment for solidification, prepare having containing organic nano-wire array
Machine semiconductor layer；
Step S4：Evaporation process technology is covered respectively in the organic semiconductor layer containing organic nano-wire array using pattern mask
Surface and silicon/silicon dioxide substrate back formation Cr/Au clad metal electrodes, and received respectively to should be used as organic semiconductor
Source electrode, the drain and gate of nanowire arrays conducting channel thin film transistor (TFT).
2. a kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method according to claim 1,
It is characterized in that：In the step S1, the silicon/silicon dioxide Substrate Area is 1cm × 1cm；The silicon dioxide layer is made
For the insulating barrier of thin film transistor (TFT), and thickness is 30nm to 300nm；ZnO layer thickness is 20nm to 500nm；Single ZnO bar shapeds
1 μm to 5 μm of array-width；Adjacent single ZnO bar shapeds gap width is 1 μm to 2 μm；The μ of ZnO stripe arrays zone length 100
m；5 μm to 50 μm of ZnO stripe arrays peak width.
3. a kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method according to claim 1,
It is characterized in that：In the step S2, the thick photoresist is SU8 glue；The acid solution is dilute for 4mol/L's to 6mol/L
Hydrochloric acid solution；The thick photoresist thickness degree is 1 μm to 10 μm, and the channel region length of thick photoresist covering is 1 μm
To 20 μm, the channel region width of thick photoresist covering is 5 μm to 50 μm.
4. a kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method according to claim 1,
It is characterized in that：In the step S3, the organic semiconductor precursor solution includes pentacene or PEDOT/PSS chlorobenzene
Solution；The organic semiconductor spin coating proceeding revolution is 1000 rpm to 3000rpm；The temperature of the heat treatment is：80 DEG C extremely
150℃；The time of the heat treatment is：0.5 h to 3.0h；The organic semiconductor layer thickness is 5 nm to 30nm.
5. a kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method according to claim 1,
It is characterized in that：In the step S4, the pattern mask covering evaporation process technology is to be covered using patterned metal
Film covers sample surfaces, is then deposited in sample surfaces；The source electrode, the drain electrode and the gate area are 200 μ
M × 300 μm, and the source electrode and the drain electrode spacing are 10 μm to 50 μm.
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| CN1540649A (en) * | 2003-10-24 | 2004-10-27 | 周照耀 | Thin film material assembled by templet and preparation method |
| CN1707748A (en) * | 2005-04-20 | 2005-12-14 | 中山大学 | Method for producing silicon nano-line diode structual field emitting device |
| KR20080072981A (en) * | 2007-02-05 | 2008-08-08 | 연세대학교 산학협력단 | Fabrication method of thin film transistor using 1 dimensional nano-wire channel |
| CN101870453A (en) * | 2010-05-19 | 2010-10-27 | 中国科学院半导体研究所 | Manufacture method of semiconductor nano-pillar array structure |
| CN103539956A (en) * | 2013-10-10 | 2014-01-29 | 中国科学院上海技术物理研究所 | Preparation method of PVDF (polyvinylidene fluoride)-based organic ferroelectric polymer nanowire |
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| CN1540649A (en) * | 2003-10-24 | 2004-10-27 | 周照耀 | Thin film material assembled by templet and preparation method |
| CN1707748A (en) * | 2005-04-20 | 2005-12-14 | 中山大学 | Method for producing silicon nano-line diode structual field emitting device |
| KR20080072981A (en) * | 2007-02-05 | 2008-08-08 | 연세대학교 산학협력단 | Fabrication method of thin film transistor using 1 dimensional nano-wire channel |
| CN101870453A (en) * | 2010-05-19 | 2010-10-27 | 中国科学院半导体研究所 | Manufacture method of semiconductor nano-pillar array structure |
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