CN1707748A - Method for producing silicon nano-line diode structual field emitting device - Google Patents
Method for producing silicon nano-line diode structual field emitting device Download PDFInfo
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- CN1707748A CN1707748A CN 200510034259 CN200510034259A CN1707748A CN 1707748 A CN1707748 A CN 1707748A CN 200510034259 CN200510034259 CN 200510034259 CN 200510034259 A CN200510034259 A CN 200510034259A CN 1707748 A CN1707748 A CN 1707748A
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Abstract
The present invention discloses one kind of nanometer silicon line diode structure field emitting device making process, and the making process has combined preparing self-assembled nanometer silicon carbide crystal grain and hydrogen plasma itching to prepare erect ordered nanometer silicon line array. Nanometer silicon line diode structure field emitting device capable of emitting electrons under low grid voltage driving is made successfully. The making process needs no electron beam photoitching and thus has greatly lowered cost. The present invention is significant in the application of nanometer silicon line in the field of nanometer and micron photoelectronic device.
Description
Technical field
The present invention relates to a kind of manufacture method of diode structure feds, especially a kind of method of making silicon nanowire diode structure feds.
Background technology
The development of silica-based nano-micro structure device is an important topic of current vacuum microelectronic device research field, and accurate one dimension silicon nanowires has good photoelectric characteristic, is to be most likely in the recent period to receive one of new material that low-light electronic device applications field has breakthrough.At present, mainly contain following several method and can be used for the preparation of silicon nanowires: laser ablation method (laserablation), thermal evaporation (thermal evaporation), overcritical liquid phase method (supercritical fluid solution-phase), catalyst-free oxidation auxiliary law (catalyst free of oxide-assisted growth), mask plasma etching method (plasma etching with use of lithography masks).Preceding four kinds of silicon nanowires clusters that are generally unordered, lie low, twine mutually that method obtained, this brings difficulty for the making and the assembling of silicon nanowires opto-electronic device.For example, though existing researcher proves that the unordered silicon nanowires cluster that lies low has excellent electronic emission performance, there is not the researcher to produce the silicon nano-line diode structual field emitting device of energy electron gain emission so far as yet.Though and employing mask plasma etching method can obtain upright orderly silicon nanowire array, because process must adopt electron beam lithography, cost of manufacture is quite expensive.Therefore, develop a kind of method that need not to adopt electron beam lithography to make the nanometer mask and obtain upright orderly silicon nanowire array, important meaning is arranged receiving the application of low-light field of electronic devices promoting silicon nanowires.
Summary of the invention
The invention discloses a kind of self assembly preparation of based on silicon carbide nanocrystal and the method for hydrogen gas plasma etching, the upright orderly silicon nanowire array of preparation, and just successfully produce under low grid voltage drives can emitting electrons silicon nano-line diode structual field emitting device.
The present invention is a kind of method of making silicon nano-line diode structual field emitting device, it is characterized in that processing step is as follows:
On silicon chip, adopt coating process to deposit insulating thin layer and metal film layer successively; then evenly apply one deck photoresist at layer on surface of metal; and adopt photoetching technique on photoresist, to leave little circular hole; use etching technics successively erosion removal metal and insulating barrier in little circular hole of photoresist protection are not arranged; expose silicon face, form silicon-insulating barrier-metal diode grid pore structure.
The plasma self assembly of adopting the mist of methane and hydrogen on the silicon face in the diode grid hole in the above-mentioned steps is deposited the nanometer silicon carbide crystal grain of discrete distribution.
Silicon face in the hole of grid hole is a mask with nanometer silicon carbide crystal grain, adopts hydrogen gas plasma the silicon face that is not coated with nanometer silicon carbide crystal grain in the diode grid hole to be etched the silicon nanowire array of vertical arrangement in anisotropic mode.Adopt the purpose of hydrogen gas plasma to be: hydrogen gas plasma is very faint to the corrasion of metal, therefore the sample surfaces metal level can remain intact, simultaneously, hydrogen gas plasma can carry out etching to the silicon materials in the hole of grid hole, because there is the nanometer silicon carbide crystal grain of discrete distribution in the silicon materials surface, with these nanometer silicon carbide crystal grain is mask, carries out etching by the control hydrogen gas plasma in anisotropic mode, can produce the silicon nanowire array of vertical arrangement in the grid hole.
Prolong the processing time of hydrogen gas plasma to above-mentioned sample.Along with the prolongation of hydrogen gas plasma etch period, the silicon nanowires height increases, and nanometer silicon carbide crystal grain also is converted into amorphous silicon simultaneously.The little grid pore structure of silicon-insulating barrier-metal that is manufactured with silicon nanowire array (nanowire surface is coated with amorphous silicon layer) after the almanac step in the grid hole that is obtained just constitutes a band control grid feds.
A kind of method of making silicon nano-line diode structual field emitting device of the present invention, it need not to adopt electron beam lithography, saved cost greatly, use device that this method prepares still can be under low grid voltage drives just can emitting electrons, it has important meaning to the promotion silicon nanowires receiving the application of low-light field of electronic devices.
Description of drawings
The top that Fig. 1 (a) forms after for 30 minutes methane of experience and hydrogen gas mixture plasma treatment deposits the silicon nanowires HRTEM figure of nanocrystal;
Fig. 1 (b) is the HRTEM figure of nano wire top nanocrystal;
The silicon nanowires HRTEM figure that Fig. 1 (c) forms after for 1 hour methane of experience and hydrogen gas mixture plasma treatment;
Fig. 2 handles the analysis result of back diode structure feds for 1 hour methane of experience and hydrogen mixed gas bulk plasmon and 4 hours hydrogen gas plasmas, wherein:
Fig. 2 (a), Fig. 2 (b), Fig. 2 (c), Fig. 2 (d) are the SEM shape appearance figure;
Fig. 2 (e), Fig. 2 (f) by the HRTEM shape appearance figure of formation silicon nanowires;
Fig. 3 is silicon nano-line diode structual field emitting device field emission one a grid voltage performance diagram;
Illustration among Fig. 3 is the FN curve of silicon nano-line diode structual field emitting device field emission one grid voltage characteristic curve correspondence.
Embodiment
Come the present invention is done further detailed description below in conjunction with accompanying drawing and a specific embodiment.
1. adopt＜100〉monocrystalline silicon piece as substrate.
2. adopt Oxford Plus 80+ chemical gas-phase deposition system, deposition one layer thickness is the SiO of 0.4 μ m on silicon chip
2Film.The film preparation condition is as follows: process gas: SiH
4(40sccm), O
2(20sccm); Underlayer temperature: 350C; Microwave radio source power: 20W; Time: 10mins.
3. utilize SP-3 type magnetron sputtering coater, depositing SiO
2Deposition one layer thickness is crome metal (Cr) film of 0.2 μ m on the silicon chip of film.Chromium film sedimentary condition is as follows: sputtering power: 300W; Underlayer temperature: room temperature; Working vacuum degree: 5 * 10
-4Pa; Sputter gas: Ar (60sccm); Time: 20 minutes.
4. utilize Karl Suss R8 glue spreader at the silicon-insulating barrier-even spin coating last layer of metal three-decker substrate surface AZ 5200NJ positive photoresist, the gluing rotating speed is 4000rpm, and the time is 60 seconds, and the photoresist thickness that is obtained is about 0.5 μ m.
5. gluing sample is carried out the heat baking, baking temperature is 100 ℃, and the time is 60 seconds.
6. utilize Karl Suss MA45 mask aligner that sample is carried out 10 seconds uv-exposure, adopt micropore (diameter 5mm) domain mask plate in the exposure process as mask.Exposure mode is hard contact.
7. adopt AZ 300MIF developer solution that the gluing sample that exposes is developed, developing time is 25 seconds, and the back of developing forms little circular hole on the sample surfaces photoresist.
8. the sample that develops is carried out the heat baking, baking temperature is 100 ℃, and the time is 60 seconds.
9. with sample (ammonium ceric nitrate (15g)+4ml HClO in ammonium ceric nitrate that dilutes and perchloric acid mixed solution
4(4ml)+H
2O (100ml)) soaked 1.5 minutes the crome metal film in the little circular hole of erosion removal photoresist in; Take out washing, and dry up with nitrogen.
10. adopt magnetic to strengthen plasma etching machine (RlE), use CHF
3(21sccm) and Ar (7sccm) mixed gas plasma etching remove SiO in the micropore
2Film; Etching power is 250W, and the time is 15 minutes; Operating pressure is 2Pa.
Strengthen in plasma system (MPCVD) the sample preparation vacuum chamber 11. above-mentioned sample silicon slice placed is gone into microwave, vacuumize.
12. when vacuum degree arrives 1Pa, feed high (99.99%) methane (20sccm) and pure (99.99%) hydrogen (80sccm) mist in the sample preparation vacuum chamber, pressure is stabilized in 220Pa in the adjusting vacuum chamber, connects at sample-the 200V bias voltage.
13. utilize frequency microwave source forcing methane and hydrogen gas mixture to produce plasma, microwave radio power is 500W.Under the acting in conjunction of microwave and plasma, sample temperature continue to rise, and arrives after 5 minutes and is stabilized in 500 ℃.
14. handled sample under these conditions 1 hour; Suspend microwave excitation, stop ventilating methane, continue logical hydrogen (80sccm); Pressure is stabilized in 110Pa in the adjusting vacuum chamber, connects at sample-the 200V bias voltage.
15. utilize frequency microwave source forcing hydrogen to produce plasma, microwave radio power is 500W.Under the acting in conjunction of microwave and plasma, sample temperature continue to rise, and arrives after 2 minutes and is stabilized in 500 ℃.
16. handled sample under these conditions 4 hours, positioning is made the high-density silicon nano-wire array perpendicular to substrate surface in silicon-insulating barrier-metal diode grid pore structure, forms silicon nano-line diode structual field emitting device.
To the product of above-mentioned band control grid silicon nanowires feds manufacturing process different phase, we have adopted scanning electron microscopy (SEM), high resolution transmission electron microscopy (HRTEM) and X ray energy dispersion spectrum (EDX) to analyze.Fig. 1 (a) shows is HRTEM pattern after silicon face in the band control grid two-level structure has experienced 30 fens kind methane and hydrogen gas mixture plasma treatment, shows that it (highly is 70～80nm) that surface of silicon has formed the nano wire that the top deposits nanocrystal.Obtaining the crystal grain spacing of lattice from the HRTEM image measurement of the nanocrystal shown in Fig. 1 (b) is 0.313nm, coincide with the spacing of lattice of SiC (200) face, proves that nanocrystal is a carborundum.Fig. 1 (c) shows is HRTEM pattern after silicon face has experienced 1 hour methane and hydrogen gas mixture plasma treatment, the spacing of lattice that measures nano wire from figure is 0.218nm, coincide with the spacing of lattice of Si (100) face, prove that it is a silicon nanowires.Fig. 2 shows is that 1 hour methane of experience and hydrogen mixed gas bulk plasmon and 4 hours hydrogen gas plasmas are handled the SEM image of back band control grid feds and the HRTEM analysis result of the silicon nanowires that forms.Sem analysis (Fig. 2 (a) is to 2 (d)) result shows the high-density silicon nano wire of formation regular arrangement in location in the grid hole, highly is 1 μ m.HRTEM analyzes (Fig. 2 (e) and 2 (f)) and proves that nano wire is a monocrystalline silicon nano line, and nanowire diameter is between 20～40nm.EDX analyzes (illustration among Fig. 2 (f)) and proves that surface of silicon nanowires and top are coated with one deck amorphous silicon layer.Comparison diagram 1 (a) and Fig. 2 (f), as can be seen, hydrogen gas plasma is handled can change into amorphous silicon fully with carborundum.Use field-causing electron emission comprehensive tester to analyze the field emission characteristic of band control grid silicon nanowires feds, Fig. 3 is for measuring the current density-grid voltage characteristic curve of gained, and the illustration among Fig. 3 has provided corresponding F-N curve.Table with test results oolemma control grid silicon nanowires feds among Fig. 3 has good field emission characteristic.When grid voltage was 50V, device can obtain the emission current of 0.1 μ A.When device grids voltage rises to 225V, the emission that anode can be collected is up to 3.4mA/cm
2
Present embodiment is whole manufacturing process of band control grid silicon nanowires feds, and wherein the formation of silicon nanowires is based on the self assembly preparation of nanometer silicon carbide crystal grain and the hydrogen gas plasma know-why to the anisotropic etching of silicon materials.And also proved by hydrogen gas plasma and handled, carborundum can have been changed into amorphous silicon.
Claims (7)
1. method of making silicon nano-line diode structual field emitting device is characterized in that processing step is as follows:
(A), on silicon chip, adopt coating process to deposit insulating thin layer and metal film layer successively, on silicon chip, insulating thin layer and metal film layer, evenly apply one deck photoresist, and adopt photoetching technique on photoresist, to leave little circular hole, use etching technics successively erosion removal metal and insulating barrier in little circular hole of photoresist protection are not arranged, expose silicon chip surface;
(B), the plasma self assembly of adopting the mist of methane and hydrogen on the silicon face in the diode grid hole in (A) is deposited the nanometer silicon carbide crystal grain of discrete distribution;
(C), the silicon face in the hole of grid hole, with nanometer silicon carbide crystal grain is mask, adopts hydrogen gas plasma the silicon face that is not coated with nanometer silicon carbide crystal grain in the diode grid hole in the step (B) to be etched the silicon nanowire array of vertical arrangement in anisotropic mode.
2. a kind of method of making silicon nano-line diode structual field emitting device as claimed in claim 1 is characterized in that: described SiO
2Insulating thin layer is with＜100〉monocrystalline silicon piece is as substrate, and employing Oxford Plus 80+ chemical gas-phase deposition system prepares SiO
2Film thickness is 0.4 μ m, and the film preparation condition is as follows:
The SiH of process gas: 40sccm
4, 20sccm O
2Underlayer temperature: 350 ℃; Microwave radio source power: 20W; Time: 10mins.
3. a kind of method of making silicon nano-line diode structual field emitting device as claimed in claim 1 is characterized in that: preparing described metal film layer is to deposit SiO
2Deposition one layer thickness is the crome metal film of 0.2 μ m on the silicon chip of film, and chromium film sedimentary condition is as follows: sputtering power: 300W; Underlayer temperature: room temperature; Working vacuum degree: 5 * 10
-4Pa; The Ar of sputter gas: 60sccm; Time: 20 minutes.
4. a kind of method of making silicon nano-line diode structual field emitting device as claimed in claim 1, it is characterized in that: at the described silicon-insulating barrier-even spin coating last layer of metal three-decker substrate surface AZ 5200NJ positive photoresist, the gluing rotating speed is 4000rpm, and the time is 60 seconds.
5. a kind of method of making silicon nano-line diode structual field emitting device as claimed in claim 1 is characterized in that: described etch process is to strengthen the CHF that uses 21sccm on the plasma etching machine at magnetic
3Remove SiO in the micropore with the mixed gas plasma etching of the Ar of 7sccm
2Film, etching power are 250W, and the time is 15 minutes, and operating pressure is 2Pa.
6. a kind of method of making silicon nano-line diode structual field emitting device as claimed in claim 1, it is characterized in that: the technology of the nanometer silicon carbide crystal grain of self assembly deposition discrete distribution is in the described step (B): when vacuum degree is 1Pa, methane that feed purity and be 99.99% in the sample preparation vacuum chamber, flow is 20sccm and purity are 99.99%, flow is the hydrogen gas mixture of 80sccm, pressure is stabilized in 220Pa in the adjusting vacuum chamber, connects-the 200V bias voltage; Utilize power to produce plasma, make temperature continue to rise, arrive after 5 minutes and be stabilized in 500 ℃, suspend microwave excitation after 1 hour, stop ventilating methane for the frequency microwave source forcing methane of 500W and hydrogen gas mixture.
7. as claim 1 or 6 described a kind of methods of making silicon nano-line diode structual field emitting device, it is characterized in that: the technology that is not coated with the silicon of nanometer silicon carbide crystal grain in the described step (C) in the etching diode grid hole is: after the PROCESS FOR TREATMENT of the nanometer silicon carbide crystal grain of self assembly deposition discrete distribution finishes in step (B), continue the hydrogen of logical 80sccm on the surface, pressure is stabilized in 110Pa in the adjusting vacuum chamber, connects-the 200V bias voltage; And handled 4 hours, positioning is made the high-density silicon nano-wire array perpendicular to substrate surface in silicon-insulating barrier-metal diode grid pore structure, forms silicon nano-line diode structual field emitting device.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047819A (en) * | 2015-06-23 | 2015-11-11 | 福州大学 | Organic semiconductor nanowire array conducting channel thin film transistor manufacturing method |
| CN106158551A (en) * | 2016-07-08 | 2016-11-23 | 中山大学 | Nanometer line cold-cathode electron source array of autoregistration focusing structure and preparation method thereof |
| CN110419093A (en) * | 2017-04-07 | 2019-11-05 | 应用材料公司 | Improve the processing method of film roughness by improving nucleation/adherency of silica |
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|---|---|---|---|---|
| JP2000164921A (en) * | 1998-11-26 | 2000-06-16 | Mitsubishi Materials Corp | Semiconductor light emitting material, manufacture thereof, and light emitting element using the material |
| US7335603B2 (en) * | 2000-02-07 | 2008-02-26 | Vladimir Mancevski | System and method for fabricating logic devices comprising carbon nanotube transistors |
| TW529188B (en) * | 2002-04-26 | 2003-04-21 | Univ Nat Taiwan | Metal oxide silicon structure with increased illumination efficiency by using nanometer structure |
| GB2389230A (en) * | 2002-05-28 | 2003-12-03 | Univ Nat Taiwan | Nanoparticle light emitting device (LED) |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047819A (en) * | 2015-06-23 | 2015-11-11 | 福州大学 | Organic semiconductor nanowire array conducting channel thin film transistor manufacturing method |
| CN105047819B (en) * | 2015-06-23 | 2017-09-22 | 福州大学 | A kind of organic semiconductor nanowires arrays of conductive channel thin-film transistor preparation method |
| CN106158551A (en) * | 2016-07-08 | 2016-11-23 | 中山大学 | Nanometer line cold-cathode electron source array of autoregistration focusing structure and preparation method thereof |
| CN106158551B (en) * | 2016-07-08 | 2017-11-21 | 中山大学 | Nanometer line cold-cathode electron source array of autoregistration focusing structure and preparation method thereof |
| CN110419093A (en) * | 2017-04-07 | 2019-11-05 | 应用材料公司 | Improve the processing method of film roughness by improving nucleation/adherency of silica |
| CN110419093B (en) * | 2017-04-07 | 2023-12-01 | 应用材料公司 | Treatment method for improving film roughness by improving nucleation/adhesion of silicon oxide |
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