CN105044860A - Wafer processing technique for vertically integrating PLC waveguide with infrared receiver - Google Patents
Wafer processing technique for vertically integrating PLC waveguide with infrared receiver Download PDFInfo
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- CN105044860A CN105044860A CN201510353426.XA CN201510353426A CN105044860A CN 105044860 A CN105044860 A CN 105044860A CN 201510353426 A CN201510353426 A CN 201510353426A CN 105044860 A CN105044860 A CN 105044860A
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
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- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a wafer processing technique for vertically integrating a PLC waveguide with an infrared receiver. The technique comprises steps of: processing a groove on the surface of a covering layer, close to an output end, of a PLC waveguide; depositing a photosensitive layer on the bottom of the groove; depositing a protective layer on the surface of the photosensitive layer and the surface of the covering layer and processing a groove on the surface of the protective layer on each of both ends of the bottom of the groove; depositing a metallic layer on the bottom of the groove and the surface of the protective layer and processing the metallic layer to be an electrode metallic lead; and depositing another protective layer on the electrode metallic lead and the surface of the protective layer and processing a wiring port. The technique achieves tight integration that the output end of the waveguide and a photoreceptor based on a germanium compound crystal are coupled on the wafer and a waveguide core and an infrared photoreceptor are vertically coupled such that maximum signal current output of the photoreceptor is easy to acquire. The processing technique is simple and low in production cost, and prevents consumption of a plenty of labor force.
Description
Technical field
The present invention relates to the wafer processing technology of a kind of PLC waveguide and infrared receptacle Vertical collection, belong to waveguide device preparation field.
Background technology
Along with the application of PLC planar waveguide chip device is from wide area network to the expansion of intercity net and Access Network, increasing optical module needs with PLC chip integrated with the high integration realizing application module and high-performance.Less closeer index request can require to realize in some modules, and these modules are as TOSA (light launches sub-Knockdown block) and ROSA (the sub-Knockdown block of light-receiving).Past in the application module of wide area network, laser instrument, waveguide chip, optical receiver usually be separation assembly.In the prior art the optical device of separation being assembled into method together, is generally reflect light to photodiode by a reflective mirror to get on, and needs corresponding aligning and encapsulation technology.At present under the trend effect of 100G data network requirement, the transmitting of inserting in the intercity network equipment accepts module and is required to do less.Discrete device is fitted together and is difficult to meet telecom dealer to undersized requirement, and the method is also a kind of job operation of costliness.Because module is encapsulated by reflective mirror, photodiode and waveguide device to form, volume is difficult to reduce again.
Summary of the invention
Have for optical module of the prior art and PLC chip integration module that processing cost is high, complicated operation, and integration module device volume is large, existing application requirement cannot be adapted to, the object of the invention is to be to provide a kind of simple to operate, cost is low, can realize the closely integrated wafer processing technology of infrared light sensing device and PLC waveguide.
In order to realize technical purpose of the present invention, the invention provides the wafer processing technology of a kind of PLC waveguide and infrared receptacle Vertical collection, comprising the following steps:
(1) at the cover surface machined grooves I of PLC waveguide near output terminal, groove I is positioned at directly over waveguide core;
(2) at groove I bottom deposit photoinduction layer;
(3) at photoinduction layer and cover surface Deposition of protective layer I, and the protective seam I surface at two ends respectively processes a groove II bottom groove I;
(4) bottom groove II and protective seam I surface deposition metal level, and metal level is processed into electrode metal lead-in wire;
(5) at electrode metal lead-in wire and protective seam I surface deposition protective seam II, and connection jaws is processed.
Technical scheme of the present invention is by being positioned at machined grooves directly over waveguide core at waveguide output terminal overlayer, and deposit Germanium compound crystal photoinduction layer, the photoreceptor realized based on germanium compound crystal and waveguide is vertical coupled, intensive one-tenth is tightened at wafer, have the advantages that volume is little, can provide convenience with the application on ROSA (the sub-Knockdown block of light-receiving) for arrayed waveguide gratings, and easy and simple to handle, avoid in prior art in the packaging technology of rear end, consume a large amount of labour (such as coupling centering of single optical device in packaging technology).
The wafer processing technology of PLC waveguide of the present invention and infrared receptacle Vertical collection also comprises following preferred version:
In preferred scheme, PLC waveguide substrate thickness is 15 ~ 20 microns, and cover thickness is 15 ~ 20 microns, and waveguide core width is 5 ~ 8 microns, and thickness is 5 ~ 7 microns.
In preferred scheme, PLC waveguide has at least 8 output channels (i.e. waveguide core number).8,16,40,100 or more multi output passage can be had.
It is 1 ~ 2 micron with the vertical range of waveguide core bottom preferred scheme further groove I.The vertical coupled distance of photoinduction layer and waveguide can be controlled by the degree of depth of adjusting grooves I, be conducive to obtaining best light signal output effect.
Parallel with waveguide bottom preferred scheme further groove I, groove I bottom width is 25 ~ 35 microns, and length is 100 ~ 150 microns.By regulating the length of the groove I of processing, the length of photoinduction layer along waveguide parallel direction can be controlled in 100 ~ 150 micrometer ranges.Groove I most preferably is inverted trapezoidal shape groove.
In preferred scheme, photoinduction layer thickness is 0.1 ~ 1 micron.
In preferred scheme, photoinduction layer is made up of infra-red sensitive material germanium compound crystal.The present invention processes low pressure chemical vapor deposition by highly purified germanium compound crystal, and the photoinduction layer bandwidth energy that germanium compound crystal makes is less than 0.77 electron-volt.
In preferred scheme, protective seam I thickness is 0.5 ~ 1 micron.
In preferred scheme, protective seam II thickness is 0.5 ~ 1 micron.
More preferably in scheme, protective seam I and protective seam II is selected from SiO independently of one another
2or SiN material.
In preferred scheme, metal level is made up of aluminium.
More preferably in scheme, metal layer thickness is 2000 ~ 2500 dusts.
Photoinduction layer for exposing bottom preferred scheme further groove II.Metal level is deposited directly on photoinduction layer, is reprocessed into the plain conductor of photoinduction layer.
In preferred scheme by photoetching process and dry corrosion method at PLC waveguide machined grooves I on the overlayer of output terminal.
In preferred scheme, by photoetching and etching process, the two ends protective seam I surface bottom groove I respectively processes a groove II.
By photoetching and etching process processing connection jaws in the solution of the present invention, so that the laminating realizing COG or SOG and chip and glass encapsulates.
Each processing groove I directly over each Luciola substriata core in the solution of the present invention, and process infra-red sensitive material germanium compound crystal as optical inductor, monitor the light intensity transmitted in waveguide like this.
The present invention can regulate the vertical coupled distance of infra-red sensitive material germanium compound crystal and waveguide core and and the length of optical inductor to obtain the optimum coupling effect of waveguide core and optical inductor, thus the peak signal electric current obtaining optical inductor exports, by amplify and the last signal of array analog to digital conversion be export in a digital manner, as shown in Fig. 2 (in figure, L represents length, and d represents height).
Beneficial effect of the present invention: it is closely integrated that waveguide and the infrared light inductor process photoreceptor achieved on same wafer based on waveguide output terminal and germanium compound crystal are coupling on wafer by method of the present invention, and waveguide core and infrared light inductor vertical coupled, be easy to obtain export from the peak signal electric current of optical inductor.Waveguide of the present invention and infrared light inductor closely integrated, volume is little, can provide convenience for arrayed waveguide gratings with the application on ROSA (the sub-Knockdown block of light-receiving).Processing technology of the present invention is simple, and avoid a large amount of labour to consume, production cost is low.
Accompanying drawing explanation
[Fig. 1] is process chart of the present invention;
The complete configuration diagram of the PLC waveguide that [Fig. 2] is prepared for the present invention and infrared receptacle Vertical collection device;
[Fig. 3] turns electric circuit diagram for the light of the PLC waveguide that comprises the present invention and prepare and infrared receptacle Vertical collection device waveguide device;
Wherein, 1 is substrate layer, and 2 is waveguide core, 3 overlayers, and 4 is groove I, and 5 is photoinduction layer, and 6 is protective seam I, and 7 is groove II, and 8 is electrode metal lead-in wire, and 9 is protective seam II, and 10 is PCL waveguide, and 11 is output device, and 12 is AMP.
Embodiment
Following examples are intended to further illustrate content of the present invention, instead of the protection domain of restriction the claims in the present invention.
Embodiment 1
Starting material: PLC wafer; Starting material for deposited substrate layer in substrate, waveguide core layer and tectal PLC wafer (as shown in a in Fig. 1); Substrate thickness is about 18 microns, and cover thickness is about 19 microns, and waveguide core width is about 6 microns, and thickness is about 6 microns.PLC wafer has 16 output channels.
(1) inverted trapezoidal groove (as shown in b in Fig. 1) is etched on the cover layer by photo-etching processes and dry etching, the degree of depth of groove is about 12 microns, bottom portion of groove width about 30 microns, length is about 120 microns, and cover thickness remaining in waveguide core layer is about 1 micron..Photo-etching processes include paving photoresist and exposure with development formed figure again by dry etching Graphic transitions to overlayer.
(2) at inverted trapezoidal groove bottom deposit photoinduction layer (polycrystal germanium), thickness about 0.6 micron, width and length and bottom portion of groove basically identical.Figure (as shown in c in Fig. 1) is formed by photo-etching processes and dry etching.
(3) layer protective layer is deposited in cover surface (comprising groove surfaces); thickness is about 0.6 micron; material is silicon dioxide; again by photo-etching processes and etched recesses (as shown in d in Fig. 1) on the two ends protective seam be dry-etched in bottom trapezoidal groove, the Pocket Machining degree of depth is until expose photoinduction layer.
(4) deposit one deck aluminium when electric shock plain conductor at protective layer, thickness is about 2200 dusts, forms figure (as shown in e in Fig. 1) by photo-etching processes with dry etching.
(5) on aluminium lamination, depositing layer protective layer, thickness is about 0.6 micron, and material is silicon dioxide; Breach is exposed on the protection layer to facilitate external electrode (as in Fig. 1 as described in f) with dry etching by photo-etching processes.
Integrated products as shown in Figure 2, what as can be seen from Figure 2 waveguide and the infrared light inductor process photoreceptor achieved on same wafer based on waveguide output terminal and germanium compound crystal were coupling on wafer is closely integrated, and waveguide core and infrared light inductor vertical coupled.
Claims (13)
1. a wafer processing technology for PLC waveguide and infrared receptacle Vertical collection, is characterized in that, comprise the following steps:
(1) at the cover surface machined grooves I of PLC waveguide near output terminal, groove I is positioned at directly over waveguide core;
(2) at groove I bottom deposit photoinduction layer;
(3) at photoinduction layer and cover surface Deposition of protective layer I, and the protective seam I surface at two ends respectively processes a groove II bottom groove I;
(4) bottom groove II and protective seam I surface deposition metal level, and metal level is processed into electrode metal lead-in wire;
(5) at electrode metal lead-in wire and protective seam I surface deposition protective seam II, and connection jaws is processed.
2. technique according to claim 1, is characterized in that, described PLC waveguide substrate thickness is 15 ~ 20 microns, and cover thickness is 15 ~ 20 microns, and waveguide core width is 5 ~ 8 microns, and thickness is 5 ~ 7 microns.
3. technique according to claim 1, is characterized in that, described PLC waveguide has at least 8 output channels.
4. technique according to claim 1, is characterized in that, is 1 ~ 2 micron with the vertical range of waveguide core bottom described groove I.
5. technique according to claim 1, is characterized in that, parallel with waveguide bottom described groove I, and groove I bottom width is 25 ~ 35 microns, and length is 100 ~ 150 microns.
6. technique according to claim 1, is characterized in that, described photoinduction layer thickness is 0.1 ~ 1 micron.
7. the technique according to claim 1 or 6, is characterized in that, described photoinduction layer is made up of infra-red sensitive material germanium compound crystal.
8. technique according to claim 1, is characterized in that, described protective seam I thickness is 0.5 ~ 1 micron.
9. technique according to claim 1, is characterized in that, described protective seam II thickness is 0.5 ~ 1 micron.
10. the technique according to claim 1,8 or 9, is characterized in that, described protective seam I and protective seam II is selected from SiO independently of one another
2or SiN material.
11. techniques according to claim 1, is characterized in that, described metal level is made up of aluminium.
12. techniques according to claim 1 or 11, it is characterized in that, described metal layer thickness is 2000 ~ 2500 dusts.
13. techniques according to claim 1, is characterized in that, the photoinduction layer for exposing bottom described groove II.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510353426.XA CN105044860B (en) | 2015-06-24 | 2015-06-24 | A kind of PLC waveguide and the wafer processing technique of infrared accepter Vertical collection |
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| CN201510353426.XA CN105044860B (en) | 2015-06-24 | 2015-06-24 | A kind of PLC waveguide and the wafer processing technique of infrared accepter Vertical collection |
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| CN105044860A true CN105044860A (en) | 2015-11-11 |
| CN105044860B CN105044860B (en) | 2016-08-24 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0697187A (en) * | 1992-09-14 | 1994-04-08 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| CN1094817A (en) * | 1993-03-19 | 1994-11-09 | 阿克佐诺贝尔公司 | Semiconductor element and mutually integrated method and the electric-optical appliance of polymeric optical waveguide element |
| US20060034561A1 (en) * | 2003-02-18 | 2006-02-16 | Jds Uniphase Corporation | Planar lightwave circuit package |
-
2015
- 2015-06-24 CN CN201510353426.XA patent/CN105044860B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0697187A (en) * | 1992-09-14 | 1994-04-08 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| CN1094817A (en) * | 1993-03-19 | 1994-11-09 | 阿克佐诺贝尔公司 | Semiconductor element and mutually integrated method and the electric-optical appliance of polymeric optical waveguide element |
| US20060034561A1 (en) * | 2003-02-18 | 2006-02-16 | Jds Uniphase Corporation | Planar lightwave circuit package |
| US7203390B2 (en) * | 2003-02-18 | 2007-04-10 | Jds Uniphase Corporation | Planar lightwave circuit package |
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| CN105044860B (en) | 2016-08-24 |
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