JPH0697187A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the base or source/drain resistance by using a polycrystalline Ge film or polycrystalline SiGe compound film, instead of a polycrystalline Si film, for the base or source.drain lead-out electrode. CONSTITUTION:The title semiconductor device consists of a p-type Si substrate 1, n-type impurity buried layer 2, low-concentration n-type epitaxial layer 3, p-type impurity diffusion layer 4, n-type impurity diffusion layer 5, element isolation SiO2 film 6, p-type polycrystalline Ge film 7, SiO2 film 8, n-type polycrystalline Si film 9, W silicide Si film 10, and metal electrodes 11, 12, and 13 as base, emitter, and collector, respectively. The n-type impurity diffusion layer 5 and n-type polycrystalline Si film 9 to serve as emitter; the p-type impurity diffusion layer 4 as base; the low-concentration n-type epitaxial layer 3 and n-type impurity buried layer 2 as collector; and the p-type polycrystalline Ge film 7 and W silicide Si film 10 as base lead-out electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a digital IC and an analog IC which are highly integrated and suitable for ultra-high speed operation.

[0002]

2. Description of the Related Art Regarding a base layer take-out electrode of a bipolar transistor according to the prior art, Technical Digest of IDM 1988.
Pages 744 to 747 (Technical Digest of IED
M 1988 pp.744-747). That is, in this conventional technique, as shown in FIG. 4, the extraction electrode of the base layer is made of the polycrystalline Si film 22, and the graft base (external base) layer 4 is formed by implanting impurities into the polycrystalline Si film. It is formed by heating and diffusing it in the substrate.

Regarding the extraction electrodes for the source and drain of the MOS transistor according to the prior art, the Extended Abstracts of the 9th Conference on Solid State is known.
Devices and Materials, pages 343-346 (Extended Abstracts of the Conference onSo
(Lid State Devices and Materials, 1987 pp.343-346)
Are described in. That is, in this conventional technique, the source and drain take-out electrodes are made of a polycrystalline Si film as in the case of the base take-out electrode of a bipolar transistor, and the source and drain diffusion layers are made by ion implantation of impurities into the polycrystalline Si film. It is formed by implanting, heating and diffusing into the substrate.

[0004]

When the graft base impurity diffusion layer of the bipolar transistor and the source / drain impurity diffusion layer of the MOS transistor are made high in concentration and shallow, it is advantageous for speeding up and size reduction. In the prior art, in order to make these diffusion layers shallow, polycrystalline Si is used.
Means have been taken to lower the heating temperature and shorten the time after the implantation of impurity ions into the film. However, the implanted ions have a non-uniform distribution in the polycrystalline Si film, and the diffusion rates of impurities differ by at most about two digits in the polycrystalline Si film and the single crystal Si substrate. If the time and time are reduced too much, the impurity concentration in the substrate will not be sufficiently high and the parasitic resistance will increase. Therefore, in the prior art, it is impossible to make these diffusion layers shallower than a certain limit, which is an obstacle to speeding up and miniaturization of dimensions.

Next, in the case of complementary bipolar in which CMOS or NPN-type and PNP-type bipolar transistors according to the prior art are formed on the same substrate, a base lead-out electrode or source / drain lead-out using polycrystalline Si is used. There are both P-type and N-type electrodes, and each has a junction with a metal or metal silicide electrode. However, it is difficult to reduce the heights of both P-type and N-type Schottky barriers by the same electrode material, and different P-type and N-type materials are used to reduce the contact resistance when the junction area is fine. However, there is a problem in that the manufacturing process becomes complicated because it is necessary to use the electrode.

Further, in the conventional bipolar transistor and MOS transistor, a polycrystalline Si film deposited on the Si substrate is selectively removed by photolithography and dry etching to form an emitter or gate hole reaching the Si substrate surface. A forming process is required. However, since the polycrystalline Si film and the Si substrate are made of the same material, there is no difference in the etching rate in dry etching, and it is difficult to detect the etching end point of the polycrystalline Si film. Therefore, there is also a problem that the Si substrate is etched in this step and the transistor characteristics are adversely affected.

Therefore, it is an object of the present invention to provide the above-mentioned graft base impurity diffusion layer and source,
The problem is that it is difficult to make the drain impurity diffusion layer shallow at a high concentration, and the contact resistance between the base extraction electrode and the source / drain extraction electrode with the metal electrode is P
Solves the problem that it is difficult to reduce both type N type and the problem that it is difficult to selectively remove the polycrystalline Si film of the base extraction electrode or the source / drain extraction electrode with respect to the Si substrate by etching. To do.

[0008]

A polycrystalline Ge film or a polycrystalline SiGe compound film is used instead of a polycrystalline Si film for a base extraction electrode or a source / drain extraction electrode.

The graft base and the impurity diffusion layers of the source and drain are formed of this polycrystalline Ge film or polycrystalline Si film.
The Ge compound film is formed by ion-implanting impurities into the Ge compound film and then heating it to diffuse it into the Si substrate.

Also, a base take-out electrode or a source,
When a two-layer film of a polycrystalline Si film and a metal film or a metal silicide film is used for the drain extraction electrode, a two-layer film of a polycrystalline Ge film or a polycrystalline SiGe compound film and a metal film or a metal silicide film is used instead. Use a membrane.

As a method of forming a polycrystalline Ge film or a polycrystalline SiGe compound film, there is a method of directly depositing a polycrystalline film or a method of depositing an amorphous film and ion-implanting impurities and then heating to polycrystallize. To use.

[0012]

The diffusion constants of impurities in single crystal Ge and single crystal Si are compared in FIGS. 3 (a) and 3 (b). From this figure, it is found that in Ge at the same temperature, P and As have 5 digits or more.
It can be understood that it is about 7 digits and B is about 3 digits larger than that in Si. The impurity diffusion constant in the polycrystalline Ge film is larger than that in single crystalline Ge, and the difference between polycrystalline Ge and single crystalline Si is further expanded by about two digits.

When these impurity atoms are added by ion implantation into an amorphous Ge film or a polycrystalline Ge film deposited on a Si substrate and heated at a low temperature of about 700 ° C. or less, the impurities are different due to the difference in diffusion constant. It is possible to diffuse the atoms so as to be distributed almost uniformly in the polycrystallized Ge film without causing the atoms to be diffused into the Si substrate. When impurities are diffused further into the Si substrate from the polycrystalline Ge film in which the impurities are uniformly distributed, the influence of the impurity distribution in the film due to the ion implantation is eliminated, so that a high-concentration and extremely shallow impurity diffusion layer is formed. It becomes possible to form it in a Si substrate. The action is qualitatively the same when a polycrystalline SiGe compound film is used instead of the polycrystalline Ge film.

For the above reasons, a polycrystalline Ge film or a polycrystalline SiGe compound film is used for the base extraction electrode or the source / drain extraction electrode, and the impurities ion-implanted in the film are heated at a low temperature to be introduced into the Si substrate. By diffusing, it becomes possible to form a very shallow graft base or an impurity diffusion layer of source and drain.

Next, regarding the height of the Schottky barrier formed at the junction between a semiconductor and a specific metal, when the P-type and N-type are added together, a value close to the forbidden band width of the semiconductor is obtained. There is a property of becoming.

In the case of Si, the forbidden band width is about 1.1 eV, so that the Schottky barrier height of either P type or N type becomes 0.55 eV or more, and the contact resistance becomes high. However, in the case of Ge, the forbidden band width is about 0.6.
Since it is 6 eV, the Schottky barrier height at the junction with most metals is 0.5 eV or less for both P-type and N-type, and it is possible to reduce the contact resistance. Therefore, even if the complementary bipolar or CMOS base take-out electrode or the source / drain take-out electrode is finely bonded to the metal electrode, the metal electrode is
There is no need to make the mold and N-type different. The action is qualitatively the same when a polycrystalline SiGe compound film is used instead of the polycrystalline Ge film.

Furthermore, when fluorine-based gas and chlorine-based gas are used as reaction gases when etching a polycrystalline Ge film on a Si substrate, the etching rate ratio between polycrystalline Ge and single crystal Si should be 5 times or more. It is possible. Further, the end point of etching can be detected by detecting the emission of GeF and GeCl radicals. Therefore, it is possible to selectively remove the polycrystalline Ge film of the base lead-out electrode or the source / drain lead-out electrode on the Si substrate to form a hole for an emitter or a gate, without substantially cutting the Si substrate. . Polycrystalline G
The action is qualitatively the same when a polycrystalline SiGe compound film is used instead of the e film.

When impurities are ion-implanted into a Ge film or a SiGe compound film, the impurities are almost completely activated by heating at a low temperature when the film is amorphous, but when the film is polycrystalline. Only partial activation.
Therefore, as a method of forming a polycrystalline Ge film or a polycrystalline SiGe compound film, it is preferable to deposit amorphous and polycrystallize by heating after ion implantation of impurities.
This is advantageous for reducing the source / drain resistance.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 shows a sectional view of a bipolar transistor of the first embodiment of the present invention. Reference numeral 1 is a P-type Si substrate, 2 is an N-type impurity buried layer, 3 is a low concentration N-type epitaxial layer, 4 is a P-type impurity diffusion layer, 5 is an N-type impurity diffusion layer, and 6 is element isolation Si.
O ₂ film, 7 P-type polycrystalline Ge film, 8 SiO ₂ film, 9 N
Type polycrystalline Si film, 10 is W silicide Si film, 11, 1
Reference numerals 2 and 13 denote metal electrodes serving as a base, an emitter, and a collector, respectively. N-type impurity diffusion layer 5 and N-type polycrystalline S
i film 9 is an emitter, P type impurity diffusion layer 4 is a base, low concentration N type epitaxial layer 3 and N type impurity buried layer 2 are collectors, P type polycrystalline Ge film 7 and W silicide Si film 1
0 acts as a base take-out electrode. Although the present embodiment is an NPN type bipolar transistor, it is also possible to reverse the type of impurities in each part to form a PNP type bipolar transistor. It is also possible to use a polycrystalline SiGe compound film instead of the polycrystalline Ge film 7 of the base extraction electrode.

Next, the manufacturing method of this embodiment will be described with reference to FIG. FIG. 5 is a sectional view of each main step of this embodiment. However, the drawing of the collector is omitted in this figure.

The steps up to the formation of the low-concentration N type epitaxial layer 3 and the SiO ₂ film 6 for element isolation follow the same method as in the prior art (FIG. 5A).

Next, an amorphous Ge film 25 having a thickness of 150 nm is deposited by a normal low pressure vapor deposition (low pressure CVD) method. After that, 1 × 10 B is added by the ion implantation method.
^It is added to the amorphous Ge film 25 at a density of ¹⁶ / cm ² . Further, a W silicide Si film 10 having a thickness of 50 nm and a SiO ₂ film 8 having a thickness of 200 nm are formed by a normal low pressure CVD method.
Are deposited (FIG. 5B).

Next, by photolithography and plasma etching, SiO on the region where the emitter is to be formed is formed.
₂ film 8, W silicide Si film 10 and amorphous Ge film 2
5 is removed by etching. For plasma etching of the amorphous Ge film 25, CF4 or CCl4 is used as a reaction gas. After that, the amorphous Ge film is crystallized by heating at a temperature of about 700 ° C. in a nitrogen atmosphere to form a polycrystalline Ge film 7, and at the same time, B is diffused into the Si substrate to form P.
The type impurity diffusion layer 4 is formed. After that, B is added to the Si substrate by the method of ion implantation or thermal diffusion, and P is added.
The type impurity diffusion layer 23 is formed (FIG. 5C).

Next, a 20 nm thick SiO ₂ film is formed on the exposed portion of the Si substrate by thermal oxidation. Further, after depositing a SiO ₂ film having a thickness of 150 nm by the low pressure CVD method, the Si of the flat portion is formed by anisotropic plasma etching.
The O ₂ film is removed by etching to leave only the side wall SiO ₂ film 24 (FIG. 5D).

The following is the same known method as in the prior art,
The polycrystalline Si emitter 9 and the emitter impurity diffusion layer 5 are formed, and finally the metal electrodes 11 and 12 are formed by a normal method (FIG. 5E).

According to this embodiment, the depth of the graft base impurity layer can be reduced to 50 nm, which is about 1/3 of the conventional value, while the surface impurity concentration is maintained at 1 × 10 ²⁰ / cm ³ or more. Becomes Further, in the step of forming a hole for an emitter in the base take-out electrode by plasma etching, the amount of shaving of the Si substrate is reduced to about half that of the conventional one, 10 nm.
It becomes possible to reduce to the following. Further, in the case of the PNP transistor, the contact resistance between the W silicide and the N-type polycrystalline Ge film is reduced to about 1/5 as compared with the case of using the N-type polycrystalline Si film, so that the base resistance is reduced. 2 /
It becomes possible to reduce to 3.

Embodiment 2 FIG. 2 shows a sectional view of a MOS transistor according to a second embodiment of the present invention. 6 is a SiO ₂ film for element isolation, 9 is an N-type polycrystalline Si film, 10 is a W silicide Si film, 14 is an N-type polycrystalline Ge film, 15 is an N-type Si substrate, 16 is a P-type impurity diffusion layer, Reference numeral 17 is an N-type impurity diffusion layer, 18 is a SiO ₂ film as a gate insulating film, and 19, 20 and 21 are metal electrodes as a source, a gate and a drain, respectively. The W silicide Si film 10 and the N-type polycrystalline Ge film 14 are sources and drains, the N-type impurity diffusion layer 17 is a source,
The drain impurity diffusion layer, the SiO ₂ film 18 functions as a gate oxide film, and the N-type polycrystalline Si film 9 functions as a gate electrode.

Although the present embodiment is an N-channel MOS transistor, it may be a P-channel MOS transistor by reversing the type of impurities in each part. It is also possible to use a polycrystalline SiGe film instead of the polycrystalline Ge film 14 for the source / drain extraction electrodes.

Next, the manufacturing method of this embodiment will be described with reference to FIG. FIG. 6 is a sectional view of each main process of this embodiment.

The steps up to the formation of the P-type impurity diffusion layer 16 and the SiO ₂ film 6 for element isolation follow the same method as in the prior art (FIG. 6A).

Next, an amorphous Ge film 25 having a thickness of 150 nm is deposited by a normal low pressure vapor deposition (low pressure CVD) method. After that, P is set to 1 × 10 by the ion implantation method.
^It is added to the amorphous Ge film 25 at a density of ¹⁶ / cm ² . Further, a W silicide Si film 10 having a thickness of 50 nm and a SiO ₂ film 8 having a thickness of 200 nm are formed by a normal low pressure CVD method.
Are deposited (FIG. 6B).

Next, by photolithography and plasma etching, SiO ₂ on the region where the gate is to be formed is formed.
Film 8, W silicide Si film 10, and amorphous Ge film 25
Are removed by etching. For plasma etching of the amorphous Ge film 25, CF4 or CCl4 is used as a reaction gas. After that, the amorphous Ge film is crystallized by heating at a temperature of about 700 ° C. in a nitrogen atmosphere to form a polycrystalline Ge film 14, and at the same time, P is diffused into the Si substrate to form N.
The type impurity diffusion layer 17 is formed (FIG. 6C).

Next, a SiO ₂ film having a thickness of 20 nm is formed on the exposed portion of the Si substrate by thermal oxidation. Further, after depositing a SiO ₂ film with a thickness of 150 nm by the low pressure CVD method, the Si of the flat portion is subjected to anisotropic plasma etching.
The O ₂ film is removed by etching so that only the side wall SiO ₂ film 24 is left. Furthermore, a SiO ₂ film 18 having a thickness of 20 nm is formed on the exposed portion of the Si substrate by thermal oxidation (FIG. 6D).

The following is the same known method as in the prior art,
The polycrystalline Si gate electrode 9 is formed, and finally the metal electrode 1
9 and 20 are formed by a normal method (FIG. 6E).

According to the present embodiment, the depth of the source and drain impurity layers can be reduced to 50 nm, which is about 1/3 of the conventional value, while the surface impurity concentration is maintained at 1 × 10 ²⁰ / cm ³ or more. It will be possible. Further, in the step of forming the gate hole in the source / drain extraction electrode by plasma etching, the amount of shaving of the Si substrate is about half that of the conventional one.
Can be reduced to 10 nm or less. further,
Since the contact resistance between the W silicide and the N-type polycrystalline Ge film is reduced to about 1/5 as compared with the case where the N-type polycrystalline Si film is used, the resistance of the source and drain is reduced to about 2/3. It becomes possible.

[0037]

According to the present embodiment, in the graft base impurity layer or the source / drain impurity layer, the depth is about 1/3 of that of the conventional one while keeping the surface impurity concentration at 1 × 10 ²⁰ / cm ³ or more. Can be made as shallow as 50 nm.

Further, in the step of forming holes for emitters or gates in the polycrystalline Ge film by plasma etching, the amount of abrasion of the Si substrate is about half that of the conventional technique, 10n.
It becomes possible to reduce to m or less. Further, the contact resistance between the metal or metal silicide and the polycrystalline Ge film is 1/5 to 1/2 as compared with the case where the polycrystalline Si film is used.
Therefore, the base resistance of the bipolar transistor or the resistance of the source and drain is about 2/3.
It becomes possible to reduce to ~ 4/5.

Instead of the polycrystalline Ge film 7 for the base extraction electrode or the source / drain extraction electrodes, polycrystalline S film is used.
When the iGe compound film is used, the effect on the purpose is qualitatively the same as that of the polycrystalline Ge film, but quantitatively, it is proportional to the ratio of Ge in the film. The ratio of Ge in the film needs to be 10% or more to obtain a practically meaningful effect.

[Brief description of drawings]

FIG. 1 is a sectional view of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a MOS transistor according to a second embodiment of the present invention.

FIG. 3 is a diagram comparing the temperature dependence of diffusion constants of impurities in Ge and Si.

FIG. 4 is a cross-sectional view of a conventional bipolar transistor.

FIG. 5 is a cross-sectional view of an element for each step showing the method for manufacturing the bipolar transistor of the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of an element for each step showing a method for manufacturing a MOS transistor according to a second embodiment of the present invention.

[Explanation of symbols]

1 ... P-type Si substrate, 2 ... N-type impurity buried layer, 3 ... Low-concentration N-type epitaxial layer, 4 ... P-type impurity diffusion layer, 5 ... N
-Type impurity diffusion layer, 6 ... SiO ₂ film, 7 ... P-type polycrystalline Ge
Film, 8 ... SiO ₂ film, 9 ... N-type polycrystalline Si film, 10 ... W
Silicide film, 11, 12, 13 ... Metal electrode, 14 ... N
-Type polycrystalline Ge film, 15 ... N-type Si substrate, 16 ... P-type impurity diffusion layer, 17 ... N-type impurity diffusion layer, 18 ... SiO
₂ film, 19, 20, 21 ... Metal electrode, 22 ... P-type polycrystalline Si film, 23 ... P-type impurity diffusion layer, 24 ... SiO ₂ film,
25 ... Amorphous Ge film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 29/784 (72) Inventor Yoichi Tamaki 1-280, Higashi-Kengikubo, Kokubunji-shi, Tokyo Hitachi Central Co., Ltd. In the laboratory

Claims (7)

[Claims] 1. A semiconductor device using a polycrystalline Ge film or a polycrystalline SiGe compound film as an extraction electrode of an impurity diffusion layer. 2. A bipolar transistor using a polycrystalline Ge film or a polycrystalline SiGe compound film as at least a part of a takeout electrode of a base layer. 3. A polycrystalline Ge film or a polycrystalline SiGe compound film on at least a part of the extraction electrode of the base layer,
A bipolar transistor using a two-layer film of a metal film or a metal silicide film. 4. A polycrystalline Ge film or polycrystalline SiGe on at least a part of the source and drain take-out electrodes.
A MOS transistor using a compound film. 5. A polycrystalline Ge film or polycrystalline SiGe on at least a part of the source and drain take-out electrodes.
A MOS transistor using a two-layer film of a compound film and a metal film or a metal silicide film. 6. The bipolar transistor and the MOS transistor according to any one of claims 1 to 5 of the present invention, wherein the ratio of Ge in the polycrystalline SiGe compound film is 10% or more. 7. An amorphous Ge or SiGe compound thin film deposited on a Si substrate is ion-implanted and heated to crystallize the film and Si.
A method of manufacturing a semiconductor device, characterized in that impurity atoms are diffused in a substrate.