CN105023939A

CN105023939A - Novel 4H-SiC MOSFET device with under-gate well structure

Info

Publication number: CN105023939A
Application number: CN201510161064.4A
Authority: CN
Inventors: 高博; 吴勤
Original assignee: Sichuan University
Current assignee: Sichuan University
Priority date: 2015-04-08
Filing date: 2015-04-08
Publication date: 2015-11-04

Abstract

The invention discloses a novel 4H-SiC MOSFET device with an under-gate well structure in a planar technology. The 4H-SiC MOSFET device is mainly used in the high-voltage circuit design. An under-gate well in the novel 4H-SiC MOSFET device can be grounded or suspended. Through the structural design of the novel 4H-SiC MOSFET device with the under-gate well, the breakdown voltage of the 4H-SiC MOSFET device can be significantly increased. The novel 4H-SiC MOSFET device is a longitudinal NMOSFET, the structure thereof is shown in Figure 1, and the longitudinal NMOSFET comprises a drain electrode (1), an n-substrate (2), an n-drift layer (3), a p-well (4), a bottom p-well (BPW) (5), a p- (6), an n+ (7), a p+ (8), a gate oxide (9), a poly-Si (10), an interlayer oxide (11) and a source electrode (12) from top to bottom. Since the grounded or suspended BPW structure is additionally arranged below the poly-Si, the novel 4H-SiC MOSFET device has the advantage that the breakdown voltage thereof is higher than that of an ordinary 4H-SiC field effect transistor when in breakover, and is more suitable for design and research of high-voltage circuits.

Description

Well structure 4H-SiCMOSFET device under a kind of novel grid

Technical field

The present invention relates to a kind of electronic component technology field, particularly relate to a kind of field-effect transistor, can be applicable to as large power semiconductor device.

Background technology

SiC material has band gap length, disruptive field intensity is high, electron saturation velocities is high, the feature of the high excellence of thermoelectricity conductance, is suitable for high-temperature high-frequency work, and can be the same with Si, adopts planar technique to make various SiC power device, comprises IGBT.In the polymorph of SiC, the electron mobility of 4H-SiC is about the twice of homostructural 6H-SiC, and therefore most power device adopts 4H-SiC as making material.

Although compare with traditional Si device, the puncture voltage of SiC device significantly improves.But under Gao Yuan, drain dias voltage, the reliability of local highfield to device proposes challenge.

A symmetric form 4H-SiC NMOSFET structure adopting standard SiC planar technique to make as shown in Figure 1.By its puncture voltage of device simulation acquisition as shown in Figure 2, at about 530V.Fig. 3 gives the inside field strength distribution of this device near disruptive critical voltage, finds in p-well and n-drift layer contact-making surface corner, easily forms local high field intensity, reduces the voltage endurance of device.

Summary of the invention

The object of the invention is to the deficiency for existing structure, propose the 4H-SiC NMOSFET that a kind of puncture voltage is larger, improve device performance.

The key of the technology of the present invention is: on the basis of existing symmetric form 4H-SiCNMOSFET structure, adds a BPW structure below polysilicon gate, and this BPW structure is divided into ground connection or unsettled two types.

The novel 4H-SiCNMOSFET of BPW structure under band grid of the present invention, as shown in Figure 4, comprise metal leakage pole (drain electrode) from bottom to top, the highly doped 4H-SiC substrate (n-substrate) of N-shaped, N-shaped light dope 4H-SiC epitaxial loayer (n-drift layer), p trap (BPW) (ground connection or unsettled) under grid, common p trap (p-well), p-type light dope channel region (p-), the highly doped ohmic contact regions of N-shaped (n+), the highly doped ohmic contact regions of p-type (p+), SiO ₂gate oxide (gate oxide), polysilicon gate (poly-Si), Si ₃n ₄grid, source separator (interlayer oxide), metal source (source electrode).

The present invention owing to introducing a ground connection or unsettled BPW structure under polysilicon gate, and the conducting puncture voltage of 4H-SiCNMOSFET obtains and significantly improves, and when BPW ground connection, puncture voltage reaches about 675V, as shown in Figure 5; When BPW is unsettled, puncture voltage reaches 710V, as shown in Figure 6.In device, local high field intensity obtains and effectively alleviates, as shown in Figure 7.

Accompanying drawing explanation

Fig. 1 is the symmetric form 4H-SiCNMOSFET structure chart not with BPW structure;

Fig. 2 is the symmetric form 4H-SiCNMOSFET breakdown characteristics figure not with BPW structure;

Fig. 3 is the device inside field intensity map of symmetric form 4H-SiCNMOSFET under disruptive critical voltage not with BPW structure;

Fig. 4 is the novel 4H-SiCNMOSFET structure chart of ground connection or unsettled BPW structure under band grid of the present invention;

Signal number in the figure illustrates:

(1) metal leakage pole (drain electrode), (2) the highly doped 4H-SiC substrate (n-substrate) of N-shaped, (3) N-shaped light dope 4H-SiC epitaxial loayer (n-drift layer), (4) common p trap (p-well), (5) p trap (BPW) (ground connection or unsettled) under grid, (6) p-type light dope channel region (p-), the highly doped ohmic contact regions of (7) N-shaped (n+), (8) the highly doped ohmic contact regions of p-type (p+), (9) SiO ₂gate oxide (gate oxide), (10) polysilicon gate (poly-Si), (11) Si ₃n ₄grid, source separator (interlayer oxide), (12) metal source (source electrode).

Fig. 5 is BPW structure with ground and the breakdown characteristics device simulation result figure in the on state of the 4H-SiCNMOSFET not with BPW structure;

Fig. 6 is the unsettled BPW structure of band and the breakdown characteristics device simulation result figure in the on state of the 4H-SiCNMOSFET not with BPW structure;

Fig. 7 is the device inside field intensity map of novel 4H-SiCNMOSFET under disruptive critical voltage of ground connection BPW structure under band grid.

Claims

1. under novel grid, trap 4H-SiCNMOSFET structure comprises drain electrode(1 from top to bottom), n-substrate(2), n-drift layer(3), p-well(4), bottom p-well (BPW) (5), p-district (6), n+ district (7), p+ district (8), gate oxide(9), poly-Si(10), interlayer oxide(11), source electrode(12).

2. the drain electrode(1 of new structure 4H-SiCNMOSFET described in) and source electrode(12) represent source metal, drain electrode respectively; The poly-Si(10 of described new structure 4H-SiCNMOSFET) be polygate electrodes; Bottom p-well (BPW) (5) of described new structure 4H-SiCNMOSFET are positioned at gate oxide(9) below a ground connection or unsettled p-well; The n-substrate(2 of described new structure 4H-SiCNMOSFET) be the highly doped 4H-SiC substrate of N-shaped; The n-drift layer(3 of described new structure 4H-SiCNMOSFET) be N-shaped light dope 4H-SiC substrate epitaxial layer; The n+ district (7) of described new structure 4H-SiCNMOSFET is the highly doped ohmic contact regions of N-shaped; The p-well(4 of described new structure 4H-SiCNMOSFET) be the p trap of NMOSFET; The p-district (6) of described new structure 4H-SiCNMOSFET is p-type light dope channel region; The p+ district (8) of described new structure 4H-SiCNMOSFET is the highly doped ohmic contact regions of p-type, is used for connecting p-well and metal source; The gate oxide(9 of described new structure 4H-SiCNMOSFET) and interlayer oxide(11) be SiO respectively ₂gate oxide and Si ₃n ₄separator.

3. the 4H-SiCNMOSFET according to claims 1,2, is characterized in that the vertical structure that have employed a kind of symmetry; Electric current flows into from metal-drain (1), flows out to metal source (12) by the p-channel region (6) of both sides.

4. the 4H-SiCNMOSFET according to claims 1,2, is characterized in that adding below polysilicon gate the BPW structure of a unsettled or ground connection, effectively can improve device electric breakdown strength.

5. the 4H-SiCNMOSFET according to claims 1,2, is characterized in that middle BPW(5) and the common p-well(4 in both sides) what adopt is identical planar technique.

6. the 4H-SiCNMOSFET according to claims 1,2 adopts the SiC power device plane manufacture craft of standard.