CN105023905A - Lead frame and power integrated circuit package with lead frame - Google Patents
Lead frame and power integrated circuit package with lead frame Download PDFInfo
- Publication number
- CN105023905A CN105023905A CN201510464941.5A CN201510464941A CN105023905A CN 105023905 A CN105023905 A CN 105023905A CN 201510464941 A CN201510464941 A CN 201510464941A CN 105023905 A CN105023905 A CN 105023905A
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- chip
- lead frame
- support bar
- power integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to a lead frame and a power integrated circuit package with the lead frame. According to an embodiment of the invention, a power integrated circuit package comprises a control chip which is arranged on a first chip bearing base and used for receiving an input signal, a power chip which is arranged on a second chip bearing base and used for transmitting an output signal, a plurality of input pins extending between the first chip bearing base and a first side, a plurality of output pins extending between the second chip bearing base and a second side, a pair of supporting parts located on a third side and a fourth side separately, and a package shell covering the control chip, the power chip and the pair of supporting parts, wherein each supporting part comprises two supporting rods separated from each other by a safe distance. The power integrated circuit package is capable of effectively preventing the occurrence of the electric arc creepage phenomenon between the input end and the output end thereof during a high voltage isolation test; as a result, the accuracy rate of the test and the product yield are improved, and furthermore, the production cost can be reduced.
Description
Technical field
The present invention relates generally to semiconductor applications, more specifically, relates to the power integrated circuit packaging part of lead frame and this lead frame of use.
Background technology
When carrying out high_voltage isolation test to power integrated circuit packaging part, usually there is the problem of input and output short circuit.The main cause of this problem is caused to be: when only carrying out Hi-pot test to power integrated circuit encapsulation, can produce electric arc between the input and output of packaging part, electric arc can flow through strutting piece along packaging body further; Because strutting piece common is at present generally integral curved structure, creepage (creepage distance) distance is shorter, thus causes input and the output short circuit of power integrated circuit packaging part.
For example, Fig. 1 is the structural representation of an existing power integrated circuit packaging part.As shown in Figure 1, this existing power integrated circuit packaging part 10, the strutting piece 110 that it comprises lays respectively at the opposite side of power integrated circuit packaging part 10, and the strutting piece 110 of every side is all integral curved structure, cause the creepage spacing at these strutting piece 110 two ends, namely safe distance is comparatively short.When carrying out Hi-pot test to this power integrated circuit packaging part 10, electric arc can flow through this strutting piece, causes input and the output short circuit of this power integrated circuit packaging part 10.
The short circuit of power integrated circuit encapsulation input and output can affect the chip of packaging part inside, the serious chip that directly may damage packaging part inside, thus affects the quality of power integrated circuit packaging part, and then affects product yield.
Therefore, existing power integrated circuit encapsulating structure needs to improve further, causes the short circuit between input and output to avoid the electric arc of its input and output to produce creepage by strutting piece.
Summary of the invention
An object of the present invention is the power integrated circuit packaging part providing a wire frame and use this lead frame, and it can effectively reduce mortality power integrated circuit packaging part being carried out to high_voltage isolation test, thus improves product percent of pass.
According to one embodiment of the invention, one lead frame encapsulated for power integrated circuit, it comprises: housing and multiple lead frame unit, wherein, each in multiple lead frame unit has the first relative side and the second side, and the 3rd relative side and the 4th side.Each lead frame unit comprises: the first chip loading seat; Second chip loading seat; Multiple input pin, is connected between the first chip loading seat and the first side; Multiple output pin, is connected between the second chip loading seat and the second side; And pair of engage members, lay respectively at the 3rd side and the 4th side of lead frame unit; And each strutting piece comprise a spaced apart safe distance the first support bar and the second support bar.
According to another embodiment of the present invention, this is used for the first support bar in the lead frame of power integrated circuit encapsulation and the safe distance at the second support bar interval is not less than 650um.According to another embodiment of the present invention, this is used for the first support bar in the lead frame of power integrated circuit encapsulation and the shape of the second support bar is hook-shaped.
One embodiment of the invention additionally provide a power integrated circuit packaging part, and it has the first relative side and the second side, and the 3rd relative side and the 4th side.This power integrated circuit packaging part comprises: control chip, and it is configured to be arranged on the first chip loading seat; This control chip is for receiving input signal; Power chip, it is configured to be arranged on the second chip loading seat; This power chip is for sending output signal; Multiple input pin, extends between described first chip loading seat and described first side; Multiple output pin, extends between described second chip loading seat and described second side; Pair of engage members, lays respectively at described 3rd side and the 4th side, and each strutting piece comprise a spaced apart safe distance the first support bar and the second support bar; And encapsulating housing, its Coverage Control chip, power chip and pair of engage members.
According to another embodiment of the present invention, the voltage that this power integrated circuit packaging part is applied is less than 10 kilovolts.
Compared with prior art, the power integrated circuit packaging part of the lead frame that the embodiment of the present invention provides and this lead frame of use is when high_voltage isolation is tested, can effectively prevent from producing electric arc creepage phenomenon between its input and output, improve accuracy rate and the product yield of test, and then reduce production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of an existing power integrated circuit packaging part.
Fig. 2 is according to an embodiment of the invention for the structural representation of the lead frame of power integrated circuit encapsulation.
Fig. 3 is the structural representation of power integrated circuit packaging part according to an embodiment of the invention.
Embodiment
Spirit for a better understanding of the present invention, is described further it below in conjunction with part preferred embodiment of the present invention.
Fig. 2 is according to an embodiment of the invention for the structural representation of the lead frame 20 of power integrated circuit.
As shown in Figure 2, comprise for the lead frame 20 of power integrated circuit encapsulation according to an embodiment of the invention: housing 200 and multiple lead frame unit 220.For the purpose of simple, this schematic diagram only illustrates the structure of one of them lead frame unit 220.There is in this lead frame unit 220 the first relative side 202 and the second side 204, and the 3rd relative side 206 and the 4th side 208; And comprise: the first chip loading seat 221, second chip loading seat 222, multiple input pin 223, multiple output pin 224, and pair of engage members 225.The plurality of input pin 223 is connected between the first chip loading seat 221 and the first side 202.The plurality of output pin 224 is connected between the second chip loading seat 222 and the second side 204.And this extends the 3rd side 206 and the 4th side 208 of lead frame unit 220 respectively from corresponding housing 220 place to strutting piece 225.In order to avoid the shorter generation short circuit of creepage distance when high_voltage isolation is tested, each strutting piece 225 be designed to comprise a spaced apart safe distance the first support bar 226 and the second support bar 227.The safe distance at this first support bar 226 and the second support bar 227 interval is not less than 650um, and it is applicable to the power integrated circuit encapsulation that applied voltage is not less than 10 kilovolts.The shape of the first support bar 226 and the second support bar 227 is not limit, and those skilled in the art can be designed to vertical bar shaped or the various shape such as hook-shaped as required.
When using this lead frame 20 to encapsulate, first the finishing process after plastic packaging needs to carry out cutting process to the connection bracket 240 of lead frame unit 220 first side 202 and the second side 204, and lead frame unit 220 is separated with connection bracket 240; Carry out forming processes subsequently; Finally the 3rd side 206 and the first support bar 226 of the 4th side 208 and the epitaxial part of the second support bar 227 are cut.The benefit of this treatment process order is: after lead frame 20 is cut, passive first support bar 226 and the second support bar 227 can effectively avoid lead frame unit 220 to drop on board.
In addition, not only due to strutting piece 225 be designed to be separated two support bars and with entirety, and between two support bars, there is minimum safe distance, when carrying out high pressure (as 10KV) isolation test to semiconductor package part 30, by the short-circuit conditions effectively avoiding semiconductor package part 30 input and output to cause due to creepage phenomenon.According to one embodiment of the invention, when safe distance is greater than 650um, semiconductor package part 30 can support that the voltage on a large scale of 600V-11KV inputs.
Fig. 3 is the structural representation of power integrated circuit packaging part 30 according to an embodiment of the invention.
As shown in Figure 3, comprise a power integrated circuit packaging part 30 in the embodiment of the present invention according to an embodiment of the invention, it has the first relative side 202 and the second side 204, and the 3rd relative side 206 and the 4th side 208.This power integrated circuit packaging part 30 comprises: control chip 302, power chip 304, multiple input pin 223, multiple output pin 224, pair of engage members 225 and encapsulating housing (not shown).This control chip 302 to be arranged on chip first load bearing seat 221 and this control chip 302 for receiving input signal.Power chip 304 to be arranged on the second chip loading seat 222 and this power chip 304 for sending output signal.Multiple input pin 223 extends between this first chip loading seat 221 and first side 202; Multiple output pin 224 extends between the second chip loading seat 222 and the second side 204.Pair of engage members 225 lays respectively at the 3rd side 206 and the 4th side 208, and each strutting piece 225 comprise a spaced apart safe distance the first support bar 226 and the second support bar 227.Encapsulating housing (not shown) Coverage Control chip 302, power chip 304, first support bar 226 and the second support bar 227; And the safe distance at this first support bar 226 and the second support bar 227 interval is not less than 650um.
Technology contents of the present invention and technical characterstic disclose as above, but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modification, and is contained by present patent application claims.
Claims (7)
1., for a lead frame for power integrated circuit encapsulation, it comprises:
Housing; And
Multiple lead frame unit, wherein, each in described multiple lead frame unit has the first relative side and the second side, and the 3rd relative side and the 4th side; Each lead frame unit described comprises:
First chip loading seat;
Second chip loading seat;
Multiple input pin, is connected between described first chip loading seat and described first side;
Multiple output pin, is connected between described second chip loading seat and described second side;
And
Pair of engage members, lays respectively at described 3rd side and the 4th side of described lead frame unit; And
Each strutting piece comprise a spaced apart safe distance the first support bar and the second support bar.
2. the lead frame for power integrated circuit encapsulation according to claim 1, the described safe distance at wherein said first support bar and described second support bar interval is not less than 650um.
3. the lead frame for power integrated circuit encapsulation according to claim 1, the shape of described first support bar and the second support bar is hook-shaped.
4. a power integrated circuit packaging part, it has the first relative side and the second side, and the 3rd relative side and the 4th side; Described power integrated circuit packaging part comprises:
Control chip, it is configured to be arranged on the first chip loading seat; Described control chip is for receiving input signal;
Power chip, it is configured to be arranged on the second chip loading seat; Described power chip is for sending output signal;
Multiple input pin, extends between described first chip loading seat and described first side;
Multiple output pin, extends between described second chip loading seat and described second side;
Pair of engage members, lays respectively at described 3rd side and the 4th side, and each strutting piece comprise a spaced apart safe distance the first support bar and the second support bar; And
Encapsulating housing, it covers described control chip, described power chip and described to strutting piece.
5. power integrated circuit packaging part according to claim 4, the described safe distance at wherein said first support bar and described second support bar interval is not less than 650um.
6. power integrated circuit packaging part according to claim 4, the shape of described first support bar and the second support bar is hook-shaped.
7. power integrated circuit packaging part according to claim 4, its voltage applied is less than 10 kilovolts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510464941.5A CN105023905B (en) | 2015-07-31 | 2015-07-31 | Lead frame and the power integrated circuit packaging part using the lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510464941.5A CN105023905B (en) | 2015-07-31 | 2015-07-31 | Lead frame and the power integrated circuit packaging part using the lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105023905A true CN105023905A (en) | 2015-11-04 |
| CN105023905B CN105023905B (en) | 2018-01-16 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510464941.5A Active CN105023905B (en) | 2015-07-31 | 2015-07-31 | Lead frame and the power integrated circuit packaging part using the lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105023905B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370382A (en) * | 2018-12-25 | 2020-07-03 | 恩智浦美国有限公司 | Hybrid lead frame for semiconductor die package with improved creepage distance |
| CN112133688A (en) * | 2020-11-25 | 2020-12-25 | 苏州纳芯微电子股份有限公司 | Packaging structure of multi-base-island lead frame |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230783A (en) * | 1998-03-27 | 1999-10-06 | 三菱电机株式会社 | Semiconductor device and lead fram for semiconductor device |
| US20030147436A1 (en) * | 2002-02-01 | 2003-08-07 | Sharp Kabushiki Kaisha | Semiconductor laser device, method of fabricating the same, and optical pickup employing the same |
| CN101174603A (en) * | 2006-11-02 | 2008-05-07 | 株式会社瑞萨科技 | Semiconductor device and manufacturing method of the same |
| CN101442036A (en) * | 2007-11-23 | 2009-05-27 | 华泰电子股份有限公司 | Conductor holder structure and application thereof |
| CN204857713U (en) * | 2015-07-31 | 2015-12-09 | 日月光封装测试(上海)有限公司 | Lead frame and power integrated circuit packaging part that uses this lead frame |
-
2015
- 2015-07-31 CN CN201510464941.5A patent/CN105023905B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230783A (en) * | 1998-03-27 | 1999-10-06 | 三菱电机株式会社 | Semiconductor device and lead fram for semiconductor device |
| US20030147436A1 (en) * | 2002-02-01 | 2003-08-07 | Sharp Kabushiki Kaisha | Semiconductor laser device, method of fabricating the same, and optical pickup employing the same |
| CN101174603A (en) * | 2006-11-02 | 2008-05-07 | 株式会社瑞萨科技 | Semiconductor device and manufacturing method of the same |
| CN101442036A (en) * | 2007-11-23 | 2009-05-27 | 华泰电子股份有限公司 | Conductor holder structure and application thereof |
| CN204857713U (en) * | 2015-07-31 | 2015-12-09 | 日月光封装测试(上海)有限公司 | Lead frame and power integrated circuit packaging part that uses this lead frame |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370382A (en) * | 2018-12-25 | 2020-07-03 | 恩智浦美国有限公司 | Hybrid lead frame for semiconductor die package with improved creepage distance |
| CN112133688A (en) * | 2020-11-25 | 2020-12-25 | 苏州纳芯微电子股份有限公司 | Packaging structure of multi-base-island lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105023905B (en) | 2018-01-16 |
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Effective date of registration: 20201229 Address after: No. 669, GuoShouJing Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Patentee after: Rirong semiconductor (Shanghai) Co.,Ltd. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 669 Patentee before: ASE ASSEMBLY & TEST (SHANGHAI) Ltd. |
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