CN105023905B - Lead frame and the power integrated circuit packaging part using the lead frame - Google Patents
Lead frame and the power integrated circuit packaging part using the lead frame Download PDFInfo
- Publication number
- CN105023905B CN105023905B CN201510464941.5A CN201510464941A CN105023905B CN 105023905 B CN105023905 B CN 105023905B CN 201510464941 A CN201510464941 A CN 201510464941A CN 105023905 B CN105023905 B CN 105023905B
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- China
- Prior art keywords
- support bar
- integrated circuit
- support
- lead frame
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Power integrated circuit packaging part the present invention relates to lead frame and using the lead frame.According to one embodiment of the invention, a power integrated circuit packaging part includes：The control chip being arranged on the first chip loading seat, it is used to receive input signal；The power chip being arranged on the second chip loading seat, it is used to send output signal；Extend multiple input pins between the first chip loading seat and the first side；Extend multiple output pins between the second chip loading seat and the second side；Respectively positioned at a pair of support members of the 3rd side and the 4th side, and each support member includes two support bars for being spaced apart a safe distance；And encapsulating housing, it covers control chip, power chip and a pair of support members.The power integrated circuit packaging part can effectively prevent generation electric arc creepage phenomenon between its input and output end when high_voltage isolation is tested, and improve the accuracy rate and product yield of test, and then reduce production cost.
Description
Technical field
The present invention relates generally to semiconductor applications, the work(more particularly, to lead frame and using the lead frame
Rate ic package.
Background technology
When carrying out high_voltage isolation test to power integrated circuit packaging part, input and output terminal shortcircuit are usually present
The problem of.The main reason for causing this problem is：When only carrying out Hi-pot test to power integrated circuit encapsulation, encapsulating
Electric arc can be produced between the input and output end of part, electric arc can flow through support member further along packaging body；Due to common at present
Support member be usually integral curved structure, it is shorter to climb electric (creepage distance) distance, so as to cause the integrated electricity of power
The input and output terminal shortcircuit of road packaging part.
For example, Fig. 1 is the structural representation of an existing power integrated circuit packaging part.As shown in figure 1, the existing work(
Rate ic package 10, its support member 110 included are located at the opposite side of power integrated circuit packaging part 10 respectively, and often
The support member 110 of side is all integral curved structure, and cause the both ends of support member 110 climbs electric spacing, i.e. safe distance is shorter.
When carrying out Hi-pot test to the power integrated circuit packaging part 10, electric arc can flow through the support member, cause the integrated electricity of the power
The input and output terminal shortcircuit of road packaging part 10.
Power integrated circuit encapsulates input and the short-circuit chip that can be influenceed inside packaging part of output end, serious possibility
The chip directly damaged inside packaging part, so as to influence the quality of power integrated circuit packaging part, and then influence product yield.
Therefore, existing power integrated circuit encapsulating structure need to be improved further, to avoid its input and output end
Electric arc is produced by support member climbs electricity to cause the short circuit between input and output end.
The content of the invention
An object of the present invention is the power integrated circuit packaging part for providing a wire frame and the use lead frame,
It can effectively reduce the mortality that high_voltage isolation test is carried out to power integrated circuit packaging part, so as to improve product percent of pass.
The lead frame of power integrated circuit encapsulation is used for according to one embodiment of the invention, one, it includes：Housing and multiple
Lead frame unit, wherein, each of multiple lead frame units have the first relative side and the second side, and relative
3rd side and the 4th side.Each lead frame unit includes：First chip loading seat；Second chip loading seat；Multiple inputs are drawn
Pin, it is connected between the first chip loading seat and the first side；Multiple output pins, it is connected to the second chip loading seat and the second side
Between；And a pair of support members, respectively positioned at the 3rd side of lead frame unit and the 4th side；And each support member includes interval
Open the first support bar and second support bar of a safe distance.
According to another embodiment of the present invention, the first support bar being used in the lead frame of power integrated circuit encapsulation
It is not less than 650um with the safe distance at second support bar interval.According to another embodiment of the present invention, this is used for the integrated electricity of power
Road encapsulation lead frame in first support bar and second support bar be shaped as it is hook-shaped.
One embodiment of the invention additionally provides a power integrated circuit packaging part, and it has relative the first side and second
Side, and the 3rd relative side and the 4th side.The power integrated circuit packaging part includes：Control chip, it is configured to be arranged at
On first chip loading seat；The control chip is used to receive input signal；Power chip, it is configured to be arranged at the second chip
On load bearing seat；The power chip is used to send output signal；Multiple input pins, extend first chip loading seat and institute
State between the first side；Multiple output pins, extend between second chip loading seat and second side；A pair of supports
Part, respectively positioned at the 3rd side and the 4th side, and each support member include the first support bar that is spaced apart a safe distance and
Second support bar；And encapsulating housing, it covers control chip, power chip and a pair of support members.
According to another embodiment of the present invention, the voltage that the power integrated circuit packaging part is applied is less than 10 kilovolts.
Compared with prior art, lead frame provided in an embodiment of the present invention and the integrated electricity of power using the lead frame
Road packaging part can effectively prevent from producing electric arc creepage phenomenon between its input and output end, improve and survey when high_voltage isolation is tested
The accuracy rate and product yield of examination, and then reduce production cost.
Brief description of the drawings
Fig. 1 is the structural representation of an existing power integrated circuit packaging part.
Fig. 2 is the structural representation of the lead frame according to an embodiment of the invention for power integrated circuit encapsulation.
Fig. 3 is the structural representation of power integrated circuit packaging part according to an embodiment of the invention.
Embodiment
Spirit for a better understanding of the present invention, it is made furtherly below in conjunction with the part preferred embodiment of the present invention
It is bright.
Fig. 2 is the structural representation of the lead frame 20 according to an embodiment of the invention for power integrated circuit.
As shown in Fig. 2 the lead frame 20 according to an embodiment of the invention for power integrated circuit encapsulation includes：Outside
Frame 200 and multiple lead frame units 220.For the sake of simplicity, this schematic diagram only illustrates one of lead frame unit 220
Structure.There is relative the first side 202 and the second side 204, and the 3rd relative side 206 and in the lead frame unit 220
Four sides 208；And comprising：First chip loading seat 221, the second chip loading seat 222, multiple input pins 223, multiple outputs are drawn
Pin 224, and a pair of support members 225.The plurality of input pin 223 be connected to the first chip loading seat 221 and the first side 202 it
Between.The plurality of output pin 224 is connected between the second chip loading seat 222 and the second side 204.And this divides support member 225
The 3rd side 206 and the 4th side 208 of lead frame unit 220 are not extended from corresponding housing 220.In order to avoid high pressure every
Creep age distance is shorter during from test produces short circuit, and each support member 225 is designed as including first of a safe distance spaced apart
Strut 226 and second support bar 227.The safe distance that the first support bar 226 and second support bar 227 are spaced is not less than
650um, it is applicable to power integrated circuit of the applied voltage not less than 10 kilovolts and encapsulated.First support bar 226 and second
The shape of strut 227 is unlimited, and those skilled in the art can be designed to vertical bar shaped or the various shapes such as hook-shaped as needed.
When being packaged using the lead frame 20, the finishing after plastic packaging is handled firstly the need of to lead frame unit
The connecting bracket 240 of 220 first sides 202 and the second side 204 carries out cutting process, makes lead frame unit 220 and connecting bracket 240
Separation；Then carry out forming processes；Finally to the first support bar 226 and second support bar of the 3rd side 206 and the 4th side 208
227 epitaxial part is cut.This handling process order is advantageous in that：After lead frame 20 is cut, plays support and make
First support bar 226 and second support bar 227 can effectively avoid lead frame unit 220 from dropping on board.
Not only further, since support member 225 be designed as two support bars of separation and with entirety, and between two support bars
With minimum safe distance, when entering semiconductor package part 30 horizontal high voltage (such as 10KV) isolation test, effectively will avoid partly leading
The input of body packaging part 30 and the output end short-circuit conditions caused by creepage phenomenon.According to one embodiment of the invention, safety away from
During from more than 650um, semiconductor package part 30 can support 600V-11KV a wide range of control source.
Fig. 3 is the structural representation of power integrated circuit packaging part 30 according to an embodiment of the invention.
As shown in figure 3, according to an embodiment of the invention include a power integrated circuit packaging part in the embodiment of the present invention
30, it has relative the first side 202 and the second side 204, and the 3rd relative side 206 and the 4th side 208.The integrated electricity of the power
Road packaging part 30 includes：Control chip 302, power chip 304, multiple input pins 223, multiple output pins 224, a pair
Support member 225 and encapsulating housing (not shown).The control chip 302 is arranged on the first load bearing seat of chip 221 and the control core
Piece 302 is used to receive input signal.Power chip 304 is arranged on the second chip loading seat 222 and the power chip 304 is used for
Send output signal.Multiple input pins 223 are extended between the side 202 of the first chip loading seat 221 and first；Multiple outputs
Pin 224 is extended between the second chip loading seat 222 and the second side 204.A pair of support members 225 are located at the 3rd side 206 respectively
With the 4th side 208, and each support member 225 include be spaced apart a safe distance first support bar 226 and second support bar
227.Encapsulating housing (not shown) covering control chip 302, power chip 304, first support bar 226 and second support bar 227；
And the safe distance that the first support bar 226 and second support bar 227 are spaced is not less than 650um.
The technology contents and technical characterstic of the present invention have revealed that as above, but those skilled in the art still may base
Make a variety of replacements and modification without departing substantially from spirit of the present invention in teachings of the present invention and announcement.Therefore, protection model of the invention
Content disclosed in embodiment should be not limited to by enclosing, and should include various replacements and modification without departing substantially from the present invention, and be this patent
Application claims are covered.
Claims (7)
1. a kind of lead frame for power integrated circuit encapsulation, it includes：
Housing；And
Multiple lead frame units, wherein, each of the multiple lead frame unit has the first relative side and the
Two sides, and the 3rd relative side and the 4th side；Each lead frame unit includes：
First chip loading seat；
Second chip loading seat；
Multiple input pins, it is connected between first chip loading seat and first side；
Multiple output pins, it is connected between second chip loading seat and second side；
And
First support member and the second support member, first support member and second support member are located at the lead frame respectively
The 3rd side of unit and the 4th side；Wherein, first support member, which includes, is spaced apart first of a safe distance
Strut and second support bar, second support member include the 3rd support bar and the 4th support bar for separating a safe distance, institute
State first support bar and the second support bar one end be connected to the lead frame unit the 3rd side edge, institute
State the other end suspension of first support bar and the second support bar；One end of 3rd support bar and the 4th support bar
Be connected to the edge of the 4th side of the lead frame unit, the 3rd support bar and the 4th support bar it is another
End suspension.
2. it is according to claim 1 for power integrated circuit encapsulation lead frame, wherein the first support bar and
The safe distance at the second support bar interval is not less than 650 μm, and the 3rd support bar and the 4th support bar
The safe distance at interval is not less than 650 μm.
3. the lead frame according to claim 1 for power integrated circuit encapsulation, the first support bar, described the
Two support bars, the 3rd support bar and the 4th support bar be shaped as it is hook-shaped.
4. a kind of power integrated circuit packaging part, it has the first relative side and the second side, and relative the 3rd side and the 4th
Side；The power integrated circuit packaging part includes：
Control chip, it is configured to be arranged on the first chip loading seat；The control chip is used to receive input signal；
Power chip, it is configured to be arranged on the second chip loading seat；The power chip is used to send output signal；
Multiple input pins, extend between first chip loading seat and first side；
Multiple output pins, extend between second chip loading seat and second side；
First support member and the second support member, first support member and second support member integrate positioned at the power respectively
The 3rd side of circuit package and the 4th side；Wherein, first support member, which includes, is spaced apart a safe distance
First support bar and second support bar, second support member include the 3rd support bar for separating a safe distance and the 4th support
One end of bar, the first support bar and the second support bar is connected to the described 3rd of the power integrated circuit packaging part
The other end suspension of the edge of side, the first support bar and the second support bar；3rd support bar and the described 4th
One end of support bar is connected to the edge of the 4th side of the power integrated circuit packaging part, the 3rd support bar and institute
State the other end suspension of the 4th support bar；And
Encapsulating housing, it covers the control chip, the power chip, first support member and second support
Part.
5. power integrated circuit packaging part according to claim 4, wherein the first support bar and second support
The safe distance at bar interval is not less than 650 μm, and the peace at the 3rd support bar and the 4th support bar interval
Full distance is not less than 650 μm.
6. power integrated circuit packaging part according to claim 4, the first support bar, the second support bar, institute
State the 3rd support bar and the 4th support bar be shaped as it is hook-shaped.
7. power integrated circuit packaging part according to claim 4, its voltage applied is less than 10 kilovolts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510464941.5A CN105023905B (en) | 2015-07-31 | 2015-07-31 | Lead frame and the power integrated circuit packaging part using the lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510464941.5A CN105023905B (en) | 2015-07-31 | 2015-07-31 | Lead frame and the power integrated circuit packaging part using the lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105023905A CN105023905A (en) | 2015-11-04 |
| CN105023905B true CN105023905B (en) | 2018-01-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510464941.5A Active CN105023905B (en) | 2015-07-31 | 2015-07-31 | Lead frame and the power integrated circuit packaging part using the lead frame |
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| Country | Link |
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| CN (1) | CN105023905B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370382A (en) * | 2018-12-25 | 2020-07-03 | 恩智浦美国有限公司 | Hybrid lead frame for semiconductor die package with improved creepage distance |
| CN112133688A (en) * | 2020-11-25 | 2020-12-25 | 苏州纳芯微电子股份有限公司 | Packaging structure of multi-base-island lead frame |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230783A (en) * | 1998-03-27 | 1999-10-06 | 三菱电机株式会社 | Semiconductor device and lead fram for semiconductor device |
| CN101174603A (en) * | 2006-11-02 | 2008-05-07 | 株式会社瑞萨科技 | Semiconductor device and manufacturing method of the same |
| CN204857713U (en) * | 2015-07-31 | 2015-12-09 | 日月光封装测试(上海)有限公司 | Lead frame and power integrated circuit packaging part that uses this lead frame |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3853279B2 (en) * | 2002-02-01 | 2006-12-06 | シャープ株式会社 | Semiconductor laser device, manufacturing method thereof, and optical pickup using the same |
| CN101442036A (en) * | 2007-11-23 | 2009-05-27 | 华泰电子股份有限公司 | Conductor holder structure and application thereof |
-
2015
- 2015-07-31 CN CN201510464941.5A patent/CN105023905B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230783A (en) * | 1998-03-27 | 1999-10-06 | 三菱电机株式会社 | Semiconductor device and lead fram for semiconductor device |
| CN101174603A (en) * | 2006-11-02 | 2008-05-07 | 株式会社瑞萨科技 | Semiconductor device and manufacturing method of the same |
| CN204857713U (en) * | 2015-07-31 | 2015-12-09 | 日月光封装测试(上海)有限公司 | Lead frame and power integrated circuit packaging part that uses this lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105023905A (en) | 2015-11-04 |
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Effective date of registration: 20201229 Address after: No. 669, GuoShouJing Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Patentee after: Rirong semiconductor (Shanghai) Co.,Ltd. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 669 Patentee before: ASE ASSEMBLY & TEST (SHANGHAI) Ltd. |