CN204011408U - Lead frame and semiconductor package body - Google Patents
Lead frame and semiconductor package body Download PDFInfo
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- CN204011408U CN204011408U CN201420422438.4U CN201420422438U CN204011408U CN 204011408 U CN204011408 U CN 204011408U CN 201420422438 U CN201420422438 U CN 201420422438U CN 204011408 U CN204011408 U CN 204011408U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model relates to lead frame and semiconductor package body.Lead frame in an embodiment comprises: supporting disk (311), and it is configured as bearer circuit core (315); The first pin array (321), it is positioned at a side of supporting disk, and is configured as being connected to circuit core, and the first pin array has the first pin that is positioned at one end; Matrix busbar (331), it is positioned at a side identical with the first pin array of supporting disk, and near the first pin, and be configured as being connected to circuit core; The second pin array (322), it extends in the indent of matrix busbar, and is configured as being connected to circuit core; Wherein, matrix busbar is away from the central region of the electrical interconnection between the first pin and circuit core.Adopt the technical scheme in the utility model, can avoid, because the first pin array contacts with the connecting line lodging between circuit core the packaging body line fault that busbar causes, having improved the rate of finished products of semiconductor device.
Description
Technical field
The utility model relates generally to chip package, more specifically, relates to the encapsulation of lead frame (Lead Frame) structure.
Background technology
Lead frame is as the chip carrier of integrated circuit, it is a kind of electric connection that realizes chip internal circuit exit and outer lead by means of bonding material (spun gold, copper wire, aluminium wire), the key structure part that forms electrical loop, it has played the function served as bridge being connected with outer lead.In most semiconductor integrated block, all use lead frame, it is basic material important in electronics and information industry.
Utility model content
Existing lead frame and semiconductor packaging are still further improved.
In an embodiment of the present utility model, disclosed a kind of lead frame, this lead frame comprises: supporting disk, it is configured as bearer circuit core; The first pin array, it is positioned at a side of described supporting disk, and is configured the circuit core that is carried on described supporting disk for being connected to, and described the first pin array has the first pin that is positioned at one end; Matrix busbar, it is positioned at a side identical with described the first pin array of described supporting disk, and near described the first pin, and be configured the circuit core that is carried on described supporting disk for being connected to; The second pin array, it extends in the indent of described matrix busbar, and is configured the circuit core that is carried on described supporting disk for being connected to; Wherein, described matrix busbar is away from described the first pin and be carried on the central region of the electrical interconnection between the circuit core of described supporting disk.
In another embodiment, disclosed a kind of semiconductor package body, this semiconductor package body comprises: supporting disk; Circuit core, it is carried on described supporting disk; The first pin array, it is positioned at a side of described supporting disk, and is connected to described circuit core via connecting line, and described the first pin array has the first pin that is positioned at one end; Matrix busbar, it is positioned at a side identical with described the first pin array of described supporting disk, and near described the first pin, and be configured as be connected to described circuit core via connecting line; The second pin array, it extends in the indent of described matrix busbar, and is connected to described circuit core via connecting line; And packing colloid, its coated described supporting disk, circuit core, matrix busbar, the first pin array, the second pin array and connecting line; Wherein, described matrix busbar is away from the central region of the electric connection line between described the first pin and described circuit core.
In a specific embodiment of above-mentioned lead frame or semiconductor package body, the mid point between described the first pin and the respective pad of described circuit core and the minimum distance of described matrix busbar are over 8% of distance between described the first pin and the respective pad of described circuit core.
In a specific embodiment of above-mentioned lead frame or semiconductor package body, described matrix busbar towards the direction away from described the first pin depart from and away from the mid point between described the first pin and the respective pad of described circuit core to form an anti-short-circuit structure.
In a specific embodiment of above-mentioned lead frame or semiconductor package body, the described anti-short-circuit structure structure of cutting sth. askew that to be described matrix busbar form near the corner of described the first pin, this structure of cutting sth. askew is the angle between 15～60 degree from contiguous the first leads ends deflection one of described matrix busbar.
In a specific embodiment of above-mentioned lead frame or semiconductor package body, described angle is between 30～45 degree.
In a specific embodiment of above-mentioned lead frame or semiconductor package body, described anti-short-circuit structure is that described matrix busbar is near the level and smooth arcuate structure of corner's formation of described the first pin.
In a specific embodiment of above-mentioned lead frame or semiconductor package body, described anti-short-circuit structure is that described matrix busbar is near the hierarchic structure of corner's formation of described the first pin.
In a specific embodiment of above-mentioned lead frame or semiconductor package body, the distance between described matrix busbar and described circuit core is more than or equal to the distance between described the first pin array and described circuit core.
Adopt the technical scheme in the utility model, can avoid because the connecting line lodging between the first pin array and circuit core contacts the packaging body line fault that busbar causes, improve the rate of finished products that the lead-frame packages with bus-bar structure becomes semiconductor device.
Accompanying drawing explanation
By reference to the accompanying drawings, the detailed description about preferred embodiment of the present utility model below will be easier to understand.The utility model is explained by way of example, is not limited to accompanying drawing, and in accompanying drawing, similarly Reference numeral is indicated similar element.
Fig. 1 is the plane figure schematic diagram of a lead frame;
Fig. 2 A shows the part 200 of the lead frame of an embodiment;
Fig. 2 B shows lead-frame packages shown in Fig. 2 A and becomes the lateral plan after chip;
Fig. 3 A shows a grid of the lead frame of an embodiment;
Fig. 3 B shows the part of grid shown in Fig. 3 A;
Fig. 3 C is along the generalized section of dotted arrow A-A direction in Fig. 3 B;
Fig. 4 shows the part of the lead frame of another embodiment;
Fig. 5 shows the part of the lead frame of another embodiment;
Fig. 6 shows the part of the lead frame of another embodiment.
Embodiment
The detailed description of accompanying drawing is intended to the explanation as currently preferred embodiment of the present utility model, but not is intended to represent that the utility model can be achieved only form.It should be understood that function identical or that be equal to can be completed by the different embodiment that are intended to be contained within spirit and scope of the present utility model.
Fig. 1 is the plane figure schematic diagram of a lead frame 10.Lead frame 10 comprises the array that supporting disk 102 forms.The array arrangement of pin 104 in supporting disk 102 around.Pin array links together by connecting muscle 106.Connect muscle 106 and be connected to each other the framework that forms grid type, thereby lead frame 10 is connected into an integral body.Supporting disk 102 is connected to framework by support bar 103.It should be understood that Fig. 1 is only intended to schematically express the array of supporting disk 102, support bar 103, pin 104, connects the relative position relation between muscle 106, but not be intended to accurately show the dimension scale of each parts.Lead frame 10 is applicable to and miscellaneous part overall package, after encapsulating encapsulation, cut list (Singulation) remove connect muscle 106, crooked pin 104 can form each independently chip package again.
Fig. 2 A shows the part 200 of the metal lead wire frame of an embodiment.This lead frame comprises the framework of grid type, and part 200 is positioned at one of them grid.Square supporting disk 211 is connected to the frame of grid via the support bar 213 on four angles.A plurality of pins 204 are stretched from four epitaxial lateral overgrowths of supporting disk.The pin array of each side links together via connecting muscle 206, and is connected to the frame of grid.Supporting disk 211 is for bearer circuit core.In Fig. 2 A, also show such circuit core 215, it is the electric connection with pin array via wire 217 realizations.For simplicity's sake, the part that only shows circuit core 215 in figure is drawn contact and corresponding wire 217.Octangle dotted line frame 219 represents the edge of packaging body.Fig. 2 B shows lead-frame packages shown in Fig. 2 A and becomes the lateral plan after chip.After the scope encapsulating encapsulation of dotted line frame 219, cut the single company's of removal muscle 206 and disconnect being connected of support bar 213 and grid frame, more crooked pin 204 in encapsulating region (dotted line frame 219) part in addition, can form independently semiconductor package body.
Fig. 3 A shows the part 300 of the lead frame of an embodiment, and this part 300 can be one of them grid that is positioned at grid type framework.Supporting disk 311 is connected to the frame of grid via the support bar 313 on four angles.A plurality of pin array are arranged in the surrounding of supporting disk 311, and can link together via connecting muscle (not shown), and are connected to the frame of grid.Supporting disk 311, for bearer circuit core, also shows such circuit core 315 in Fig. 3 A.The busbar 331 and 332 that is substantially matrix is arranged in a side of supporting disk 311.Busbar can converge to the contact (for example surpassing 2 earth points) of drawing of a plurality of identical definition on circuit core 315 together, thereby has reduced taking pin.Circuit core 315 draw contact via the electric connection of wire 317 realizations and pin, busbar.For simplicity's sake, in figure, only show part wire 317.The two ends of matrix busbar are connected to grid type frame, form two pins, thereby are kept the stable of busbar in routing (wire bonding) stage.Between busbar 331 and 332, be placed with pin array 321, in the indent of busbar 331, be placed with pin array 322.Pin array 321 and 322 and circuit core 315 between distance roughly the same.After encapsulating encapsulation within pin array scope, cut the single company's of removal muscle and disconnect being connected of support bar 313 and grid frame, thereby form independently semiconductor package body.According to the particular type of encapsulation, may also comprise the step of the part beyond crooked pin is in encapsulating region.
Fig. 3 B shows the part of grid shown in Fig. 3 A, and Fig. 3 C is along the generalized section of dotted arrow A-A direction in Fig. 3 B.There is shown corresponding on the first pin 321a of pin array 321 one end and circuit core 315 draws corresponding on pin in connecting line 317a between contact (or claiming pad), pin array 322 and circuit core 315 and draws connecting line 317b between contact and a corresponding connecting line 317c who draws between contact on matrix busbar 331 and circuit core 315.Distance between circuit core 315 and busbar 331 inner edges is about d
31, the distance between busbar 331 inner edges and pin 322 is about d
32, and d
31significantly be greater than d
32.Such as but not limited to, d
31be not less than d
321.5 times, 2 times or more.Supporting disk 311 adopts sunk type design, makes circuit core 315 have the skew in level height with respect to pin array 322 (and 321) and busbar 331.Because packing colloid has certain viscosity property, in encapsulating program, each connecting line 317 can be along colloid flow direction, and example is the direction of arrow x as shown in Figure 3 B, produces lodging.More approach the middle part of connecting line, lodging degree is higher, especially connecting line 317a in lodging process, thereby more easily contact and cause packaging body short trouble with matrix busbar.Due to d
31significantly be greater than d
32, the inner edge of busbar 331 departs from and away from the central region of electric connection line between circuit core 315 and the first pin 321a towards the direction away from the first pin 321a, and near the corner of the first pin 321a, form the structure 331a that cuts sth. askew at busbar 331, this structure 331a that cuts sth. askew forms anti-short-circuit structure, make busbar 331 away from the mid point between the first pin 321a and the respective pad of circuit core 315, thereby avoided the packaging body line fault causing due to connecting line 317a lodging contact busbar 331, improved the rate of finished products that the lead-frame packages with bus-bar structure becomes semiconductor device.Mid point between the first pin 321a and the respective pad of circuit core 315 and the minimum distance of matrix busbar 331 are such as but not limited to surpassing 8% of distance between the first pin 321a and the respective pad of circuit core 315.The deflection angle that the structure of cutting sth. askew 331a is close to leads ends from it is conventionally between 15～60 degree, preferably between 30～45 degree.As shown in Figure 3A, busbar 322 also has with busbar 321 and similarly arranges (comprise and cutting sth. askew).
Fig. 4 shows the part of the lead frame of another embodiment.Circuit core 415 is carried on supporting disk 411.Pin array 421 is arranged in a side of supporting disk, and the busbar 431 that is substantially matrix is arranged between the support bar 413 of pin array 421 and homonymy.Busbar can converge to the contact (for example surpassing 2 earth points) of drawing of a plurality of identical definition on circuit core 415 together, thereby has reduced taking pin.The two ends of matrix busbar are connected to grid type frame, form two pins, thereby are kept the stable of busbar in the routing stage.In the indent of busbar 431, be placed with pin array 422.Pin array 421 and 422 and circuit core 415 between distance roughly the same.Circuit core 415 draw contact via the electric connection of wire 417 realizations and pin, busbar.For simplicity's sake, in figure, only showing corresponding on the first pin 421a of pin array 421 one end and circuit core 415 draws corresponding on pin in connecting line 417a between contact (or claiming pad), pin array 422 and circuit core 415 and draws connecting line 417b between contact and a corresponding connecting line 417c who draws between contact on matrix busbar 431 and circuit core 415.The distance there is shown between circuit core 415 and busbar 431 inner edges is about d
41, the distance between busbar 431 inner edges and pin 422 is about d
42, and d
41significantly be greater than d
42.Such as but not limited to, d
41be not less than d
421.5 times, 2 times or more.Because packing colloid has certain viscosity property, in encapsulating program, each connecting line 417 can be along colloid flow direction, and example is the direction of arrow x as shown in Figure 4, produces lodging.More approach the middle part of connecting line, lodging degree is higher, especially connecting line 417a in lodging process, thereby more easily contact and cause packaging body short trouble with matrix busbar.Due to d
41significantly be greater than d
42, the inner edge of busbar 431 departs from and away from the central region of electric connection line between circuit core 415 and the first pin 421a towards the direction away from the first pin 421a, and near the corner of the first pin 421a, form level and smooth arcuate structure 431a at busbar 431, this level and smooth arcuate structure 431a forms anti-short-circuit structure, make busbar 431 away from the mid point between the first pin 421a and the respective pad of circuit core 415, thereby avoided the packaging body line fault causing due to connecting line 417a lodging contact busbar 431, improved the rate of finished products that the lead-frame packages with bus-bar structure becomes semiconductor device.Mid point between the first pin 421a and the respective pad of circuit core 415 and the minimum distance of matrix busbar 431 are such as but not limited to surpassing 8% of distance between the first pin 421a and the respective pad of circuit core 415.After encapsulating encapsulation within pin array scope, cut the single company's of removal muscle and disconnect being connected of support bar 413 and grid frame, thereby form independently semiconductor package body.According to the particular type of encapsulation, may also comprise the step of the part beyond crooked pin is in encapsulating region.
Fig. 5 shows the part of the lead frame of another embodiment.Circuit core 515 is carried on supporting disk 511.Pin array 521 is arranged in a side of supporting disk, and the busbar 531 that is substantially matrix is arranged between the support bar 513 of pin array 521 and homonymy.Busbar can converge to the contact (for example surpassing 2 earth points) of drawing of a plurality of identical definition on circuit core 515 together, thereby has reduced taking pin.The two ends of matrix busbar are connected to grid type frame, form two pins, thereby are kept the stable of busbar in the routing stage.In the indent of busbar 531, be placed with pin array 522.Pin array 521 and 522 and circuit core 515 between distance roughly the same.Circuit core 515 draw contact via the electric connection of wire 517 realizations and pin, busbar.For simplicity's sake, in figure, only showing corresponding on the first pin 521a of pin array 521 one end and circuit core 515 draws corresponding on pin in connecting line 517a between contact (or claiming pad), pin array 522 and circuit core 515 and draws connecting line 517b between contact and a corresponding connecting line 517c who draws between contact on matrix busbar 531 and circuit core 515.Because packing colloid has certain viscosity property, in encapsulating program, each connecting line 517 can be along colloid flow direction, and example is the direction of arrow x as shown in Figure 5, produces lodging.More approach the middle part of connecting line, lodging degree is higher, especially connecting line 517a in lodging process, thereby more easily contact and cause packaging body short trouble with matrix busbar.The inner edge of busbar 531 departs from and away from the central region of electric connection line between circuit core 515 and the first pin 521a towards the direction away from the first pin 521a, and the formation hierarchic structure 531a of corner at busbar 531 near the first pin 521a, this hierarchic structure 531a forms anti-short-circuit structure, make busbar 531 away from the mid point between the first pin 521a and the respective pad of circuit core 515, thereby avoided the packaging body line fault causing due to connecting line 517a lodging contact busbar 531, improved the rate of finished products that the lead-frame packages with bus-bar structure becomes semiconductor device.Mid point between the first pin 521a and the respective pad of circuit core 515 and the minimum distance of matrix busbar 531 are such as but not limited to surpassing 8% of distance between the first pin 521a and the respective pad of circuit core 515.After encapsulating encapsulation within pin array scope, cut the single company's of removal muscle and disconnect being connected of support bar 513 and grid frame, thereby form independently semiconductor package body.According to the particular type of encapsulation, may also comprise the step of the part beyond crooked pin is in encapsulating region.
Fig. 6 shows the part of the lead frame of another embodiment.Circuit core 615 is carried on supporting disk 611.Pin array 621 is arranged in a side of supporting disk, and the busbar 631 that is substantially matrix is arranged between the support bar 613 of pin array 621 and homonymy.Busbar can converge to the contact (for example surpassing 2 earth points) of drawing of a plurality of identical definition on circuit core 615 together, thereby has reduced taking pin.The two ends of matrix busbar are connected to grid type frame, form two pins, thereby are kept the stable of busbar in the routing stage.In the indent of busbar 631, be placed with pin array 622.Distance between busbar 631 and circuit core 615 is no more than the distance between pin array 621 and circuit core 615.Circuit core 615 draw contact via the electric connection of wire 617 realizations and pin, busbar.For simplicity's sake, in figure, only showing corresponding on the first pin 621a of pin array 621 one end and circuit core 615 draws corresponding on pin in connecting line 617a between contact (or claiming pad), pin array 622 and circuit core 615 and draws connecting line 617b between contact and a corresponding connecting line 617c who draws between contact on matrix busbar 631 and circuit core 615.In encapsulating program, each connecting line 617 can produce lodging along colloid flow direction.More approach the middle part of connecting line, lodging degree is higher, especially connecting line 617a in lodging process, thereby more easily contact and cause packaging body short trouble with matrix busbar.Because the distance between busbar 631 and circuit core 615 is more than or equal to the distance between pin array 621 and circuit core 615, thereby avoided the packaging body line fault causing due to connecting line 617 lodging contact busbars 631, improved the rate of finished products that the lead-frame packages with bus-bar structure becomes semiconductor device.After encapsulating encapsulation within pin array scope, cut the single company's of removal muscle and disconnect being connected of support bar 613 and grid frame, thereby form independently semiconductor package body.According to the particular type of encapsulation, may also comprise the step of the part beyond crooked pin is in encapsulating region.
Although illustrated and described different embodiment of the present utility model, the utility model is not limited to these embodiment.The technical characterictic only occurring in some claim or embodiment does not also mean that and can not combine to realize useful new technical scheme with other features in other claims or embodiment.In the situation that not deviating from as the described spirit and scope of the present utility model of claims, many modifications, change, distortion, to substitute and be equal to be obvious to those skilled in the art.
Claims (16)
1. a lead frame, is characterized in that, this lead frame comprises:
Supporting disk, it is configured as bearer circuit core;
The first pin array, it is positioned at a side of described supporting disk, and is configured the circuit core that is carried on described supporting disk for being connected to, and described the first pin array has the first pin that is positioned at one end;
Matrix busbar, it is positioned at a side identical with described the first pin array of described supporting disk, and near described the first pin, and be configured the circuit core that is carried on described supporting disk for being connected to;
The second pin array, it extends in the indent of described matrix busbar, and is configured the circuit core that is carried on described supporting disk for being connected to;
Wherein, described matrix busbar is away from described the first pin and be carried on the central region of the electrical interconnection between the circuit core of described supporting disk.
2. lead frame as claimed in claim 1, it is characterized in that described the first pin and be carried on mid point between the respective pad of circuit core of described supporting disk and the minimum distance of described matrix busbar surpasses described the first pin and is carried on 8% of distance between the respective pad of circuit core of described supporting disk.
3. lead frame as claimed in claim 2, it is characterized in that, described matrix busbar departs from and away from described the first pin be carried on mid point between the respective pad of circuit core of described supporting disk to form an anti-short-circuit structure towards the direction away from described the first pin.
4. lead frame as claimed in claim 3, it is characterized in that, the described anti-short-circuit structure structure of cutting sth. askew that to be described matrix busbar form near the corner of described the first pin, this structure of cutting sth. askew is the angle between 15～60 degree from contiguous the first leads ends deflection one of described matrix busbar.
5. lead frame as claimed in claim 4, is characterized in that, described angle is between 30～45 degree.
6. lead frame as claimed in claim 3, is characterized in that, described anti-short-circuit structure is that described matrix busbar is near the level and smooth arcuate structure of corner's formation of described the first pin.
7. lead frame as claimed in claim 3, is characterized in that, described anti-short-circuit structure is that described matrix busbar is near the hierarchic structure of corner's formation of described the first pin.
8. lead frame as claimed in claim 2, is characterized in that, described matrix busbar and be carried on distance between the circuit core of described supporting disk and be more than or equal to described the first pin array and be carried on the distance between the circuit core of described supporting disk.
9. a semiconductor package body, is characterized in that, this semiconductor package body comprises:
Supporting disk;
Circuit core, it is carried on described supporting disk;
The first pin array, it is positioned at a side of described supporting disk, and is connected to described circuit core via connecting line, and described the first pin array has the first pin that is positioned at one end;
Matrix busbar, it is positioned at a side identical with described the first pin array of described supporting disk, and near described the first pin, and be configured as be connected to described circuit core via connecting line;
The second pin array, it extends in the indent of described matrix busbar, and is connected to described circuit core via connecting line; And
Packing colloid, its coated described supporting disk, circuit core, matrix busbar, the first pin array, the second pin array and connecting line;
Wherein, described matrix busbar is away from the central region of the electric connection line between described the first pin and described circuit core.
10. semiconductor package body as claimed in claim 9, it is characterized in that, the mid point between described the first pin and the respective pad of described circuit core and the minimum distance of described matrix busbar are over 8% of distance between described the first pin and the respective pad of described circuit core.
11. semiconductor package body as claimed in claim 10, it is characterized in that, described matrix busbar towards the direction away from described the first pin depart from and away from the mid point between described the first pin and the respective pad of described circuit core to form an anti-short-circuit structure.
12. semiconductor package body as claimed in claim 11, it is characterized in that, the described anti-short-circuit structure structure of cutting sth. askew that to be described matrix busbar form near the corner of described the first pin, this structure of cutting sth. askew is the angle between 15～60 degree from contiguous the first leads ends deflection one of described matrix busbar.
13. semiconductor package body as claimed in claim 12, is characterized in that, described angle is between 30～45 degree.
14. semiconductor package body as claimed in claim 11, is characterized in that, described anti-short-circuit structure is that described matrix busbar is near the level and smooth arcuate structure of corner's formation of described the first pin.
15. semiconductor package body as claimed in claim 11, is characterized in that, described anti-short-circuit structure is that described matrix busbar is near the hierarchic structure of corner's formation of described the first pin.
16. semiconductor package body as claimed in claim 10, is characterized in that, the distance between described matrix busbar and described circuit core is more than or equal to the distance between described the first pin array and described circuit core.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420422438.4U CN204011408U (en) | 2014-07-29 | 2014-07-29 | Lead frame and semiconductor package body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420422438.4U CN204011408U (en) | 2014-07-29 | 2014-07-29 | Lead frame and semiconductor package body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204011408U true CN204011408U (en) | 2014-12-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420422438.4U Active CN204011408U (en) | 2014-07-29 | 2014-07-29 | Lead frame and semiconductor package body |
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| Country | Link |
|---|---|
| CN (1) | CN204011408U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103620A (en) * | 2014-07-29 | 2014-10-15 | 日月光封装测试(上海)有限公司 | Lead frame and semiconductor packaging body |
-
2014
- 2014-07-29 CN CN201420422438.4U patent/CN204011408U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103620A (en) * | 2014-07-29 | 2014-10-15 | 日月光封装测试(上海)有限公司 | Lead frame and semiconductor packaging body |
| CN104103620B (en) * | 2014-07-29 | 2017-02-15 | 日月光封装测试(上海)有限公司 | Lead frame and semiconductor packaging body |
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Effective date of registration: 20161230 Address after: 201201 room T3-100201, No. 5001 East Road, Shanghai, Pudong New Area Patentee after: Advanced integrated circuit manufacturing (Chinese) Co. Ltd. Patentee after: ASE Assembly & Test (Shanghai) Ltd. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 669 Patentee before: ASE Assembly & Test (Shanghai) Ltd. |
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Effective date of registration: 20170401 Address after: 201203 Shanghai city Chinese (Shanghai) free trade zone 669 GuoShouJing Road No. six building Patentee after: ASE Assembly & Test (Shanghai) Limited Address before: 201201 room T3-100201, No. 5001 East Road, Shanghai, Pudong New Area Patentee before: Advanced integrated circuit manufacturing (Chinese) Co. Ltd. Patentee before: ASE Assembly & Test (Shanghai) Limited |