CN203800033U - Leading wire frame and semiconductor packaging body - Google Patents

Leading wire frame and semiconductor packaging body Download PDF

Info

Publication number
CN203800033U
CN203800033U CN201320892708.3U CN201320892708U CN203800033U CN 203800033 U CN203800033 U CN 203800033U CN 201320892708 U CN201320892708 U CN 201320892708U CN 203800033 U CN203800033 U CN 203800033U
Authority
CN
China
Prior art keywords
support bar
supporting disk
lead frame
semiconductor package
package body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201320892708.3U
Other languages
Chinese (zh)
Inventor
周素芬
Original Assignee
Ase Assembly & Test (shanghai) Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ase Assembly & Test (shanghai) Ltd filed Critical Ase Assembly & Test (shanghai) Ltd
Priority to CN201320892708.3U priority Critical patent/CN203800033U/en
Application granted granted Critical
Publication of CN203800033U publication Critical patent/CN203800033U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model relates to a leading wire frame and a semiconductor packaging body; an embodiment discloses the leading wire frame comprising the following structures: a framework; a support disc connected with the framework through a support rod; an array connected with pins of the framework through connecting ribs, and the array is configured to connect with a circuit core supported by the support disc. The support rod and/or the support disc is provided with a fastening member; the fastening member is configured to fix the leading wire frame with a packaging rubber body, and is good for improving yield of finished product chips.

Description

Lead frame and semiconductor package body
Technical field
The utility model relates generally to chip package, more specifically, relates to the encapsulation of lead frame (Lead Frame) structure.
Background technology
Lead frame is as the chip carrier of integrated circuit, it is a kind of electrical connection that realizes chip internal circuit exit and outer lead by means of bonding material (spun gold, aluminium wire, copper wire), the key structure part that forms electric loop, it has played the function served as bridge being connected with outer lead.In most semiconductor integrated block, all use lead frame, it is basic material important in electronics and information industry, mainly by mould punching method and chemical etching method, produces.
Utility model content
A main purpose of the present utility model is to provide a kind of new lead frame scheme, further to improve performance.
An embodiment discloses a kind of lead frame, and this lead frame comprises: framework; Via support bar, be connected to the supporting disk of described framework; Via company's muscle, be connected to the array of the pin of described framework, be configured to connect the circuit core that is carried on described supporting disk; Wherein, on described support bar and/or supporting disk, there is clamp structure, be configured to the combination of fastening described lead frame and packing colloid.
In various embodiment, clamp structure comprises bifurcated, lateral protrusion, through hole or its combination, in packaging body, all by the packing colloid of framework two sides up/down perforation, is coated.
In one embodiment, on the support bar of lead frame, there is lateral protrusion.
In one embodiment, the clamp structure of lead frame comprises that described support bar is with respect to the distal portion of described supporting disk, the bifurcated within packaging area.
In one embodiment, the clamp structure of lead frame comprises through hole, and it is positioned on support bar and/or supporting disk.
In one embodiment, lead frame arbitrary support bar on there are a plurality of through holes.
In one embodiment, lead frame in described pin array, described support bar, be coated with at least in part bonding coating on respect to the close end of described supporting disk and described supporting disk, described clamp structure comprises the through hole in the bonding cladding region of support bar.
In one embodiment, the area of the bonding cladding region of the support bar of lead frame is not less than 20% of the support bar gross area, and the area of the through hole in the bonding cladding region of described support bar is within 20%~30% scope of the area of the bonding cladding region of described support bar.
In one embodiment, in the pin array of lead frame, a pin distal portion has projection, and this distance that projects into packaging body edge is not less than 0.1mm, and width is not less than 0.1mm.
An embodiment discloses a kind of semiconductor package body, and it comprises: supporting disk and support bar; Circuit core, it is fixed on described supporting disk; Pin array, it is positioned at around described supporting disk and is electrically connected at described circuit core; Packing colloid, its coated described supporting disk, support bar, circuit core, and be partly coated described pin array; Wherein, on described support bar and/or supporting disk, there is clamp structure, be configured to the combination of fastening described supporting disk and packing colloid.
In an embodiment, the described clamp structure in semiconductor package body comprises the lateral protrusion on described support bar.
In an embodiment, the described clamp structure in semiconductor package body comprises that described support bar is with respect to the distal portion of described supporting disk, the bifurcated within packaging area.
In an embodiment, the described clamp structure in semiconductor package body comprises the through hole on described support bar and/or supporting disk.
In an embodiment, on the arbitrary support bar in semiconductor package body, there are a plurality of through holes.
In an embodiment, semiconductor package body is coated with bonding coating in described pin array, described support bar on respect to the close end of described supporting disk and described supporting disk at least in part, and described clamp structure comprises the through hole in the bonding cladding region of support bar.
In an embodiment, the area of the through hole in the bonding cladding region of the support bar in semiconductor package body is within 20%~30% scope of the area of the bonding cladding region of described support bar.
In an embodiment, in semiconductor package body, in described pin array, a pin distal portion has projection, and this distance that projects into described semiconductor package body edge is not less than 0.1mm, and width is not less than 0.1mm.
Accompanying drawing explanation
By reference to the accompanying drawings, the detailed description about preferred embodiment of the present utility model below will be easier to understand.The utility model is explained by way of example, is not limited to accompanying drawing, and in accompanying drawing, similarly Reference numeral is indicated similar element.
Fig. 1 is the plane figure schematic diagram of a lead frame;
Fig. 2 shows the part 200 of the lead frame of an embodiment;
Fig. 2 A shows lead-frame packages shown in Fig. 2 and becomes the lateral plan after chip;
Fig. 2 B shows a kind of distortion of lead frame shown in Fig. 2;
Fig. 3 shows the part 300 of the lead frame of an embodiment;
Fig. 3 A shows the part of Fig. 3;
Fig. 4 shows the part 400 of the lead frame of an embodiment;
Fig. 4 A shows the part of Fig. 4;
Fig. 5 shows the part 500 of the lead frame of an embodiment;
Fig. 6 shows the part 600 of the lead frame of an embodiment;
Fig. 6 A shows a kind of distortion of lead frame shown in Fig. 6;
Fig. 7 A shows the part 600 of the lead frame of an embodiment;
Fig. 7 B shows a kind of distortion of lead frame shown in Fig. 7 A;
Fig. 7 C shows the another kind distortion of lead frame shown in Fig. 7 A.
Embodiment
The detailed description of accompanying drawing is intended to the explanation as currently preferred embodiment of the present utility model, but not is intended to represent that the utility model can be achieved only form.It should be understood that function identical or that be equal to can be completed by the different embodiment that are intended to be contained within spirit and scope of the present utility model.
Fig. 1 is the plane figure schematic diagram of a lead frame 10.Lead frame 10 comprises the array that supporting disk 102 forms.The array arrangement of pin 104 in supporting disk 102 around.Pin array links together by connecting muscle 106.Connect muscle 106 and be connected to each other the framework that forms grid type, thereby lead frame 10 is connected into an integral body.Supporting disk 102 is connected to framework by support bar 103.It should be understood that Fig. 1 is only intended to the array of schematically illustrated supporting disk 102, support bar 103, pin 104, connects the relative position relation between muscle 106, but not be intended to accurately show the dimension scale of each parts.Lead frame 10 is applicable to and miscellaneous part overall package, after encapsulating encapsulation, cut list (Singulation) remove connect muscle 106, crooked pin 104 can form each independently chip package again.
Fig. 2 shows the part 200 of the metal lead wire frame of an embodiment.This lead frame comprises the framework of grid type, and part 200 is positioned at one of them grid.Square supporting disk 211 is connected to the frame of grid via the support bar 213 on four angles.A plurality of pins 204 are stretched from four epitaxial lateral overgrowths of supporting disk.The pin array of each side links together via connecting muscle 206, and is connected to the frame of grid.Supporting disk 211 is for bearer circuit core (being chip).In Fig. 2, also show such circuit core 215, it is the electrical connection with pin array via wire 217 realizations.For simplicity's sake, the part that only shows circuit core 215 in figure is drawn contact and corresponding wire 217.Octangle dotted line frame 219 represents the edge of packaging body.After the scope encapsulating encapsulation of dotted line frame 219, cut the single company's of removal muscle 206 and disconnect being connected of support bar 213 and grid frame, again crooked pin 204 in encapsulating region (dotted line frame 219) part in addition, can form independently semiconductor package body (chip package).Fig. 2 A shows the lateral plan of packaged chip, outside visible packing colloid 219 and the pin 204 of comprising.Support bar 213 has two symmetrical lateral protrusion 221 on the position within the distal portion with respect to supporting disk, packaging area 219 scopes.Lateral protrusion 221 is securely combined with packing colloid, hindered the stress that for example produces along the propagation of the length direction of support bar 213 when cutting list, reduce stress and shaken supporting disk 211, core circuit 215, conductive connecting line 217 and the risk of defective chip, contributed to improve the yields of finished chip.
In other embodiment, lateral protrusions is not symmetrical arranged, as long as can play packing colloid fastening effect.
Fig. 2 B shows a kind of distortion of lead frame shown in Fig. 2.In this distortion, on the position of support bar 213 within the distal portion with respect to supporting disk, packaging area 219 scopes, except thering are two symmetrical lateral protrusion 221, also there is one and be positioned at the middle through hole 241 of two lateral protrusion 221.Packing colloid is also by through hole 241 up/down perforations, make the combination of support bar 213, supporting disk 211 and packing colloid more fastening, hindered to a greater degree the stress that for example produces along the propagation of the length direction of support bar 213 when cutting list, reduce stress and shaken internal structure and the risk of defective chip, contributed to further to improve the yields of finished chip.In some other distortion, through hole 241 can also be positioned at the middle part of support bar 213 or with respect to the close end of supporting disk 211, or on support bar 213, has a plurality of through holes 241.
Fig. 3 shows the part 300 of the lead frame of an embodiment, and Fig. 3 A shows a jiao of this part 300.This lead frame comprises the framework of grid type, and part 300 is positioned at one of them grid.Square supporting disk 311 is connected to the frame of grid via the support bar 313 on four angles.A plurality of pins 304 are stretched from four epitaxial lateral overgrowths of supporting disk.The pin array of each side links together via connecting muscle 306, and is connected to the frame of grid.Supporting disk 311 is for bearer circuit core.In Fig. 3, also show such circuit core 315, it is the electrical connection with pin array via wire 317 realizations.For simplicity's sake, the part that only shows circuit core 315 in figure is drawn contact and corresponding wire 317.Octangle dotted line frame 319 represents the edge of packaging body.After the scope encapsulating encapsulation of dotted line frame 319, cut the single company's of removal muscle 306 and disconnect being connected of support bar 313 and grid frame, again crooked pin 304 in encapsulating region (dotted line frame 319) part in addition, can form independently semiconductor packages (chip package).Support bar 313 has two bifurcateds 331 on the position within the distal portion with respect to supporting disk, packaging area 319 scopes, also has two lateral protrusion 321 on each bifurcated 331.The shape of support bar 313 these end junctions of three roads is subject to the clamping of the packing colloid of three side up/down perforations, makes support bar 313 very firm with the combination of packing colloid.And bifurcated 331 has changed the conduction orientation of stress, reduced the impact on internal structure.Lateral protrusion 321 is thrust packing colloid from the side of bifurcated 331, makes support bar 313 more fastening with the combination of packing colloid.Finished chip thereby promoted yields.In figure, also show the projection 324 within pin 304 distal portion, packaging area 319 scopes, it contributes to pin 304 fixing in packing colloid.Lateral protrusion 321 is d to the distance at packaging body edge 319 31, to the distance at bifurcated 331 edges, be d 32.Projection 324 on pin 304 is d to the distance at packaging body edge 319 33, width is d 34.D 31, d 33and d 34all be not less than 0.1mm, d 32be not less than 0.15mm, so that enough locked mode adhesion and enough support forces to be provided.Angle between the lateral protrusion 321 of bifurcated 331 and contiguous another bifurcated is acute angle, and better locked mode adhesion can be provided.
Fig. 4 shows the part 400 of the lead frame of an embodiment, and Fig. 4 A shows a jiao of this part 400.This lead frame comprises the framework of grid type, and part 400 is positioned at one of them grid.Square supporting disk 411 is connected to the frame of grid via the support bar 413 on four angles.A plurality of pins 404 are stretched from four epitaxial lateral overgrowths of supporting disk.The pin array of each side links together via connecting muscle 406, and is connected to the frame of grid.Supporting disk 411 is for bearer circuit core.In Fig. 4, also show such circuit core 415, it is the electrical connection with pin array via conductive connecting line 417 realizations.For simplicity's sake, the part that only shows circuit core 415 in figure is drawn contact and corresponding conductive connecting line 417.Dotted line frame 419 represents the edge of packaging body.After the scope encapsulating encapsulation of dotted line frame 419, cut the single company's of removal muscle 406 and disconnect being connected of support bar 413 and grid frame, again crooked pin 404 in encapsulating region (dotted line frame 419) part in addition, can form independently semiconductor package body (chip package).Support bar 413 is three fork-shapeds on the position within the distal portion with respect to supporting disk, packaging area 419 scopes, and two bifurcateds 431 meet at right angles substantially and are connected respectively to the frame of grid, and the width of two bifurcateds 431 is all not more than mobile jib 413 width half.At the root of trident, the both sides of mobile jib 413 have respectively a lateral protrusion 421.The centre of trident also has a through hole 441.The shape of support bar 413 these end junctions of three roads is subject to the bolt-lock of the packing colloid of up/down perforation in the clamping, through hole 441 of the packing colloid of three side up/down perforations, makes support bar 413 very fastening with the combination of packing colloid.The stress that blocks hardware generation is proportionate with the width of hardware substantially.Substantially rectangular bifurcated 431 has changed the conduction orientation of stress, is all not more than again half of mobile jib 413 width due to two bifurcated 431 width, makes greatly to reduce along the stress of mobile jib 413 conduction.Thereby reduced stress and shake internal structure and the risk of defective chip, improved the yields of finished chip.In figure, also show the projection 424 within pin 404 distal portion, packaging area 419 scopes, it contributes to pin 404 fixing in packing colloid.Lateral protrusion 421 is d to the distance at packaging body edge 419 41, to the distance at bifurcated 431 edges, be d 42.Projection 424 on pin 404 is d to the distance at packaging body edge 419 43, width is d 44.D 41, d 43and d 44all be not less than 0.1mm, d 42be not less than 0.15mm, so that enough locked mode adhesion and enough support forces to be provided.Between two bifurcateds 431, also have a trapezoidal protrusion 423, the angle between bifurcated 431 and projection 423 is acute angle, and through hole 441 is polygon, so that better locked mode adhesion to be provided.
Fig. 5 shows the part 500 of the lead frame of an embodiment.This lead frame comprises the framework of grid type, and part 500 is positioned at one of them grid.Rectangle supporting disk 511 is connected to the frame of grid via the support bar 513 of length direction both sides.A plurality of pins 504 stretch out in the Width both sides of supporting disk 511, line up array.The pin array of each side links together via connecting muscle 506, and is connected to the frame of grid.Supporting disk 511 is for bearer circuit core.In Fig. 5, also show such circuit core 515, it is the electrical connection with pin array via conductive connecting line 517 realizations.For simplicity's sake, the part that only shows circuit core 515 in figure is drawn contact and corresponding conductive connecting line 517.Dotted line frame 519 represents the edge of packaging body.After the scope encapsulating encapsulation of dotted line frame 519, cut the single company's of removal muscle 506 and disconnect being connected of support bar 513 and grid frame, more crooked pin 504 in encapsulating region (dotted line frame 519) part in addition, can form independently semiconductor package body.Support bar 513 has two symmetrical lateral protrusion 521 on the position within the distal portion with respect to supporting disk 511, packaging area 519 scopes, also has through hole 541 between two lateral protrusion.Lateral protrusion 521 is securely combined with packing colloid, and in through hole 541, the packing colloid of up/down perforation forms bolt-lock to support bar 513, hindered the stress that for example produces along the propagation of the length direction of support bar 513 when cutting list, reduce stress and shaken the internal structure such as supporting disk 511, core circuit 515, conductive connecting line 517 and the risk of defective chip, contributed to improve the yields of finished chip.In figure, also show the projection that pin 504 roots extend to both sides, this width (length extending out from pin 504) that projects into distance He this projection at packaging body edge 519 is all not less than 0.1mm, and it contributes to pin 504 fixing in packing colloid.Lateral protrusion 521 is not less than 0.1mm to the distance at packaging body edge 519, and the distance extending laterally away from support bar 513 is not less than 0.15mm.These projections can provide enough locked mode adhesion and enough support forces.Lateral protrusion 521 is acute angle with an angle of support bar 513, and better locked mode adhesion can be provided.
Fig. 6 shows the part 600 of the lead frame of an embodiment.This lead frame comprises the framework of grid type, and part 600 is positioned at one of them grid.Rectangle supporting disk 611 is connected to the frame of grid via the support bar 613 of length direction both sides.A plurality of pins 604 stretch out in the Width both sides of supporting disk 611, line up array.The pin array of each side links together via connecting muscle 606, and is connected to the frame of grid.Supporting disk 611 is for bearer circuit core.Dotted line frame 619 represents the edge of packaging body.Shadow region 620 within dotted line frame 619 scopes represents bonding coating.In Fig. 6, also show the circuit core 615 that is carried on supporting disk 611, it is realized and the electrical connection that has covered the pin array of bonding coating via conductive connecting line 617.For simplicity's sake, the part that only shows circuit core 615 in figure is drawn contact and corresponding conductive connecting line 617.After the scope encapsulating encapsulation of dotted line frame 619, cut the single company's of removal muscle 606 and disconnect being connected of support bar 613 and grid frame, more crooked pin 604 in encapsulating region (dotted line frame 619) part in addition, can form independently semiconductor package body.On support bar 613, there is the long through-hole 643 extending along its length.The area of through hole 643 is within 20%~30% scope of the area of the bonding cladding region of support bar 613.Packing colloid up/down perforation in through hole 643, the bolt-lock of formation to support bar 613, and clamp securely support bar 613, hindered on the one hand the stress that for example produces along the propagation of the length direction of support bar 613 when cutting list, reduce stress and shaken internal structure and the risk of defective chip, also partly overcome on the other hand the adhesion of bonding coating and packing colloid compared with the weak and easy problem that produces lamination at bonding cladding region.These advantages all contribute to improve the yields of finished chip.
Fig. 6 A shows a kind of distortion of lead frame shown in Fig. 6.In this distortion, the long through-hole 643 on support bar 613, the bonding cladding region of supporting disk 611 on edge, surrounding also has the turning shape through hole 644 in four bights and the through hole 645 of four middle side edge.Packing colloid, by these through hole up/down perforations, is packaged in supporting disk 611 wherein securely, has overcome the adhesion of bonding coating and packing colloid compared with the weak and easy problem that produces lamination at bonding cladding region.
Fig. 7 A shows the part 700 of the metal lead wire frame of an embodiment.This lead frame comprises the framework of grid type, and part 700 is positioned at one of them grid.Square supporting disk 711 is connected to the frame of grid via the support bar 713 on four angles.A plurality of pins 704 are stretched from four epitaxial lateral overgrowths of supporting disk.The pin array of each side links together via connecting muscle 706, and is connected to the frame of grid.Supporting disk 711 is for bearer circuit core.Dotted line frame 719 represents the edge of packaging body.Octagon shadow region 720 represents bonding cladding region.In Fig. 7 A, also show the circuit core 715 that is carried on supporting disk 711, it is realized and the electrical connection that has covered the pin array of bonding coating via conductive connecting line 717.For simplicity's sake, the part that only shows circuit core 715 in figure is drawn contact and corresponding conductive connecting line 717.After the scope encapsulating encapsulation of dotted line frame 719, cut the single company's of removal muscle 706 and disconnect being connected of support bar 713 and grid frame, more crooked pin 704 in encapsulating region (dotted line frame 719) part in addition, can form independently semiconductor package body.Within bonding cladding region on support bar 713, there is the long through-hole 743 extending along its length.The area of through hole 743 is within 20%~30% scope of the area of the bonding cladding region of support bar 713.Packing colloid up/down perforation in through hole 743, the bolt-lock of formation to support bar 713, and clamp securely support bar 713, hindered on the one hand the stress that for example produces along the propagation of the length direction of support bar 713 when cutting list, reduce stress and shaken internal structure and the risk of defective chip, also partly overcome on the other hand the adhesion of bonding coating and packing colloid compared with the weak and easy problem that produces lamination at bonding cladding region.These advantages all contribute to improve the yields of finished chip.
Fig. 7 B shows a kind of distortion of lead frame shown in Fig. 7 A.In this distortion, support bar 713 is except the long through-hole 743 in bonding cladding region, and the region outside bonding coating also has two long through-holes 744.
Fig. 7 C shows the another kind distortion of lead frame shown in Fig. 7 A.In this distortion, support bar 713 has the through hole 745 extending along its length, and this through hole 745 extends to the far-end outside bonding region within bonding coating always.
Although illustrated and described different embodiment of the present utility model, the utility model is not limited to these embodiment.The technical characterictic only occurring in some claim or embodiment does not also mean that and can not combine to realize useful new technical scheme with other features in other claims or embodiment.In the situation that not deviating from as the described spirit and scope of the present utility model of claims, many modifications, change, distortion, to substitute and be equal to be obvious to those skilled in the art.

Claims (16)

1. a lead frame, is characterized in that, this lead frame comprises:
Framework;
Via support bar, be connected to the supporting disk of described framework;
Via company's muscle, be connected to the pin array of described framework, be configured to connect the circuit core that is carried on described supporting disk;
Wherein, on described support bar and/or supporting disk, there is clamp structure, be configured to the combination of fastening described lead frame and packing colloid.
2. lead frame as claimed in claim 1, is characterized in that, described clamp structure comprises the lateral protrusion on described support bar.
3. lead frame as claimed in claim 1, is characterized in that, described clamp structure comprises that described support bar is with respect to the distal portion of described supporting disk, the bifurcated within packaging area.
4. lead frame as claimed in claim 1, is characterized in that, described clamp structure comprises the through hole on described support bar and/or supporting disk.
5. lead frame as claimed in claim 4, is characterized in that, has a plurality of through holes on arbitrary support bar.
6. lead frame as claimed in claim 1, it is characterized in that, in described pin array, described support bar, be coated with at least in part bonding coating on respect to the close end of described supporting disk and described supporting disk, described clamp structure comprises the through hole in the bonding cladding region of support bar.
7. lead frame as claimed in claim 6, is characterized in that, the area of the through hole in the bonding cladding region of described support bar is within 20%~30% scope of the area of the bonding cladding region of described support bar.
8. lead frame as claimed in claim 1, is characterized in that, in described pin array, a pin distal portion has projection, and this distance that projects into packaging body edge is not less than 0.1mm, and width is not less than 0.1mm.
9. a semiconductor package body, is characterized in that, this semiconductor package body comprises:
Supporting disk and support bar;
Circuit core, it is fixed on described supporting disk;
Pin array, it is positioned at around described supporting disk and is electrically connected at described circuit core;
Packing colloid, its coated described supporting disk, support bar, circuit core, and be partly coated described pin array;
Wherein, on described support bar and/or supporting disk, there is clamp structure, be configured to the combination of fastening described supporting disk and packing colloid.
10. semiconductor package body as claimed in claim 9, is characterized in that, described clamp structure comprises the lateral protrusion on described support bar.
11. semiconductor package body as claimed in claim 9, is characterized in that, described clamp structure comprises that described support bar is with respect to the distal portion of described supporting disk, the bifurcated within packaging area.
12. semiconductor package body as claimed in claim 9, is characterized in that, described clamp structure comprises the through hole on described support bar and/or supporting disk.
13. semiconductor package body as claimed in claim 12, is characterized in that, have a plurality of through holes on arbitrary support bar.
14. semiconductor package body as claimed in claim 9, it is characterized in that, in described pin array, described support bar, be coated with at least in part bonding coating on respect to the close end of described supporting disk and described supporting disk, described clamp structure comprises the through hole in the bonding cladding region of support bar.
15. semiconductor package body as claimed in claim 14, is characterized in that, the area of the through hole in the bonding cladding region of described support bar is within 20%~30% scope of the area of the bonding cladding region of described support bar.
16. semiconductor package body as claimed in claim 9, is characterized in that, in described pin array, a pin distal portion has projection, and this distance that projects into described semiconductor package body edge is not less than 0.1mm, and width is not less than 0.1mm.
CN201320892708.3U 2013-12-31 2013-12-31 Leading wire frame and semiconductor packaging body Expired - Fee Related CN203800033U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201320892708.3U CN203800033U (en) 2013-12-31 2013-12-31 Leading wire frame and semiconductor packaging body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201320892708.3U CN203800033U (en) 2013-12-31 2013-12-31 Leading wire frame and semiconductor packaging body

Publications (1)

Publication Number Publication Date
CN203800033U true CN203800033U (en) 2014-08-27

Family

ID=51382227

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201320892708.3U Expired - Fee Related CN203800033U (en) 2013-12-31 2013-12-31 Leading wire frame and semiconductor packaging body

Country Status (1)

Country Link
CN (1) CN203800033U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715163A (en) * 2013-12-31 2014-04-09 日月光封装测试(上海)有限公司 Lead frame and semiconductor encapsulation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715163A (en) * 2013-12-31 2014-04-09 日月光封装测试(上海)有限公司 Lead frame and semiconductor encapsulation

Similar Documents

Publication Publication Date Title
US7977774B2 (en) Fusion quad flat semiconductor package
US6608366B1 (en) Lead frame with plated end leads
US7968998B1 (en) Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US9349612B2 (en) Lead frame
JP2009140962A (en) Semiconductor device and manufacturing method thereof
US9363901B2 (en) Making a plurality of integrated circuit packages
CN101859740A (en) Advanced quad flat non-leaded package and manufacture method thereof
US20110263077A1 (en) Method of assembling semiconductor devices including saw singulation
US20160379918A1 (en) Semiconductor package with small gate clip and assembly method
US9978695B1 (en) Semiconductor device including leadframe with a combination of leads and lands and method
JP2008501242A (en) Flexible lead frame structure and integrated circuit package forming method
US7095096B1 (en) Microarray lead frame
US11152288B2 (en) Lead frames for semiconductor packages
US8901722B2 (en) Semiconductor device with integral heat sink
US9508631B1 (en) Semiconductor device including leadframe with a combination of leads and lands and method
CN203800033U (en) Leading wire frame and semiconductor packaging body
CN103715163A (en) Lead frame and semiconductor encapsulation
JP2008153710A (en) Semiconductor device and manufacturing method thereof
JP3185996U (en) Lead frame assembly
CN204011408U (en) Lead frame and semiconductor package body
CN205159315U (en) Lead frame strip
CN216054692U (en) Novel high-density semiconductor lead frame structure
CN104485323A (en) Lead frame and semiconductor packaging body
KR101209472B1 (en) Lead frame for fabricating semiconductor package and Method for fabricating semiconductor package using the same
CN213583769U (en) High-integration-level lead frame

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20161129

Address after: 201201 room -T3-10-202, No. 5001 East Road, Shanghai, Pudong New Area

Patentee after: Advanced integrated circuit manufacturing (Chinese) Co. Ltd.

Patentee after: ASE Assembly & Test (Shanghai) Limited

Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 669

Patentee before: ASE Assembly & Test (Shanghai) Limited

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170405

Address after: 201203 Shanghai City, Pudong New Area China (Shanghai) free trade zone 669 GuoShouJing Road No. six building

Patentee after: ASE Assembly & Test (Shanghai) Limited

Address before: 201201 room -T3-10-202, No. 5001 East Road, Shanghai, Pudong New Area

Patentee before: Advanced integrated circuit manufacturing (Chinese) Co. Ltd.

Patentee before: ASE Assembly & Test (Shanghai) Limited

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140827

Termination date: 20181231