CN104992985B - 薄膜晶体管及其制造方法、阵列基板 - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 title abstract description 20
- 238000000034 method Methods 0.000 claims description 31
- 239000002096 quantum dot Substances 0.000 claims description 28
- 239000010408 film Substances 0.000 claims description 12
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 92
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 10
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- ZPZCREMGFMRIRR-UHFFFAOYSA-N molybdenum titanium Chemical compound [Ti].[Mo] ZPZCREMGFMRIRR-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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Abstract
一种薄膜晶体管及其制造方法、阵列基板,在薄膜晶体管的有源层沟道区域形成相互独立的纳米导电点,使有源层沟道区域被分成多个相互独立的子沟道,从而增加了等效电场强度。等效电场强度越大,载流子迁移率越大。因此,形成的薄膜晶体管的开态电流就越大,有利于制造具有更高解析度和更高开口率的薄膜晶体管。
Description
技术领域
本发明涉及电子器件技术领域,尤其涉及一种薄膜晶体管,还涉及一种具有该薄膜晶体管的阵列基板以及用于制造该薄膜晶体管的方法。
背景技术
薄膜场效应晶体管(Thin Film Transistor,TFT)是晶体管的种类之一,被广泛应用于显示领域。现有技术中的薄膜晶体管包括栅极、栅极绝缘层、有源层、源极和漏极。
显示面板一般包括阵列基板。阵列基板上形成有多个像素,且每一个像素对应一个薄膜晶体管,从而通过薄膜晶体管控制相应像素进行显示。随着显示行业的发展,对薄膜晶体管特性的要求也日益提高,需要薄膜晶体管具有较大的开态电流。薄膜晶体管开态电流Ids的计算式为其中u表示有源层的载流子迁移率,COX表示单位面积的绝缘层电容,W表示薄膜晶体管的沟道宽度,L表示薄膜晶体管的沟道长度,Vgs表示栅极相对于源极的电压,Vth表示阈值电压。根据开态电流的计算式可知,u、W和L都是影响薄膜晶体管开态电流的主要因素。在薄膜晶体管中,L值过小容易导致源漏极金属发生短路,W过大会导致开口率降低以及源漏极与栅极的直接耦合电容增加。增加u是提高薄膜晶体管开态电流的最为有效的方法之一。因此,亟需一种具有较高的载流子迁移率的薄膜晶体管。
发明内容
本发明所要解决的技术问题是:现有技术中不存在具有较高的载流子迁移率的薄膜晶体管。
为了解决上述技术问题,本发明提供了一种薄膜晶体管及其制造方法、阵列基板。
根据本发明的第一个方面,提供了一种薄膜晶体管,其包括栅极、绝缘层、源极、漏极和有源层,所述有源层包括相互独立的纳米导电点。
优选的是,所述纳米导电点的直径为
优选的是,所述薄膜晶体管为底栅型薄膜晶体管或者顶栅型薄膜晶体管。
根据本发明的第二个方面,提供了一种具有上述薄膜晶体管的阵列基板。
根据本发明的第三个方面,提供了一种用于制造薄膜晶体管的方法,其包括:
形成包括栅极、绝缘层、源极、漏极和有源层在内的多层结构,并使所述有源层包括相互独立的纳米导电点。
优选的是,形成包括栅极、绝缘层、源极、漏极和有源层在内的多层结构,并使所述有源层包括相互独立的纳米导电点,包括:
形成栅极;
在所述栅极上形成所述绝缘层;
在所述绝缘层上形成所述有源层;
在所述有源层上形成具有所述源极和所述漏极的图形,所述图形由金属合金形成;
采用脱合金化方法在所述图形对应所述有源层的区域形成纳米点掩膜;
利用所述纳米点掩膜,在所述有源层上形成所述相互独立的纳米导电点。
优选的是,采用离子注入的方法,利用所述纳米点掩膜,在所述有源层上形成所述相互独立的纳米导电点。
优选的是,形成包括栅极、绝缘层、源极、漏极和有源层在内的多层结构,并使所述有源层包括相互独立的纳米导电点,包括:
形成所述有源层;
在所述有源层上形成具有所述源极和所述漏极的图形,所述图形由金属合金形成;
采用脱合金化方法在所述图形对应所述有源层的区域形成纳米点掩膜;
利用所述纳米点掩膜,在所述有源层上形成所述相互独立的纳米导电点;
去除所述纳米点掩膜;
在具有所述纳米导电点的有源层及所述图形上形成所述绝缘层;
在所述绝缘层上形成所述栅极。
优选的是,采用离子注入的方法,利用所述纳米点掩膜,在所述有源层上形成所述相互独立的纳米导电点。
优选的是,所述纳米导电点的直径为
与现有技术相比,上述方案中的一个或多个实施例可以具有如下优点或有益效果:
本发明在有源层沟道区域形成相互独立的纳米导电点,使得有源层沟道区域被分成多个相互独立的子沟道,从而增加了等效电场强度。等效电场强度越大,载流子迁移速度和载流子迁移率越大。因此,形成的薄膜晶体管的开态电流就越大,有利于制造具有更高解析度和更高开口率的薄膜晶体管,提高了薄膜晶体管的性能。
本发明的其它特征和优点将在随后的说明书中阐述,并且部分地从说明书中变得显而易见,或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解,并且构成说明书的一部分,与本发明的实施例共同用于解释本发明,并不构成对本发明的限制。在附图中:
图1示出了本发明实施例底栅型薄膜晶体管的结构示意图;
图2示出了本发明实施例用于制造底栅型薄膜晶体管的方法的流程示意图;
图3a示出了本发明实施例中在衬底基板上形成栅极后的示意图;
图3b示出了本发明实施例中在栅极上形成绝缘层和有源层后的示意图;
图3c示出了本发明实施例中在有源层上形成具有源极和漏极的图形后的示意图;
图3d示出了本发明实施例中在具有源极和漏极的图形上形成光阻后的示意图;
图3e示出了本发明实施例中使所述图形的部分区域形成纳米点掩膜后的示意图;
图3f示出了本发明实施例中利用纳米点掩膜在有源层上形成纳米导电点后的示意图;以及
图4示出了本发明实施例中用于制造顶栅型薄膜晶体管的方法的流程示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术手段来解决技术问题,并达成技术效果的实现过程能充分理解并据以实施。需要说明的是,只要不构成冲突,本发明中的各个实施例以及各实施例中的各个特征可以相互结合,所形成的技术方案均在本发明的保护范围之内。
为解决现有技术中不存在具有较高的载流子迁移率的薄膜晶体管的技术缺陷,本发明实施例提供了一种具有较高的截流子迁移率的薄膜晶体管。本发明实施例的薄膜晶体管主要包括栅极、绝缘层、源极、漏极和有源层。栅极和源极同时加载信号,使得有源层导通源极和漏极。有源层包括相互独立的纳米导电点。
应用本实施例所述的薄膜晶体管,在有源层沟道区域形成相互独立的纳米导电点,使得有源层沟道区域被分成多个相互独立的子沟道,从而增加了等效电场强度。等效电场强度越大,载流子迁移速度和载流子迁移率越大。因此,形成的薄膜晶体管的开态电流就越大,有利于制造具有更高解析度和更高开口率的薄膜晶体管,提高了薄膜晶体管的性能。
为了进一步增加有源层的载流子迁移率,本发明优选的实施例将纳米导电点的直径限定在
另外,源极、漏极和栅极是薄膜晶体管的三个电极。根据各个电极的位置关系将薄膜晶体管分为两类。一类是栅极位于源极和漏极的下面,这类薄膜晶体管被称为底栅型薄膜晶体管。另一类是栅极位于源极和漏极的上面,这类薄膜晶体管被称为顶栅型薄膜晶体管。本发明实施例提供的薄膜晶体管可以是顶栅型薄膜晶体管,也可以是底栅型薄膜晶体管。本发明实施例及附图首先以底栅型薄膜晶体管为例进行详细说明。
图1示出了本发明实施例底栅型薄膜晶体管的结构示意图。如图1所示,本实施例的底栅型薄膜晶体管包括衬底基板1、栅极2、绝缘层3、有源层4、源极和漏极。
具体地,栅极2形成在衬底基板1上。绝缘层3形成在栅极2上。有源层4形成在绝缘层3上,并且该有源层4包括相互独立的纳米导电点7。具有源极和漏极的图形5形成在有源层4上。另外,在具有源极和漏极的图形5上还依次形成有钝化层和像素电极。像素电极通过钝化层具有的过孔连接具有源极和漏极的图形5。
本发明实施例还提供了一种具有上述薄膜晶体管的阵列基板。阵列基板可应用于液晶显示技术领域。
另外,本发明实施例还提供了一种用于制造上述薄膜晶体管的方法。本实施例的制造方法为:形成包括栅极2、绝缘层3、源极、漏极和有源层4在内的多层结构,并使有源层4包括相互独立的纳米导电点7。
应用本实施例所述的用于制造薄膜晶体管的方法,在有源层4沟道区域形成相互独立的纳米导电点7,使得有源层4沟道区域被分成多个相互独立的子沟道,从而增加了等效电场强度。等效电场强度越大,载流子迁移速度和载流子迁移率越大。因此,形成的薄膜晶体管的开态电流就越大,有利于制造具有更高解析度和更高开口率的薄膜晶体管,提高了薄膜晶体管的性能。
应用本实施例所述的方法制造出来的薄膜晶体管既可以是顶栅型薄膜晶体管,也可以是底栅型薄膜晶体管。
如图2所示,是本发明实施例中用于制造底栅型薄膜晶体管的方法的流程示意图。本实施例的制造方法主要包括步骤101至步骤106。
在步骤101中,提供衬底基板1并在衬底基板1上形成栅极2。
具体地,首先在衬底基板1上沉积金属层,并在金属层上涂覆光阻。这里,金属层可为钼铝(MoAl)叠层结构、钛铝(TiAl)叠层结构或者其它单层金属结构。然后经曝光显影及刻蚀操作后形成如图3a所示的栅极2图案。
在步骤102中,在栅极2上形成绝缘层3。
在步骤103中,在绝缘层3上形成有源层4。
具体地,首先在绝缘层3上沉积氢化非晶硅(a-Si:H)或者氧化铟镓锌(IGZO,Indium Gallium Zinc Oxide)等半导体材料,并在半导体材料上涂覆光阻6。然后,经曝光显影及刻蚀后形成如图3b所示的有源层4图案。
在步骤104中,在有源层4上形成具有源极和漏极的图形5,该图形5由金属合金形成。
具体地,参照图3c,在有源层4上沉积源漏极(S/D)金属电极层。此金属电极层可为钼铝、钼钛等金属合金形成。
在步骤105中,采用脱合金化方法在所述图形5对应有源层4的区域形成纳米点掩膜51。
具体地,首先在具有源极和漏极的图形5上涂覆光阻,经过曝光显影去掉对应有源层4的光阻。参照图3d,是去掉对应有源层4的光阻后的示意图。然后在上述图形5的未被光阻6覆盖的部分应用脱合金化方法,以使此部分图形5形成如图3e中所示的具有纳米级微孔的纳米点掩膜51。
这里,脱合金化方法用于选择性地溶解上述部分图形5(金属合金)中的某一组分。
在步骤106中,利用纳米点掩膜51,在有源层4上形成相互独立的纳米导电点7。
具体地,采用离子注入或类似方法,利用步骤105形成的纳米点掩膜51,在有源层4上形成如图3f所示的多个彼此独立的纳米导电点7。值得说明的是,通过控制金属合金的成份以及脱合金化方法来调节所形成的纳米点掩膜51的结构,从而调节各个纳米导电点7的尺寸大小及间距。特别地,形成的纳米导电点7的直径为
形成纳米导电点7后,利用灰化工艺去除剩余的光阻6,并去除纳米点掩膜51后,即形成如图1所示的底栅型薄膜晶体管。
如图4所示,是本发明实施例中用于制造顶栅型薄膜晶体管的方法的流程示意图。本实施例的制造方法主要包括步骤201至步骤206。
在步骤201中,提供衬底基板1并在衬底基板1上形成有源层4。
具体地,首先提供衬底基板1,然后在衬底基板1上沉积氢化非晶硅(a-Si:H)或者氧化铟镓锌(IGZO,Indium Gallium Zinc Oxide)等半导体材料,并在半导体材料上涂覆光阻。然后,经曝光显影及刻蚀后形成有源层4图案。
在步骤202中,在有源层4上形成具有源极和漏极的图形5,该图形5由金属合金形成。
具体地,在有源层4上沉积源漏极(S/D)金属电极层。此金属电极层可为钼铝、钼钛等金属合金形成。
在步骤203中,采用脱合金化方法在所述图形5对应有源层4的区域形成纳米点掩膜51。
具体地,首先在具有源极和漏极的图形5上涂覆光阻,经过曝光显影去掉对应有源层4的光阻。然后在所述图形5未被光阻6覆盖的部分应用脱合金化方法,以使此部分图形5形成具有纳米级微孔的纳米点掩膜51。
在步骤204中,利用纳米点掩膜51,在有源层4上形成相互独立的纳米导电点7。
具体地,采用离子注入或类似方法,利用步骤203形成的纳米点掩膜51,在有源层4上形成多个彼此独立的纳米导电点7。值得说明的是,通过控制金属合金的成份以及脱合金化方法来调节所形成的纳米点掩膜51的结构,从而调节各个纳米导电点7的尺寸大小及间距。特别地,形成的纳米导电点7的直径为
在步骤205中,去除所述纳米点掩膜。
在步骤206中,在具有纳米导电点7的有源层4及所述图形5上形成绝缘层3。
在步骤207中,在绝缘层3上形成栅极2。
具体地,首先在绝缘层3上沉积金属层,并在金属层上涂覆光阻。这里,金属层可为钼铝(MoAl)叠层结构、钛铝(TiAl)叠层结构或者其它单层金属结构。然后经曝光显影及刻蚀操作后形成栅极2图案。
形成栅极后,利用灰化工艺去除剩余的光阻,即形成顶栅型薄膜晶体管。
虽然本发明所公开的实施方式如上,但所述的内容只是为了便于理解本发明而采用的实施方式,并非用以限定本发明。任何本发明所属技术领域内的技术人员,在不脱离本发明所公开的精神和范围的前提下,可以在实施的形式上及细节上作任何的修改与变化,但本发明的保护范围,仍须以所附的权利要求书所界定的范围为准。
Claims (4)
1.一种用于制造薄膜晶体管的方法,其特征在于,包括:
形成包括栅极、绝缘层、源极、漏极和有源层在内的多层结构,并使所述有源层包括相互独立的纳米导电点,还使所述纳米导电点的直径为
其中,形成包括栅极、绝缘层、源极、漏极和有源层在内的多层结构,并使所述有源层包括相互独立的纳米导电点,包括:
形成栅极;
在所述栅极上形成所述绝缘层;
在所述绝缘层上形成所述有源层;
在所述有源层上形成具有所述源极和所述漏极的图形,所述图形由金属合金形成;
采用脱合金化方法在所述图形对应所述有源层的区域形成纳米点掩膜;
利用所述纳米点掩膜,在所述有源层上形成所述相互独立的纳米导电点。
2.根据权利要求1所述的方法,其特征在于,采用离子注入的方法,利用所述纳米点掩膜,在所述有源层上形成所述相互独立的纳米导电点。
3.一种用于制造薄膜晶体管的方法,其特征在于,包括:
形成包括栅极、绝缘层、源极、漏极和有源层在内的多层结构,并使所述有源层包括相互独立的纳米导电点,还使所述纳米导电点的直径为
其中,形成包括栅极、绝缘层、源极、漏极和有源层在内的多层结构,并使所述有源层包括相互独立的纳米导电点,包括:
形成所述有源层;
在所述有源层上形成具有所述源极和所述漏极的图形,所述图形由金属合金形成;
采用脱合金化方法在所述图形对应所述有源层的区域形成纳米点掩膜;
利用所述纳米点掩膜,在所述有源层上形成所述相互独立的纳米导电点;
去除所述纳米点掩膜;
在具有所述纳米导电点的有源层及所述图形上形成所述绝缘层;
在所述绝缘层上形成所述栅极。
4.根据权利要求3所述的方法,其特征在于,采用离子注入的方法,利用所述纳米点掩膜,在所述有源层上形成所述相互独立的纳米导电点。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1804122A (zh) * | 2005-12-08 | 2006-07-19 | 复旦大学 | 一种可移植超薄纳米孔金膜及其制备方法 |
CN101596598A (zh) * | 2009-07-01 | 2009-12-09 | 济南大学 | 一种整体连续纳米多孔铜的制备方法 |
CN102943187A (zh) * | 2012-11-19 | 2013-02-27 | 河北工业大学 | 纳米多孔铜的制备方法 |
CN104157698A (zh) * | 2014-08-05 | 2014-11-19 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制作方法 |
Family Cites Families (7)
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US5949188A (en) | 1996-12-18 | 1999-09-07 | Hage Gmbh & Co. Kg | Electroluminescent display device with continuous base electrode |
US20050139867A1 (en) * | 2003-12-24 | 2005-06-30 | Saito Shin-Ichi | Field effect transistor and manufacturing method thereof |
CN101689607A (zh) * | 2007-06-28 | 2010-03-31 | 3M创新有限公司 | 结合界面导电簇的薄膜晶体管 |
US8729529B2 (en) * | 2011-08-03 | 2014-05-20 | Ignis Innovation Inc. | Thin film transistor including a nanoconductor layer |
CN102856211A (zh) * | 2012-09-27 | 2013-01-02 | 中国科学院苏州纳米技术与纳米仿生研究所 | 一种碳纳米管场效应晶体管有源层的制备方法 |
TWI508305B (zh) * | 2013-05-06 | 2015-11-11 | E Ink Holdings Inc | 主動元件 |
CN104538396B (zh) * | 2015-01-16 | 2017-06-30 | 京东方科技集团股份有限公司 | 半导体层、半导体器件、阵列基板和显示装置的制备方法 |
-
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1804122A (zh) * | 2005-12-08 | 2006-07-19 | 复旦大学 | 一种可移植超薄纳米孔金膜及其制备方法 |
CN101596598A (zh) * | 2009-07-01 | 2009-12-09 | 济南大学 | 一种整体连续纳米多孔铜的制备方法 |
CN102943187A (zh) * | 2012-11-19 | 2013-02-27 | 河北工业大学 | 纳米多孔铜的制备方法 |
CN104157698A (zh) * | 2014-08-05 | 2014-11-19 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制作方法 |
Non-Patent Citations (1)
Title |
---|
Technology for nanoperiodic doping of a metal-oxide-semiconductor field-effect transistor channel using a self-forming wave-ordered structure;V K Smirnov etc;《Nanotechnology》;20030501;第14卷(第7期);第710-712页 * |
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