CN104992973A - Gate heterojunction device - Google Patents
Gate heterojunction device Download PDFInfo
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- CN104992973A CN104992973A CN201510263199.1A CN201510263199A CN104992973A CN 104992973 A CN104992973 A CN 104992973A CN 201510263199 A CN201510263199 A CN 201510263199A CN 104992973 A CN104992973 A CN 104992973A
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- ion
- raceway groove
- based semiconductor
- heterojunction
- grid
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- 239000004065 semiconductor Substances 0.000 claims abstract description 92
- 150000002500 ions Chemical class 0.000 claims abstract description 57
- 239000012212 insulator Substances 0.000 claims description 36
- 239000010408 film Substances 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 230000004888 barrier function Effects 0.000 claims description 27
- 239000010409 thin film Substances 0.000 claims description 26
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 25
- 229910052742 iron Inorganic materials 0.000 claims description 17
- JLVVSXFLKOJNIY-UHFFFAOYSA-N Magnesium ion Chemical compound [Mg+2] JLVVSXFLKOJNIY-UHFFFAOYSA-N 0.000 claims description 16
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 claims description 16
- 229910001425 magnesium ion Inorganic materials 0.000 claims description 16
- 229910001415 sodium ion Inorganic materials 0.000 claims description 16
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 11
- -1 iron ion Chemical class 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052745 lead Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
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- 238000002789 length control Methods 0.000 description 11
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
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- 229910010413 TiO 2 Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Abstract
The invention relates to the technical field of semiconductors, and specifically relates to a gate heterojunction device. The gate heterojunction device mainly adopts a second kind semiconductor and a third kind to form a heterojunction, an insulating layer is arranged on an ohmic contact S end, a gate grid is arranged between a source electrode and a drain electrode, and the on-off state of a grid channel is controlled by the structure of the gate grid; in addition, when no voltage is applied to the device, by controlling the thickness of a third kind semiconductor in the gate grid and the concentration of doped positive and negative ions, the device is enabled to be a normally-closed device, and forward and reverse voltage resistance of the device is realized through the growth length between a grid drain electrode and a source drain electrode. The gate heterojunction device has the advantages that the gate heterojunction device is the normally-closed device, integration and layout are realized in a heterojunction type HEMTs, the technology compatibility is good, the performance is stable under a high-temperature high-field environment, and the voltage resistance of the circuit is controllable.
Description
Technical field
The present invention relates to technical field of semiconductor device, be specifically related to one and enclose gate heterojunction device.
Background technology
Three races-five compounds of group heterojunction High Electron Mobility Transistor (HEMTs) not only has that energy gap is large, critical breakdown electric field is high, electron saturation velocities is high, and there is the advantages such as radioresistance, good heat conductivity and good chemical stability, therefore being specially adapted to the application of high temperature high field intensity, is one of transistor of applied power electronics most potentiality.
General heterojunction HEMTs is plane superposition device, and such as AlGaN/GaN HEMTs comprises the substrate formed by sapphire, silicon or SiC, the GaN layer that substrate is formed, the AlGaN layer that GaN layer is formed, the Ohmic electrode at two intervals and the gate electrode that formed between that in AlGaN layer.
Along with the reduction of device size, double grid FinFET (fin field-effect transistor, Fin Field-Effect Transistor; FinFET) device enclosing grid structure more and more receives an acclaim, the silicon device cardinal principle of enclosing grid structure is raceway groove at two vertical side of Fin and top, pinch off and the conducting of raceway groove is controlled by the grid of Fin two vertical side, effectively can reduce the size of device, but the Fin structure devices made based on the material such as silicon, carborundum not only breakdown potential to force down Leakage Current large, and unstable properties when working under high temperature high field intensity environment, there is the problem easily lost efficacy.At present in high power device and intelligent IC field, the device not yet found that there is based on three or five group-III nitride heterojunction type Fin structures is reported.
Summary of the invention
To be solved by this invention, Problems existing in grid Fin structure devices is enclosed based on silicon or carbofrax material exactly for above-mentioned tradition, a kind of high pressure resistant Low dark curient electric current is proposed, and still can normally work under high temperature high field intensity environment, can in heterojunction type HEMTs integrated and domain and processing compatibility good, and there is ultralow leakage current enclose gate heterojunction type device.
For achieving the above object, the present invention adopts following technical scheme:
One encloses gate heterojunction device, as shown in Figure 2, comprise the first kind Semiconductor substrate 100, Equations of The Second Kind semiconductive thin film 200 and the 3rd based semiconductor film 300 that set gradually from the bottom up, described Equations of The Second Kind semiconductive thin film 200 and the 3rd based semiconductor film 300 form heterojunction in junction; The two ends of described 3rd based semiconductor film 300 are respectively arranged with the first ohmic contact 301 and the second ohmic contact 302; Described heterojunction boundary place has the first raceway groove 201, second raceway groove 202 and triple channel 203 near first ohmic contact 301 one end successively near second ohmic contact 302 one end; Described second ohmic contact 302 has the first insulator 400 away from the side of the first ohmic contact 301, and the bottom surface of described first insulator 400 is connected with the upper surface of Equations of The Second Kind semiconductive thin film 200; Have grid 303 between described first ohmic contact 301 and the second ohmic contact 302, described grid 303 is for enclosing grid structure; Described grid 303 comprises the second insulator 500 and is arranged on the metal area 600 of the second insulator 500 upper surface, described second insulator 500 is positioned at first kind Semiconductor substrate 100 upper surface, described Equations of The Second Kind semiconductive thin film 200 and the 3rd based semiconductor film 300 along device horizontal direction through the second insulator 500, described metal area 600, second insulator 500 and be arranged in the 3rd based semiconductor film 300 of the second insulator 500 and Equations of The Second Kind semiconductive thin film 200 forms MIS (metal-insulator semiconductor) structure; Described second raceway groove 202 is arranged in immediately below MIS structure the 3rd based semiconductor 300, immediately below the 3rd based semiconductor film 300 of described first raceway groove between grid 303 and the first ohmic contact 301, immediately below the 3rd based semiconductor film 300 of described triple channel between grid 303 and the second ohmic contact 302, first raceway groove 201, triple channel 203 are the drift region of device, it is the forward and reverse withstand voltage zone of device, described grid 303 has two extraction electrodes, lays respectively at MIS structure both sides along device longitudinal direction.
Further, described first kind Semiconductor substrate 100 is the one in sapphire, silicon and carborundum; Described Equations of The Second Kind semiconductive thin film 200 and the 3rd based semiconductor film 300 are three races-five compounds of group, and can form heterojunction at the contact interface place of Equations of The Second Kind semiconductor 200 and the 3rd based semiconductor 300.
Further, described metal area 600 has the metal that work function is greater than 4.0eV.
Further, it is characterized in that, the metal that metal area 600 is arranged is one or more metal levels superposition in Ti, Ni, Al, Au, Pt, No, W, Ag, Mo or Pb.
Various metals described in this programme is stacked to be added, and comprises as Ni (60nm)/Au (130nm), Ti (30nm)/Al (60nm)/Ti (30nm)/Au (150nm) etc.
Further, have the 3rd based semiconductor film 300 barrier layer that the second raceway groove 202 can be made to exhaust in described MIS structure, the thickness of the 3rd described based semiconductor film 300 barrier layer is 1 ~ 50 nanometer.
Further, have the F ion or C1 ion that the second raceway groove 202 can be made to exhaust in the Equations of The Second Kind insulator 500 in described MIS structure around the 3rd based semiconductor film 300, described F ion or C1 concentration are 10
12~ 10
20cm
-3.
Further, have the F ion or C1 ion that the second raceway groove 202 can be made to exhaust in described 3rd based semiconductor film 300 barrier layer, described F ion or C1 ion concentration are 10
12~ 10
20cm
-3.
Further, the Equations of The Second Kind semiconductive thin film 200 be arranged in described MIS structure immediately below the second raceway groove 202 has the magnesium ion or sodium ion or iron ion that the second raceway groove 202 can be made to exhaust, and described magnesium ion or sodium ion or iron concentration are 10
12~ 10
20cm
-3.
Further, doped with F ion or C1 ion in the 3rd based semiconductor 300 barrier layer in described MIS structure, the two-dimensional electron gas being provided for the second raceway groove 202 exhausts; The concentration of described F ion or C1 ion is 10
12~ 10
20cm
-3;
Further, being arranged in Equations of The Second Kind semiconductive thin film 200 immediately below the second raceway groove 202 in described MIS structure doped with magnesium ion or sodium ion or iron ion, exhausting for making the two-dimensional electron gas of the second raceway groove 202; The concentration of described F ion or C1 ion and described magnesium ion or sodium ion or iron ion is 10
12~ 10
20cm
-3.
Beneficial effect of the present invention is, the advantage of device tool stable performance under high temperature high field intensity environment, can be integrated in heterojunction type HEMTs kind, and domain and processing compatibility good, there is ultralow leakage current.
Accompanying drawing explanation
Fig. 1 of the present inventionly encloses gate heterojunction type device architecture schematic diagram;
Fig. 2 is the generalized section along E-F line in Fig. 1;
Fig. 3 is that the gate heterojunction device that encloses of the present invention is as voltage-current characteristic figure during MIS device;
Fig. 4 of the present inventionly encloses the application schematic diagram of gate heterojunction device as diode component;
Fig. 5 of the present inventionly encloses the voltage-current characteristic figure of gate heterojunction device as diode component;
Fig. 6 is generalized section of enclosing the E-F line of the first method that gate heterojunction device realizes of the present invention;
Fig. 7 is the first method of enclosing gate heterojunction device and realizing of the present invention;
Fig. 8 is the second method of enclosing gate heterojunction device and realizing of the present invention;
Fig. 9 is the third method of enclosing gate heterojunction device and realizing of the present invention;
Figure 10 is the 4th kind of method of enclosing gate heterojunction device and realizing of the present invention;
Figure 11 is the Lung biopsy enclosing gate heterojunction device and realize of the present invention;
Figure 12 is the 6th kind of method of enclosing gate heterojunction device and realizing of the present invention;
Figure 13 is the 7th kind of method of enclosing gate heterojunction device and realizing of the present invention;
Figure 14 is the 8th kind of method of enclosing gate heterojunction device and realizing of the present invention;
Figure 15 is the 9th kind of method of enclosing gate heterojunction device and realizing of the present invention;
Figure 16 is the tenth kind of method of enclosing gate heterojunction device and realizing of the present invention;
Figure 17 is the octangle structure cell schematic diagram enclosing gate heterojunction device of the present invention;
Figure 18 is the bar shaped structure cell schematic diagram enclosing gate heterojunction device of the present invention;
Figure 19 is the quadrangle cellular structural representation enclosing gate heterojunction device of the present invention;
Figure 20 is that of the present invention enclosing in gate heterojunction device making technics flow process precipitates structural representation after Equations of The Second Kind and the 3rd based semiconductor material on substrate;
Figure 21 is that of the present invention enclosing in gate heterojunction device making technics flow process deposits structural representation after first kind insulator on Equations of The Second Kind semiconductor;
Figure 22 is that of the present invention enclosing in gate heterojunction device making technics flow process makes structural representation after ohmic contact at the 3rd based semiconductor material two ends;
Figure 23 is that of the present invention to enclose in gate heterojunction device making technics flow process to etch the 3rd based semiconductor material and form structural representation after groove between two ohmic contact;
Figure 24 is structural representation after depositing Equations of The Second Kind insulator between two ohmic contact of enclosing in gate heterojunction device making technics flow process on the 3rd based semiconductor of the present invention;
Figure 25 is that of the present invention enclosing in gate heterojunction device making technics flow process completes MIS and enclose structural representation after grid.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
The present invention proposes one and enclose gate heterojunction device, as shown in Figure 2, comprise the first kind Semiconductor substrate 100, Equations of The Second Kind semiconductive thin film 200 and the 3rd based semiconductor film 300 that set gradually from the bottom up, described Equations of The Second Kind semiconductive thin film 200 and the 3rd based semiconductor film 300 form heterojunction in junction; The two ends of described 3rd based semiconductor film 300 are respectively arranged with the first ohmic contact 301 and the second ohmic contact 302; Described heterojunction boundary place has the first raceway groove 201, second raceway groove 202 and triple channel 203 near first ohmic contact 301 one end successively near second ohmic contact 302 one end; Described second ohmic contact 302 has the first insulator 400 away from the side of the first ohmic contact 301, and the bottom surface of described first insulator 400 is connected with the upper surface of Equations of The Second Kind semiconductive thin film 200; Have grid 303 between described first ohmic contact 301 and the second ohmic contact 302, described grid 303 is for enclosing grid structure; Described grid 303 comprises the second insulator 500 and is arranged on the metal area 600 of the second insulator 500 upper surface, described second insulator 500 is positioned at the upper surface of the 3rd based semiconductor film 300, and described metal area 600, second insulator 500 and the 3rd based semiconductor film 300 be positioned at immediately below the second insulator 500 and Equations of The Second Kind semiconductive thin film 200 form MIS structure; Described second raceway groove 202 is arranged in immediately below MIS structure the 3rd based semiconductor 300, immediately below the 3rd based semiconductor film 300 of described first raceway groove between grid 303 and the first ohmic contact 301, immediately below the 3rd based semiconductor film 300 of described triple channel between grid 303 and the second ohmic contact 302, first raceway groove 201, triple channel 203 are the drift region of device, are the forward and reverse withstand voltage zones of device.
Hereafter describe in, the extraction electrode of the first ohmic contact is referred to as S pole, and the extraction electrode of the second ohmic contact is referred to as D pole, and 2 extraction electrodes of grid are respectively referred to as VG1 and VG2.
Device is not when being subject to voltage effect, and the first raceway groove 201, triple channel 203 exist two-dimensional electron gas, and the second raceway groove 202 exhausts; The present invention controls conducting and the pinch off of the second raceway groove 202 by being added in the bias voltage enclosing gate electrode VG1 and VG2, realize control device and turn off and conducting; When the non-making alive of device, the length of the length and drift region first raceway groove 201, second raceway groove 202 that also can control the second raceway groove 202 pinch off realizes device becomes bidirectional trigger diode; First raceway groove 201, triple channel 203 are as the withstand voltage of main district of device.
One of operation principle of the present invention: when device encloses gate device as MIS, device is double-gate structure, by the bias voltage of control grid electrode VG1 and VG2, the conducting of control device second raceway groove 202 and shutoff, when the bias voltage of grid be greater than make the second raceway groove 202 produce the threshold voltage of two-dimensional electron gas time, second raceway groove conducting, when the bias voltage of grid be less than make the second raceway groove 202 produce the threshold voltage of two-dimensional electron gas time, the second raceway groove 202 two-dimensional electron gas exhausts pinch off; When device is not subject to voltage effect, by controlling the first raceway groove 202, the length of triple channel 203 realizes the withstand voltage of control device;
Fig. 3 is that the present invention encloses gate heterojunction device when enclosing gate device as MIS, under different gate electrode voltage, and the graph of a relation of source-drain current Id and drain terminal D bias voltage Vd; When the bias voltage of VG1 and VG2 be less than second raceway groove 202 that can make to exhaust produce the threshold voltage of two-dimensional electron gas time, source-drain current Id changes little with drain terminal D bias voltage Vd, be in cut-off state; When the bias voltage of VG1 and VG2 be equal to or greater than second raceway groove 202 that can make to exhaust produce the threshold voltage of two-dimensional electron gas time, drain-source current Id starts increase with drain terminal D bias voltage Vd and linearly increase, and now device is in conducting state; Along with drain terminal D bias voltage Vd continues to increase, source-drain current Id is in saturation condition, and namely device is in full state.
Operation principle two of the present invention: during the diode of device as forward and reverse triggering, the gate electrode VG1 of device, VG2 is not biased, the forward being realized device by the length controlling the first raceway groove 201 and the second raceway groove 202 pinch off is triggered, when there being forward voltage to be added in D pole, first raceway groove 201 is under the voltage effect of D pole, two-dimensional electron gas in first raceway groove 201 is pulled out, the second raceway groove 202 still locating pinch off is subject to the effect of large electric field at the first raceway groove 201 end, the second raceway groove 202 is made to produce short-channel effect, electronics is from triple channel 203 then through the second raceway groove 202 to the first raceway groove 201, achieve the second raceway groove 202 conducting, namely the forward achieving device triggers, when there being forward voltage to be added in S pole, gate electrode VG1, VG2 are not biased, triple channel 203 is under the voltage effect of S pole, two-dimensional electron gas in triple channel 203 is pulled out, the second raceway groove 202 still locating pinch off is subject to large electric field action at triple channel 203 end, makes the second raceway groove 202 produce short-channel effect, and electronics is from the first raceway groove 201 then through the second raceway groove 202 to the triple channel 203, achieve the second raceway groove 202 conducting, namely achieve the reverse triggering of device, when device is not subject to voltage effect, the threshold voltage that the length control forward that two-dimensional electron gas by controlling the second raceway groove 202 exhausts length and drift region first raceway groove 201 triggers, the length being exhausted length and drift region triple channel 203 by the two-dimensional electron gas controlling the second raceway groove 202 controls the reverse threshold voltage triggered, the withstand voltage that can also pass through the growth length realizing circuit of control first raceway groove 201, triple channel 203 is controlled.
Fig. 4 is that the present invention is applied to an example of esd protection circuit as bidirectional trigger diode, when forward esd pulse acts on electrode D, described D pole is as anode, described S pole is as negative electrode, electrode S, electrode G1, electrode G2 is connected on low-voltage end VSS, second raceway groove 202 pinch off, first raceway groove 201 is under the effect of forward esd pulse, two-dimensional electron gas in first raceway groove 201 is pulled out, the second raceway groove 202 exhausted is under the first raceway groove 201 end is subject to large electric field action, the second raceway groove 202 is made to produce short-channel effect, the electronics of triple channel 203 is satisfied through the first raceway groove 201 by the second raceway groove 202, second raceway groove 202 transient switching, form ESD current drain path, when ESD reverse impulse acts on electrode D, namely described D pole is as negative electrode, described S pole is as anode, electrode D, electrode G1, electrode G2 is connected on low Static Electro pressure side VSS, second raceway groove 202 pinch off, triple channel 203 is under esd pulse effect, two-dimensional electron gas in triple channel 203 is pulled out, the second raceway groove 202 exhausted is under triple channel 203 end is subject to large electric field action, the second raceway groove 202 is made to produce short-channel effect, the electronics of the first raceway groove 201 is satisfied through triple channel 203 by the second raceway groove 202, second raceway groove 202 transient switching, form reverse ESD to release path.
As shown in Figure 5, for the gate heterojunction type device that encloses of the present invention is as voltage-current characteristic schematic diagram during bidirectional diode practical application, when the voltage being added in device two ends is less than device trigger threshold voltage, the two ends terminal voltage of device equals applied voltage and to flow through the electric current of device almost nil, can ignore; When the voltage being applied to device two ends is equal to or greater than the trigger threshold voltage of device, device forms conducting instantaneously, and the two ends terminal voltage size of device equals the trigger threshold voltage of device, the steep increasing of electric current moment.
Fig. 6, Fig. 7 be a kind of at device not by the method that the second raceway groove 202 exhausts can be realized during voltage effect, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and pass through the thickness of the 3rd based semiconductor barrier layer 300 in control MIS (metal-insulator semiconductor), the second raceway groove 202 is made to exhaust pinch off, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 201 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode; Semiconductor barrier is thinner, and raceway groove more exhausts, and can realize the 3rd class barrier layer thickness in the MIS that the second raceway groove 202 exhausts is 1 ~ 10 nanometer.
As shown in Figure 8, a kind ofly enclosing the cross section structure of gate heterojunction device along A-B line in Fig. 1, is the second can realize the second raceway groove 202 and exhausts method when the non-making alive of device, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when device is not subject to voltage effect, by controlling the F ion of adulterating in the second insulator in MIS around the 3rd based semiconductor 300 or C1 ion concentration, the second raceway groove 202 is made to exhaust pinch off, realize device often to close, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 201 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode; F ion that the second raceway groove 202 exhausts can be realized or C1 ion concentration is 10
12~ 10
20cm
-3.
As shown in Figure 9, a kind ofly enclosing the cross section structure of gate heterojunction device along A-B line in Fig. 1, is that the third can realize the second raceway groove 202 when the non-making alive of device and exhausts method, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when device is not subject to voltage effect, by controlling the F ion of adulterating in the 3rd based semiconductor 300 barrier layer of heterojunction in MIS or C1 ion concentration, the second raceway groove 202 is made to exhaust pinch off, realize device often to close, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 201 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode; F ion that the second raceway groove 202 exhausts can be realized or C1 ion concentration is 10
12~ 10
20cm
-3.
As shown in Figure 10, a kind ofly enclosing the cross section structure of gate heterojunction device along A-B line in Fig. 1, is the 4th kind of method that can realize the second raceway groove 202 when the non-making alive of device and exhaust, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when device is not subject to voltage effect, by magnesium ion or sodium ion or the iron concentration of doping in the Equations of The Second Kind semiconductive thin film 200 immediately below the second raceway groove 202 in control MIS, the second raceway groove 202 is made to exhaust pinch off, realize device often to close, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 201 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode; Can realize magnesium ion that the second raceway groove 202 exhausts or sodium ion or iron concentration is 10
12~ 10
20cm
-3.
As shown in figure 11, a kind ofly enclosing the cross section structure of gate heterojunction device along A-B line in Fig. 1, is the 5th kind of method that can realize the second raceway groove 202 when the non-making alive of device and exhaust, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when device is not subject to voltage effect, by controlling F ion or the C1 ion concentration of the inner doping of Equations of The Second Kind insulator (600) in the thickness of the 3rd based semiconductor 300 barrier layer in MIS structure and MIS around the 3rd based semiconductor 300, the second raceway groove 202 is made to exhaust pinch off, realize device often to close, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 202 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode; The thickness that can realize the 3rd based semiconductor 300 barrier layer in the MIS that the second raceway groove 202 exhausts is 1 ~ 50 nanometer, and the concentration of F ion or C1 ion is 10
12~ 10
20cm
-3.
As shown in figure 12, a kind ofly enclosing the cross section structure of gate heterojunction device along A-B line in Fig. 1, is the 6th kind of method that can realize the second raceway groove 202 when the non-making alive of device and exhaust, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when device is not subject to voltage effect, by controlling the F ion of the 3rd based semiconductor 300 barrier layer doping or the concentration of C1 ion in the thickness of the 3rd based semiconductor 300 barrier layer in MIS structure and MIS structure, the second raceway groove 202 is made to exhaust pinch off, realize device often to close, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 201 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode; The thickness that can realize the 3rd based semiconductor 300 barrier layer in the MIS that the second raceway groove 202 exhausts is 1 ~ 50 nanometer, and the concentration of F ion or C1 ion is 10
12~ 10
20cm
-3.
As shown in figure 13, a kind ofly enclosing the cross section structure of gate heterojunction device along A-B line in Fig. 1, is the 7th kind of method that can realize the second raceway groove 202 when the non-making alive of device and exhaust, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when the non-making alive of device, the magnesium ion adulterated by the Equations of The Second Kind semiconductive thin film 200 controlled in the thickness of the 3rd based semiconductor 300 barrier layer in MIS structure and MIS structure immediately below the second raceway groove 202 or sodium ion or iron concentration, second raceway groove 202 is exhausted, realize device often to close, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 202 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode; The thickness that can realize the 3rd based semiconductor 300 barrier layer in the MIS that the second raceway groove 202 exhausts is 1 ~ 50 nanometer, and the concentration of magnesium ion or sodium ion or iron ion is 10
12~ 10
20cm
-3.
As shown in figure 14, a kind ofly enclosing the cross section structure of gate heterojunction device along A-B line in Fig. 1, is the 8th kind of method that can realize the second raceway groove 202 when the non-making alive of device and exhaust, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when the non-making alive of device, by controlling F ion or the C1 ion concentration of the Equations of The Second Kind insulator 600 li doping in the F ion of adulterating in the 3rd based semiconductor 300 barrier layer in MIS structure or C1 ion concentration and MIS structure around the 3rd based semiconductor 300, make the second raceway groove 200 exhaust shutoff, realize device and often close; By controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 201 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode; The concentration that can realize F ion that the second raceway groove 202 exhausts or C1 ion is 10
12~ 10
20cm
-3.
As shown in figure 15, a kind ofly enclosing the cross section structure of gate heterojunction type device along A-B line in Fig. 1, is the 9th kind of method that can realize the second raceway groove 202 when the non-making alive of device and exhaust, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when the non-making alive of device, the magnesium ion adulterated by the Equations of The Second Kind semiconductive thin film 200 controlled in the F ion of adulterating in the 3rd based semiconductor 300 barrier layer in MIS structure or C1 ion concentration and MIS structure immediately below the second raceway groove 202 or sodium ion or iron concentration, second raceway groove 202 is exhausted, realize device often to close, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 201 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode, the concentration that can realize F ion that the second raceway groove 202 exhausts or C1 ion and magnesium ion or sodium ion or iron ion is 10
12~ 10
20cm
-3.
As shown in figure 16, a kind ofly enclosing the cross section structure of gate heterojunction type device along A-B line in Fig. 1, is the tenth kind of method that can realize the second raceway groove 202 when the non-making alive of device and exhaust, mainly by the metal molar composition of control the 3rd based semiconductor (as Al
xga
1-xn/Al
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1, In
xga
1-xn/In
xga
1-xin N heterojunction, the value of mole coefficient x is between 0 ~ 1), and when the non-making alive of device, by controlling the magnesium ion of doping in the Equations of The Second Kind semiconductive thin film 200 in the F ion of adulterating in the Equations of The Second Kind insulator in MIS structure around the 3rd based semiconductor 300 or C1 ion concentration and MIS structure immediately below the second raceway groove 202 or sodium ion or iron concentration, second raceway groove 202 is exhausted, by controlling the length control device of length that the second raceway groove 202 exhausts and drift region first raceway groove 201 and drift region triple channel 203 as forward and reverse trigger threshold voltage during diode, the concentration that can realize F ion that the second raceway groove 202 exhausts or C1 ion and magnesium ion or sodium ion or iron ion is 10
12~ 10
20cm
-3.
Three combinations that additive method that the second raceway groove 202 exhausts is first method, second method, the third method, the 4th kind of method can be realized when the non-making alive of device, or four combinations, and P doping in the 3rd based semiconductor 300 potential barrier, the atom of energy P doping has magnesium, iron, sodium etc., and in the 3rd that based semiconductor 300 potential barrier, the concentration of P doping is 10
12~ 10
20cm
-3, specific implementation method is similar to the above, is not repeated here.
As shown in figure 17, it is a kind of octangle structure cell plane graph that regular polygon encloses in gate heterojunction device structure cell, innermost octangle is drain terminal 700, what surround drain terminal 700 is that octangle encloses grid structure 702, eight grooves 701 have been dug at octagonal eight angles, form one between two adjacent grooves and groove and enclose grid grid, enclose grid 702 and groove 701 surface coverage has the first metal 600; Surround the octangle source that octangle encloses grid structure, what surround octangle source is first kind insulator, and other polygonal structure cells are also similar.
As shown in figure 18, be the plane graph that gate heterojunction device structure cell is enclosed in bar shaped, cellular is from left to right leakage the 800, three based semiconductor 801 respectively, encloses grid 803, groove 802, the 3rd based semiconductor 804, source 805, and the first insulator 806; Groove 802 part is that the first kind semiconductor of first cellular surface and Equations of The Second Kind semiconductor are hollowed out, and is coated with the first metal 600 enclosing on grid 803 and groove 802.
As shown in figure 19, be the plane graph that rectangle quadrangle encloses gate heterojunction device structure cell, structure cell is drain terminal 900 from the inside to surface respectively, the 3rd based semiconductor 901, and groove 902, encloses grid 903, the 3rd based semiconductor 904, source 905, and the first insulator 906; Groove 902 part is that the first kind semiconductive thin film of first cellular surface and Equations of The Second Kind semiconductive thin film are hollowed out, and is coated with the first metal 600 enclosing on grid 903 and groove 903; Other oval and circular structure cells and quadrangle cellular similar.
Structure for a better understanding of the present invention, the invention provides a kind of Making programme enclosing gate heterojunction type device:
The first step: adopt organic chemistry deposition process on a silicon substrate, depositing Al successively
xga
1-xn and GaN, Al
xga
1-xn and GaN junction forms Al
xga
1-xn/GaN heterojunction, as Figure 20;
Second step: in GaN layer, by the method such as magnetron sputtering, PECVD, ALD, (the ε of depositing high dielectric constant
r> 6) the first insulating barrier (400).First insulating barrier can be in following material a kind of: Al
2o
3, TiO
2, AlN, Si
3n
4, SiN
x, MgO, Sc
2o
3, HfO
2, Ga
2o
3and multi-element compounds insulating material AlHfO
x, HfSiON etc.Deposit height K first insulating barrier (400) short annealing afterwards: at 300-1200 DEG C, short annealing in 1-10 minute, as Figure 21.
3rd step: with alcohol, acetone and deionized water respectively to Al
xga
1-xn/GaN heterojunction carries out ultrasonic cleaning, and nitrogen dries up rear ion etching process and etches ohmic contact regions at GaN two ends, and etching gas is BCl
3, then deposited by electron beam evaporation growth Ohm contact electrode (Ti/Al/Au) and under 850 DEG C of N2 atmosphere short annealing be about 30s, as Figure 22;
The MgO of 500nm is about with pulsed laser deposition
2film as mask, at Al
xga
1-xupper two the ohmic contact intervals of N etch groove grids window, as shown in figure 23, also can by the method for distributed extension, at Al
xga
1-xn inside and outside epitaxial growth goes out groove grids window, then uses the method such as magnetron sputtering, PECVD, ALD, the Al between GaN layer and two ohmic contact regions
xga
1-x(the ε of the upper depositing high dielectric constant of N
r> 6) the second insulating barrier 500.First insulating barrier 400 can be in following material a kind of: Al
2o
3, AlN, Si
3n
4, SiN
x, TiO
2, MgO, Sc
2o
3, HfO
2, Ga
2o
3and multi-element compounds insulating material AlHfO
x, HfSiON etc.Deposit height K first insulating barrier (400) short annealing afterwards: at 300-1200 DEG C, short annealing in 1-10 minute; As shown in figure 24;
4th step: again with groove grids evaporation growth first metal area 600 of electron beam in AB direction, as shown in figure 25.
Claims (10)
1. one kind is enclosed gate heterojunction device, comprise the first kind Semiconductor substrate (100), Equations of The Second Kind semiconductive thin film (200) and the 3rd based semiconductor film (300) that set gradually from the bottom up, described Equations of The Second Kind semiconductive thin film (200) and the 3rd based semiconductor film (300) form heterojunction in junction, the two ends of described 3rd based semiconductor film (300) are respectively arranged with the first ohmic contact (301) and the second ohmic contact (302), described heterojunction boundary place has the first raceway groove (201), the second raceway groove (202) and triple channel (203) near the first ohmic contact (301) one end successively near the second ohmic contact (302) one end, described second ohmic contact (302) has the first insulator (400) away from the side of the first ohmic contact (301), and the bottom surface of described first insulator (400) is connected with the upper surface of Equations of The Second Kind semiconductive thin film (200), have grid (303) between described first ohmic contact (301) and the second ohmic contact (302), described grid (303) is for enclosing grid structure, described grid (303) comprises the second insulator (500) and is arranged on the metal area (600) of the second insulator (500) upper surface, described second insulator (500) is positioned at first kind Semiconductor substrate (100) upper surface, described Equations of The Second Kind semiconductive thin film (200) and the 3rd based semiconductor film (300) pass the second insulator (500) along device horizontal direction, described metal area (600), second insulator (500) and be arranged in the 3rd based semiconductor film (300) of the second insulator (500) and Equations of The Second Kind semiconductive thin film (200) forms MIS structure, described second raceway groove (202) is arranged in immediately below MIS structure the 3rd based semiconductor (300), described first raceway groove is positioned at immediately below the 3rd based semiconductor film (300) between grid (303) and the first ohmic contact (301), and described triple channel is positioned at immediately below the 3rd based semiconductor film (300) between grid (303) and the second ohmic contact (302).
2. one according to claim 1 encloses gate heterojunction device, it is characterized in that, described first kind Semiconductor substrate (100) is sapphire, one in silicon and carborundum; Described Equations of The Second Kind semiconductive thin film (200) and the 3rd based semiconductor film (300) are three races-five compounds of group, and can form heterojunction at Equations of The Second Kind semiconductor (200) and the contact interface place of the 3rd based semiconductor (300).
3. one according to claim 1 encloses gate heterojunction device, it is characterized in that, described metal area (600) have the metal that work function is greater than 4.0eV.
4. one according to claim 3 encloses gate heterojunction device, it is characterized in that, the metal that described metal area (600) are arranged is one or more in Ti, Ni, Al, Au, Pt, No, W, Ag, Mo and Pb.
5. one according to claim 1 encloses gate heterojunction device, it is characterized in that, have the 3rd based semiconductor film (300) barrier layer that the second raceway groove (202) can be made to exhaust in described MIS structure, the thickness of the 3rd described based semiconductor film (300) barrier layer is 1 ~ 50 nanometer.
6. one encloses gate heterojunction type device according to claim 1 or 5, it is characterized in that, have the F ion or C1 ion that the second raceway groove (202) can be made to exhaust in 3rd based semiconductor film (300) Equations of The Second Kind insulator (500) around in described MIS structure, described F ion or C1 concentration are 10
12~ 10
20cm
-3.
7. one according to claim 5 encloses gate heterojunction type device, it is characterized in that, have the F ion or C1 ion that the second raceway groove (202) can be made to exhaust in described 3rd based semiconductor film (300) barrier layer, described F ion or C1 ion concentration are 10
12~ 10
20cm
-3.
8. the one according to claim 1 or 5 or 7 encloses gate heterojunction device, it is characterized in that, the Equations of The Second Kind semiconductive thin film (200) be arranged in described MIS structure immediately below the second raceway groove (202) has the magnesium ion or sodium ion or iron ion that the second raceway groove (202) can be made to exhaust, and described magnesium ion or sodium ion or iron concentration are 10
12~ 10
20cm
-3.
9. one according to claim 6 encloses gate heterojunction device, it is characterized in that, doped with F ion or C1 ion in the 3rd based semiconductor (300) barrier layer in described MIS structure, the two-dimensional electron gas being provided for the second raceway groove (202) exhausts; The concentration of described F ion or C1 ion is 10
12~ 10
20cm
-3.
10. one according to claim 9 encloses gate heterojunction type device, it is characterized in that, being arranged in Equations of The Second Kind semiconductive thin film (200) immediately below the second raceway groove (202) in described MIS structure doped with magnesium ion or sodium ion or iron ion, exhausting for making the two-dimensional electron gas of the second raceway groove (202); The concentration of described F ion or C1 ion and described magnesium ion or sodium ion or iron ion is 10
12~ 10
20cm
-3.
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Cited By (1)
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| CN111341841A (en) * | 2020-02-27 | 2020-06-26 | 杭州电子科技大学 | Based on Ga2O3/TiO2Heterojunction field effect tube of composite suspended floating gate, preparation method thereof and ultraviolet detector |
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| CN111341841B (en) * | 2020-02-27 | 2022-08-26 | 杭州电子科技大学 | Based on Ga 2 O 3 /TiO 2 Heterojunction field effect tube of composite suspended floating gate, preparation method thereof and ultraviolet detector |
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