CN104979271A - Interconnection structure formation method - Google Patents
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- CN104979271A CN104979271A CN201410133369.XA CN201410133369A CN104979271A CN 104979271 A CN104979271 A CN 104979271A CN 201410133369 A CN201410133369 A CN 201410133369A CN 104979271 A CN104979271 A CN 104979271A
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Abstract
The invention provides an interconnection structure formation method. The method comprises that after a dielectric layer is formed on a semiconductor substrate, a first mask which takes a metal mask as the material is formed on the dielectric layer, then a second mask is formed on the first mask, first etching is performed taking the second mask as the mask, and through holes are formed in the dielectric layer; and after the first mask exposed by the second mask is removed, second etching is performed taking the first mask as the mask, trenches are formed in the dielectric layer, and the second etching utilizes a non-fluorine-based etching agent. In the process of the second etching, the etching agent adopts the non-fluorine-based etching agent, so that a phenomenon that fluorinions and the metal mask react to generate by-products containing metal fluoride in the second etching is effectively prevented, and the metal fluoride is further prevented from reacting with the dielectric layer to damage the dielectric layer, thereby reducing damage of etching on the dielectric layer.
Description
Technical field
The present invention relates to technical field of semiconductors, especially relate to a kind of formation method of interconnection structure.
Background technology
Along with semiconductor technology evolves, the integrated level of device constantly increases, and device feature size (CriticalDimension, CD) is more and more less.
And reduce gradually along with characteristic size obtains, it is increasing on the impact of semiconductor device that the reason such as parasitic capacitance between interconnection structure and the RC that produces postpone (RC delay).The K value reducing interconnection structure dielectric layer material effectively reduces the method for RC late effect.In recent years, low-K dielectric material (K < 3) is to become the mainstay material of dielectric layer gradually, and along with semiconductor device development demand, the K value of the dielectric layer material adopted constantly reduces.
Prior art also adopts the less copper of resistance coefficient to replace the material of traditional aluminium as the metal plug in interconnection structure, to reduce the resistance of metal plug self.Meanwhile, because the fusing point of copper is high, and anti-electromigration ability is also stronger, relative to the metal plug of traditional aluminum, can carry higher current density, enters to be conducive to and improves the packaging density of the chip of formation.Particularly, prior art adopts Damascus (Damascene) or dual damascene (Dual Damascene) technique to form the metal plug of copper.
The groove (Trench) and the through hole (Via) that are defined needs formation by photoresist is generally needed in dual damascene process, low-K dielectric material or super low-K dielectric material mostly are loose porous structure, and the process removing photoresist easily causes damage to described low-K dielectric material or super low-K dielectric material.Impaired low-K dielectric material becomes and more easily absorbs water, and is easy to react with other processing contaminants and change the electrology characteristic of dielectric layer, thus causes low-K dielectric material K value increase and reduce performance of semiconductor device.
How to reduce the problem that the impaired those skilled in the art of being of low-K dielectric material need solution badly for this reason.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of interconnection structure, reduces the problem that low-K dielectric material is impaired, improves the performance of the semiconductor device formed.
For solving the problem, the invention provides a kind of formation method of interconnection structure, for the formation of the interconnection structure with damascene structure, described formation method comprises:
Semiconductor substrate is provided;
Form dielectric layer on the semiconductor substrate;
Described dielectric layer is formed the first mask being used for forming groove in the dielectric layer, and described first mask is metal mask;
Described first mask is formed the second mask being used for forming through hole in the dielectric layer;
With described second mask for mask carries out the first etching to described dielectric layer, to form through hole in described dielectric layer;
Remove described second mask and expose described first mask;
With described first mask for mask carries out the second etching to described dielectric layer, to form groove in described dielectric layer, described second etching adopts non-fluorine-based etching agent.
Alternatively, with described first mask, the step that described dielectric layer carries out the second etching is comprised: one or more in employing hydrogen, nitrogen, oxygen or argon gas carry out dry quarter to dielectric layer.
Alternatively, in the step of described second etching, in described etching gas, the percent by volume of hydrogen is 10% ~ 90%.
Alternatively, the step of described second etching comprises:
Power is 50 ~ 1000W, and gas flow is 10 ~ 1000sccm, and air pressure is 5mtorr ~ 500mtorr, and temperature is 50 ~ 150 DEG C.
Alternatively, the material of described metal mask is titanium nitride, boron nitride or aluminium nitride.
Alternatively, after the second etching, also comprise the step of wet-cleaned.
Alternatively, the step of described wet-cleaned comprises: adopt hydrogen fluoride solution to carry out wet-cleaned.
Alternatively, with described second mask for mask comprises the step that described dielectric layer carries out the first etching: adopt non-fluorine-based etching agent to carry out the first etching to described dielectric layer.
Alternatively, non-fluorine-based etching agent is adopted to comprise the step that described dielectric layer carries out the first etching: to adopt the etching gas comprising hydrogen to carry out dry quarter, to form through hole to described dielectric layer.
Alternatively, described second mask is photoresist.
Alternatively, after the described groove of formation, before described cleaning step, also comprise reparation step, form protective layer at the groove formed and the sidewall of through hole and bottom.
Alternatively, described reparation step comprises that to pass into flow be the gas that 100 ~ 1000sccm contains He or Ar, and the duration is 10s ~ 30min.
Alternatively, the material of described dielectric layer is low-K dielectric material or super low-K dielectric material.
Compared with prior art, technical scheme of the present invention has the following advantages:
Formed after dielectric layer on a semiconductor substrate, being formed on the dielectric layer with metal mask is the first mask of material, forms the second mask afterwards, and carries out the first etching with the second mask for mask, in dielectric layer, form through hole on the first mask; Remove after the second mask exposes the first mask afterwards, carry out the second etching with the first mask for mask, in dielectric layer, form groove, and described second etching adopts non-fluorine-based etching agent.In the second etching process, the etching agent adopted is non-fluorine-based etching agent, thus effectively avoid in the second etching technics, fluorine ion and metal mask react the accessory substance formed containing metal fluoride (MeFx), this part metal fluoride and dielectric layer can also be reduced react further and cause dielectric layer to damage, and then reduce etching technics dielectric layer is damaged; In addition, second etching adopts non-fluorine-based etching agent also can effectively avoid fluorine ion, metal fluoride and dielectric layer react further and form new etch by-products, and be reduced in the accessory substance that produces in etching process for the interconnection structure impact formed, and then cause the interconnection structure performance impact for follow-up formation.
Further, in the first etch step, adopt dielectric layer described in non-fluorine-based etchant, thus reduce further in etching process based on the accessory substance that fluorine ion, metal mask, dielectric layer reaction are formed; In addition, in first etch step and the second etch step, all avoid adopting fluorine base gas as etching agent, fluorine ion in the etching process of dielectric layer can be effectively avoided to remain in dielectric layer or hard mask layer, thus fluorine ion causes dielectric layer to damage in the subsequent technique avoiding semiconductor device to prepare, and then affect the performance of semiconductor device of follow-up formation.
Further, after the step of the second etching forms groove, reparation step was also comprised before described cleaning step, described reparation step can realize the sidewall of the through hole in dielectric layer, and the sidewall of groove and bottom densification, at the sidewall of described through hole, and protective layer is formed on the sidewall of groove and bottom, the problem utilizing the compact surfaces of protective layer to seal dielectric material dielectric material can be avoided to make moist in semiconductor preparation; And described protective layer also can effectively reduce the problem spread in metallic atom dielectric layer in the metal material be filled in groove and through hole, improves the reliability and stability of the interconnection structure of follow-up formation.
Accompanying drawing explanation
The structural representation after groove is formed in the existing a kind of low-K dielectric material layer of Fig. 1;
Fig. 2 ~ Fig. 4 existingly forms groove in low-K dielectric material layer, and in groove, fill the Electronic Speculum figure after metal material;
Fig. 5 ~ Fig. 9 is the structural representation of an embodiment of the formation method adopting interconnection structure of the present invention.
Embodiment
As stated in the Background Art, in prior art, formed in the process of groove in the dielectric layer of low-K dielectric material (K < 3), low-K dielectric material easily sustains damage, thus reduces the performance of the interconnection structure of follow-up formation.In conjunction with reference to the prior art shown in figure 1 and its reason of Electronic Speculum map analysis referring to figs. 2 to metal material in the groove shown in Fig. 4:
As shown in Figure 1, when prior art forms groove 13 in the dielectric layer of low-K dielectric material (K < 3), fluorine (F) base gas is mostly adopted to etch the dielectric layer 11 be positioned in Semiconductor substrate 10 as etching gas.In etching process, F base gas can react with metal hard mask 12 accessory substance formed containing metal fluoride (MeFx), and when with F base gas etch dielectric layer 11, F base gas, metal fluoride, and dielectric layer reacts further, thus cause dielectric layer 11 to damage, damage the defect such as groove 13 sidewall and bottom 14 evenness.As shown in Figure 2, (Fig. 2 is the Electronic Speculum figure fill metal material 15 in groove 13 after), existing metal hard mask layer 12 material mostly is the metal nitrides such as TiN, F base gas can react with TiN, form all kinds of accessory substances such as TiFx, this part accessory substance is mixed in metal material, thus the electric property of the final interconnection structure formed of impact, as reduced the TDDB of semiconductor device.
In addition, existing low-K dielectric material mostly is multi-pore structure, and in employing F base gas etching dielectric layer 11 process, part F ion remains in dielectric layer 11, thus in semiconductor device subsequent preparation process, causes dielectric layer to damage.Electronic Speculum figure bottom composition graphs 3(groove 13) and Fig. 4 (the sidewall Electronic Speculum figure of groove 13), easily there is damage in the sidewall 14 of groove 13 and bottom 15, reduces the inwall evenness of groove 13, affect the form of the interconnection structure of follow-up formation.
In order to solve the problem, the invention provides a kind of formation method of interconnection structure, effectively alleviate the damage that low k dielectric layer is subject to.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 5 ~ Fig. 9 is the structural representation of a formation method embodiment of interconnection structure of the present invention.
The formation method of the interconnection structure that the present embodiment provides comprises:
Shown in first reference diagram 5, Semiconductor substrate 30 is provided, described Semiconductor substrate 30 forms dielectric layer 31.
In the present embodiment, described Semiconductor substrate 30 comprises: semiconductor base or semiconductor base and be formed in semiconductor base or the semiconductor components and devices of semiconductor substrate surface, described semiconductor components and devices comprises cmos device, described cmos device comprises transistor, memory, capacitor or electric part, with the electric interconnection structure for making described semiconductor components and devices be electrically connected, and for the structure such as insulating barrier of semiconductor components and devices described in electric isolution and electric interconnection structure.
Described semiconductor base is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V substrate, and described semiconductor base materials does not limit protection scope of the present invention.
In the present embodiment, the material of described dielectric layer 31 is low-K dielectric material (K value is less than 3) or super low-K dielectric material (K value is less than 2.6).Follow-uply formed after interconnection structure in described dielectric layer 30, low-K dielectric material can effectively reduce the parasitic capacitance of interconnection structure, thus reduces RC delays (RC Delay) effect occurred when signal transmits in interconnection structure.
Alternatively, in the present embodiment, described dielectric layer 31 adopts super low-K dielectric material.
In the present embodiment, described dielectric layer 31 mostly is loose structure, as the silica of the carbon dope of loose structure.The formation process of the silica of the carbon dope of described loose structure comprises: first adopt chemical vapor deposition method to form carbon doped silicon oxide layer in Semiconductor substrate 30, adopt porous treatment process (such as UV treatment technique) to process the silicon oxide layer of described carbon dope afterwards, form the silicon oxide layer of the carbon dope of porous.
Afterwards, etch described dielectric layer 31, in described dielectric layer 31, form through hole and groove, described through hole and groove follow-up for filling metal material, to form interconnection structure.
In the present embodiment, the method forming through hole and groove in described dielectric layer 31 comprises:
Continue with reference to shown in figure 5, first on dielectric layer 31, form the first hard mask layer 32, afterwards, described first hard mask layer 32 forms silicon oxide layer 39, light optimization (OpticalDevelopment Layer from the bottom to top successively, ODL) layer 37, silicon antireflection (Si-anti Reflection Coating, Si-ARC) layer 38 and the first photoresist layer 33; After after exposure imaging technique, channel patterns is formed in described first photoresist layer 33, and along described channel patterns, etch described silicon antireflection (Si-anti ReflectionCoating, Si-ARC) layer 38, light optimization (Optical Development Layer, ODL) layer 37, silicon oxide layer 39 and the first hard mask layer 32, be transferred to channel patterns 41 in described first hard mask layer 32.
Described first hard mask layer 32 is metal hard mask layer, and concrete material comprises titanium nitride (TiN), boron nitride (BN) or aluminium nitride (AlN).
In the present embodiment, the material of described first hard mask layer 32 is TiN.
It should be noted that in the present embodiment, described ODL layer 37, Si-ARC layer 38, effectively can improve the precision of the pattern formed in the first hard mask layer 32; Described silicon oxide layer 39 can improve the bond strength of described first hard mask layer 32 and described ODL layer 37, if but do not form described silicon oxide layer 39, ODL layer 37, Si-ARC layer 38 do not affect object of the present invention and realize.Whether form described silicon oxide layer 39, ODL layer 37, Si-ARC layer 38 do not affect in protection scope of the present invention, do not repeat them here.
In the present embodiment, alternatively, the etching gas that above-mentioned etching first hard mask layer 32 adopts is non-fluorine (F) base gas, the gas containing HBr can be adopted particularly to be described first hard mask layer 32 of etching gas etching, thus avoid fluorine base gas and the first hard mask layer 32 to react the compound (TiFx) forming titanium and fluorine, thus in subsequent interconnect structure formation process, the compound of titanium and fluorine and etching gas or dielectric layer reacts, reduce the amount that etch by-products is formed; In addition, also can avoid in etching process, the F ion of generation remains in described first photoresist layer 33, or in described first hard mask layer 32 and dielectric layer 31, thus in follow-up interconnection structure formation process, avoid F ion to cause dielectric layer 31 to damage.
Then combine with reference to shown in figure 6, form described channel patterns 41 in described first hard mask layer 32 after, remove described first photoresist layer 33, ODL layer 37 and Si-ARC layer 38, and on the surface of described silicon oxide layer 39, form light optimization (optical development layer, ODL) layer 34, silicon antireflection (Si-ARC) layer 35 and the second photoresist layer 36 successively more from the bottom to top.Described ODL layer 34 fills full described channel patterns 41.After through exposure imaging technique, in described second photoresist layer 36 formed through-hole pattern 42.
In conjunction with reference to shown in figure 7, carry out the first etching technics along described through-hole pattern 42, etch described Si-arc layer 35, ODL layer 34, silicon oxide layer 39 and the first hard mask layer 32 and dielectric layer 31 successively, in described dielectric layer 31, form through hole 43.
In the present embodiment, described through hole 43 runs through described dielectric layer 31, until Semiconductor substrate 30 described in exposed portion.
It should be noted that; in the present embodiment; described Si-arc layer 35, ODL layer 34 effectively can improve follow-up through hole 43 precision be formed in described dielectric layer 31; but in other embodiments except the present embodiment; described Si-arc layer 35 and ODL layer 34 can not be formed; it can realize object of the present invention equally, and described Si-arc layer 35, ODL layer 34 do not affect described protection scope of the present invention.
Described first etching technics is dry etch process.
Alternatively, in the present embodiment, described dry etch process adopts non-F base etching agent, the gas of described non-F base etching agent not containing F.Thus avoid the accessory substance that formed in the first hard mask layer 32, dielectric layer 31 and previous etching technics, the accessory substance formed containing F is reacted with F ion, and then damage when reducing etching described dielectric layer 31, dielectric layer 31 caused, reduce the performance impact of accessory substance for the interconnection structure of follow-up formation that these contain F simultaneously; In addition adopt non-F base etching agent also can effectively avoid F ion to remain in described second photoresist layer 36 and dielectric layer 31, thus avoid in the follow-up formation process of interconnection structure, F ion causes dielectric layer 31 to damage.
Particularly, in the present embodiment, described in the first etching technics, the technological parameter of dielectric layer 31 comprises:
Adopt containing hydrogen (H
2) gas as etching gas, power is 50 ~ 1000W, and gas flow is 10 ~ 1000sccm, and air pressure is 5mtorr ~ 500mtorr, and temperature is 50 ~ 150 DEG C.
Further alternatively, in the present embodiment, described dry etching gas also can comprise assist gas, and described assist gas contains N
2, O
2or one or more in Ar.Wherein, in described etching gas, H
2percent by volume be 10% ~ 90%, the concrete composition of described etching gas and ratio can according to the thickness of dielectric layer 31, and etching requirement is determined.
In conjunction with described in reference diagram 8, form described through hole 43 in dielectric layer 31 after, remove glue-line 36 at described quarter, Si-arc layer 35 and ODL layer 34, expose described silicon oxide layer 39, and along the channel patterns 41(in described silicon oxide layer 39 and the first hard mask layer 32 as shown in Figure 5) carry out the second etching technics, continue the described dielectric layer 31 of etching, form groove 44 on described dielectric layer 31 surface.
In the present embodiment, etch described dielectric layer 31, the second etching technics forming described groove 44 is dry etch process, and described second etching technics adopts non-F base etching agent, and described non-F base etching agent is not containing F base gas.
In the present embodiment, described second etching technics comprises: with containing hydrogen (H
2) gas be dry etching, power is 50 ~ 1000W, and gas flow is 10 ~ 1000sccm, and air pressure is 5mtorr ~ 500mtorr, and temperature is 50 ~ 150 DEG C.
Further alternatively, described etching gas also can comprise assist gas, and described assist gas comprises N
2, O
2or one or more in Ar.Wherein, in described etching gas, H
2percent by volume be 10% ~ 90%.
In an embodiment of described second etching technics, the temperature of etching technics is controlled in 50 ~ 60 DEG C.At such a temperature, the etch rate of described silicon oxide layer 39 is greater than the etch rate of described first hard mask layer 32, thus increase the opening of the follow-up groove 44 formed in silicon oxide layer 39, be convenient to fill metal material in described groove 44 and through hole 43, and the density of the metal material in groove 44 and through hole 43 can be improved, thus improve the performance of the interconnection structure of follow-up formation.
In another embodiment of described second etching technics, the temperature of etching technics is controlled in 100 ~ 150 DEG C.At such a temperature, when effectively can reduce the described dielectric layer of etching, etching gas, dielectric layer, and the amount of polymer that the reaction between the accessory substance formed in each etching technics is before formed.
In the present embodiment, the technique removing the first photoresist layer 33 and the second photoresist layer 36 is chosen as wet-etching technology, or cineration technics, and it is the mature technology of this area, does not repeat them here.
Shown in figure 9, in the present embodiment, formation described groove 44 after, carry out reparations step, thus realize described dielectric layer 31 surface densification, at the sidewall of the through hole 43 of described dielectric layer 31, and the sidewall of groove 44 and bottom formation protective layer 45.
In the present embodiment, the concrete technology of described reparation step comprises:
The power controlled in reaction chamber is 100 ~ 2000W, and continuing to pass into flow is gas 10 seconds (s) ~ 30 minute (min) that 100 ~ 1000sccm contains He or Ar.
In the present embodiment, adopt cineration technics to remove the first photoresist layer and the second photoresist layer in removal, and etch in the technique of described dielectric layer 31, unavoidably cause described dielectric layer 31 to damage.Especially under the high temperature conditions, as at 100 ~ 150 DEG C, the damage of low-K dielectric material is larger.
The easier moisture absorption of low-K dielectric material after impaired, and with other pollutant reactions, thus affect the electric property of dielectric layer 31 entirety.In the present embodiment, after described reparation step, can at the sidewall of described through hole 43, and after described protective layer 45 is formed on the sidewall of groove 44 and bottom, the low-K dielectric material can effectively alleviated below described protective layer 45 is subject to wet environment damage; In addition, follow-up in described through hole 43 and groove 44, fill metal material after, described protective layer 45 can effectively avoid metallic atom to spread in described dielectric layer 31, thus improves the stability of the interconnection structure of follow-up formation.
In the present embodiment, after described reparation step, semiconductor device is taken out reaction chamber, and cleaning step is carried out to the described through hole 43 formed and groove 44.
In above-mentioned etch step, etching residue can be formed at the sidewall of described through hole 43 and groove 44, described cleaning step can effectively remove this part etching residue, with reduce described through hole 43 and groove 44 in, fill metal material formation interconnection structure after remain in etching residue in interconnection structure, and reduce described etching residue thus the electric property of interconnection structure affected.
In the present embodiment, the cleaning fluid that described cleaning step adopts comprises DHF solution (dilute hydrofluoric acid solution), (the solute main component of EKC solution comprises the EKC solution of dilution: azanol (HDA); 2-(2-amino ethoxy) ethanol (DGA); Neck benzenediol (Catechol)) or H
2o
2solution (hydrogen peroxide solution).
In the present embodiment, the cleaning fluid of employing adopts DHF solution, and wherein in DHF solution, the volume ratio of HF and water is 1:300 ~ 1:1000.
Above-mentioned protective layer 45 in through hole 43 and groove 44, also effectively can reduce the corrosion of described cleaning solution for low-K dielectric material.
Compared in prior art, adopt containing after F base gas etching dielectric layer 31, part F ion can remain in described dielectric layer 31, and by after taking out described semiconductor device in reaction chamber, the F base gas remained in dielectric layer 31 can react with the steam in air and form HF solution, thus corrosion dielectric layer 31.The first etching technics in the present invention and the second etching technics adopt non-F base etching agent, thus effectively alleviate for these reasons to the damage of dielectric layer 31.
In addition, in the preparation technology of semiconductor device, after the described groove 44 of formation, obtain and carry out cleaning rapidly, thus avoid residuing in the F ion in dielectric layer 31 and the water in air reacts.After this example effectively can increase formation groove 44, with the time of staying in the middle of cleaning step, thus increase process window, reduce semiconductor device preparation cost.
After described cleaning step, metal material can be filled in described through hole 43 and groove 44, and adopt the techniques such as cmp (CMP) to remove unnecessary metal material, and the first hard mask layer 32 on dielectric layer 31 and silicon oxide layer 39, expose described dielectric layer 31, dielectric layer 31 surface is flushed with the layer on surface of metal in described groove 44, to form interconnection structure.This step is the mature technology of this area, does not repeat them here.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (13)
1. a formation method for interconnection structure, for the formation of the interconnection structure with damascene structure, is characterized in that, described formation method comprises:
Semiconductor substrate is provided;
Form dielectric layer on the semiconductor substrate;
Described dielectric layer is formed the first mask being used for forming groove in the dielectric layer, and described first mask is metal mask;
Described first mask is formed the second mask being used for forming through hole in the dielectric layer;
With described second mask for mask carries out the first etching to described dielectric layer, to form through hole in described dielectric layer;
Remove described second mask and expose described first mask;
With described first mask for mask carries out the second etching to described dielectric layer, to form groove in described dielectric layer, described second etching adopts non-fluorine-based etching agent.
2. form method as claimed in claim 1, it is characterized in that, with described first mask, the step that described dielectric layer carries out the second etching is comprised: one or more in employing hydrogen, nitrogen, oxygen or argon gas carry out dry quarter to dielectric layer.
3. form method as claimed in claim 2, it is characterized in that, in the step of described second etching, in described etching gas, the percent by volume of hydrogen is 10% ~ 90%.
4. form method as claimed in claim 1, it is characterized in that, the step of described second etching comprises: power is 50 ~ 1000W, and gas flow is 10 ~ 1000sccm, and air pressure is 5mtorr ~ 500mtorr, and temperature is 50 ~ 150 DEG C.
5. form method as claimed in claim 1, it is characterized in that, the material of described metal mask is titanium nitride, boron nitride or aluminium nitride.
6. form method as claimed in claim 1, it is characterized in that, after the second etching, also comprise the step of wet-cleaned.
7. form method as claimed in claim 6, it is characterized in that, the step of described wet-cleaned comprises: adopt hydrogen fluoride solution to carry out wet-cleaned.
8. form method as claimed in claim 1, it is characterized in that, with described second mask for mask comprises the step that described dielectric layer carries out the first etching: adopt non-fluorine-based etching agent to carry out the first etching to described dielectric layer.
9. form method as claimed in claim 8, it is characterized in that, adopt non-fluorine-based etching agent to comprise the step that described dielectric layer carries out the first etching: adopt the etching gas comprising hydrogen to carry out dry quarter, to form through hole to described dielectric layer.
10. the formation method as described in claim 1 or 8, is characterized in that, described second mask is photoresist.
11. form method as claimed in claim 6, it is characterized in that, after the described groove of formation, before described cleaning step, also comprise reparation step, form protective layer at the groove formed and the sidewall of through hole and bottom.
12. form method as claimed in claim 11, it is characterized in that, described reparation step comprises that to pass into flow be the gas that 100 ~ 1000sccm contains He or Ar, and the duration is 10s ~ 30min.
13. form method as claimed in claim 1, it is characterized in that, the material of described dielectric layer is low-K dielectric material or super low-K dielectric material.
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| CN117976685B (en) * | 2024-03-29 | 2024-06-14 | 合肥晶合集成电路股份有限公司 | Image sensor and preparation method thereof |
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