CN104900579B - The forming method of semiconductor devices - Google Patents

The forming method of semiconductor devices Download PDF

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Publication number
CN104900579B
CN104900579B CN201410077118.4A CN201410077118A CN104900579B CN 104900579 B CN104900579 B CN 104900579B CN 201410077118 A CN201410077118 A CN 201410077118A CN 104900579 B CN104900579 B CN 104900579B
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hard mask
mask layer
layer
semiconductor devices
forming method
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CN104900579A (en
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周鸣
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

Abstract

The invention provides a kind of forming method of semiconductor devices, including：On the dielectric layer of Semiconductor substrate, formed in the first hard mask layer using the silica of carbon dope as material, the silica formation process of carbon dope, oxygen plasma gas will not be formed, thus avoid oxygen plasma gas from causing dielectric layer to damage；The second hard mask layer using the silica of carbon dope and fluorine as material is formed on the first mask layer, hard mask layer is used as using the first hard mask layer and the second hard mask layer to be overall, and using the hard mask pattern in hard mask layer as mask etching dielectric layer, perforate is formed in dielectric layer；Perforate is cleaned using cleaning solution afterwards.Wherein, the speed for cleaning the second hard mask layer is more than the speed of the first hard mask layer of cleaning, so as to effectively expand the opening of the perforate in hard mask layer and dielectric layer, during metal material is filled subsequently into the perforate of dielectric layer, it is easy to metal material to enter in the perforate of dielectric layer, the structural form of the metal in optimization perforate.

Description

The forming method of semiconductor devices
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of forming method of semiconductor devices.
Background technology
With the development of ic manufacturing technology, the characteristic size of integrated circuit also constantly reduces, the collection of integrated circuit Cheng Du is continuously increased.Such as super large integrated circuit（Very Large Scale Integration, VLSI）It is required that in several millimeters of faces It is integrated up to ten thousand to million components on long-pending silicon chip.
In order to improve the integrated level of integrated circuit, existing semiconductor devices includes multilayer dielectricity Rotating fields, semiconductor device Each component of part is distributed in each layer dielectric layer, and the component in each dielectric layer is connected by the conductive structure in each dielectric layer Connect.But the parasitic capacitance and dead resistance between conductive structure can caused RC delays（Resistive Capacitive Delay, abbreviation RC Delay）.In order to reduce the RC delays effect, prior art uses ultralow K the dielectric layer more Medium（Abbreviation ULK）Material is electrically isolated, and the ULK materials can reduce the parasitic capacitance between conductive structure, so as to drop Low resistance capacitance delays.
Be generally loose structure based on existing ULK materials, in order to avoid formed hard mask layer technique in by oxygen etc. Ionized gas is damaged, and OMCTS is formed on ULK layers using the method for spin coating in existing process（Prestox epoxy silane）Layer, and TEOS layers are formed according to this on OMCTS layers with TiN layer to be used as hard mask layer.
Fig. 1 is the cross-sectional view of the existing conductive structure formed in low K dielectric layer, and forming process includes：
ULK material layers 11 are first formed over the semiconductor substrate 10, form OMCTS layers 12 in ULK material layers 11 afterwards, TEOS layers 13 and TiN layer 14 are sequentially formed on OMCTS layers 12；Afterwards photoresist layer is coated in TiN layer 14（Do not shown in figure）, Exposed developing process is formed after pattern in photoresist layer, by mask etching TiN layer 14 of photoetching agent pattern, the and of TEOS layers 13 OMCTS layers 12 are to form hard mask pattern, and using hard mask pattern as mask etching ULK material layers 11, in ULK material layers 11 Through hole 16 is formed, fills metal material in through hole 16 afterwards to form metal plug.
Wherein, the material of photoresist layer is generally organic matter, and it is close with OMCTS layers of etching ratio, and the TiN layer is to completely cut off OMCTS layers of direct and photoresist layer, it is to avoid follow-up photoresist layer, which is removed, causes OMCTS layers of loss in technique, and described TEOS layers TiN layer and OMCTS layers of bond strength can be improved.
However, with reference to shown in Fig. 2, after existing above-mentioned technique, forming through hole in described ULK layers, and fill gold Category material formation metal plug upper end is narrower, and form is poor, and then can influence the performance of metal plug.
Therefore, the problem of structural form for how improving metal plug is those skilled in the art's urgent need to resolve.
The content of the invention
The problem of present invention is solved is to provide a kind of forming method of semiconductor devices, is avoiding what dielectric layer sustained damage Meanwhile, the structural form of the metal plug formed in the follow-up perforate formed in dielectric layer of optimization.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：
Semiconductor substrate is provided；
Dielectric layer is formed on the semiconductor substrate；
The first hard mask layer is formed on the dielectric layer, the material of first hard mask layer is the silica of carbon dope；
The second hard mask layer is formed on first hard mask layer, the material of second hard mask layer is carbon dope and fluorine Silica；
Second hard mask layer and the first hard mask layer are etched, hard mask pattern is formed；
The dielectric layer is etched along the hard mask pattern, perforate is formed in the dielectric layer；
The perforate is cleaned using cleaning solution, the speed that the cleaning solution cleans second hard mask layer is more than clearly Wash the speed of the first hard mask layer.
Alternatively, the cleaning solution is hydrofluoric acid solution.
Alternatively, in the hydrofluoric acid solution, the volume ratio of water and hydrofluoric acid is 300:1~1000:1.
Alternatively, the cleaning solution cleans the speed and the speed of the second hard mask layer of cleaning of first hard mask layer Ratio be 1:2 to 1:3.
Alternatively, the thickness of first hard mask layer is
Alternatively, the thickness of second hard mask layer is
Alternatively, the formation process of first hard mask layer is PECVD, and the technological parameter of the PECVD includes：
Reacting gas includes SiH4And CO2, the flow of the SiH4 is 100~3000sccm, the CO2Flow be 100 ~2000sccm, power is 100~2000W, and air pressure is 1~10torr, and temperature is 100~400 DEG C.
Alternatively, the formation process of second hard mask layer is PECVD, and the technological parameter of the PECVD includes：
Reacting gas includes SiH4、CO2With Fluorine source gas, the flow of the SiH4 is 100~3000sccm, the CO2's Flow is 100~2000sccm, and the flow of Fluorine source gas is 100~2000sccm, and power is 100~2000W, air pressure is 1~ 10torr, temperature is 100~400 DEG C.
Alternatively, the Fluorine source gas is：CF4, NF3Or SiF4。
Alternatively, the material of the dielectric layer is ultralow K dielectric materials.
Alternatively, in addition to：
The 3rd hard mask layer is formed on second hard mask layer, the material of the 3rd hard mask layer is nitride metal Thing；
Etching the technique of second hard mask layer and the first hard mask layer includes：
Photoresist layer is formed on the 3rd hard mask layer；
Pattern after the photoresist layer, using the photoresist layer described in mask etching the 3rd hard mask layer, second hard Mask layer and the first hard mask layer.
Alternatively, the material of the 3rd hard mask layer is TiN layer.
Alternatively, in addition into the perforate of the dielectric layer metal material is filled, to form metal plug.
Compared with prior art, technical scheme has advantages below：
On the dielectric layer of Semiconductor substrate, the first hard mask layer using the silica of carbon dope as material is formed, wherein mixing In the silica formation process of carbon, oxygen plasma gas will not be formed, thus avoids the use based on oxygen plasma gas Dielectric layer is caused to damage；Afterwards, the second hard mask layer using the silica of carbon dope and fluorine as material is formed on the first mask layer, Using the first hard mask layer and the second hard mask layer to be overall as hard mask layer, then using the hard mask pattern in hard mask layer to cover Mould etch dielectric layer, is formed after perforate in dielectric layer, perforate is cleaned using cleaning solution, to remove etch by-products.Wherein, During cleaning solution cleaning perforate, the second hard mask speed of cleaning is more than the speed of the first hard mask layer of cleaning, that is, is opening During hole, the speed that the cleaning of the second hard mask layer is removed is more than the first hard mask layer and cleans the speed removed, thus in cleaning After technique, it can effectively expand the upper end open size of the second hard mask layer, the first hard mask layer and the perforate in dielectric layer, because And, filling metal material subsequently into the perforate of dielectric layer to be formed during metal plug, it is easy to metal material to enter Jie In the perforate of electric layer, the structural form of the metal level of the formation in optimization perforate；
In addition, the material of the first hard mask layer is the silica of carbon dope, the material of the second hard mask layer is carbon dope and fluorine Silica, above-mentioned technical proposal can effectively improve the bonding strength between the first hard mask layer and the second hard mask.
Further, first hard mask layer uses SiH4And CO2For reacting gas, the second hard mask layer is with SiH4And CO2 It is reacting gas with Fluorine source gas, above-mentioned technical proposal can effectively simplify the formation process of the second hard mask layer, so as to reduce system Standby cost.
Further, the perforate is cleaned as cleaning agent using HF solution, HF solution is for the first hard mask layer and the The cleaning rate ratio of two hard mask layers is 1:2~1:3 so that using cleaning solution cleaning perforate mouthful so that the dielectric layer, Opening flare in first hard mask layer and the second hard mask layer, expands the upper end open size of the perforate.
Brief description of the drawings
The structural representation of perforate is formed in a kind of existing super low k dielectric layer of Fig. 1；
The electron microscope of the existing metal plugs formed in ultralow K dielectric materials of Fig. 2；
Fig. 3 is the structural representation of the existing defect formed in ultralow K dielectric materials after perforate；
Fig. 4 to Fig. 7 is one embodiment schematic diagram of the forming method of semiconductor devices of the present invention；
Fig. 8 is to be formed using one embodiment of the forming method of semiconductor devices of the present invention in super low k dielectric layer The electron microscope of metal plug.
Embodiment
As stated in the Background Art, the structural form for the conductive plunger that prior art is formed is poor, so as to influence metal to insert The performance of plug.Its reason is analyzed, with reference to shown in Fig. 3：
Prior art is formed after perforate 15 in ULK layers 12, it is necessary to carry out wet-cleaning using the hydrofluoric acid solution of dilution Technique, to remove in perforate 15, the etching by-product formed in etch hard mask layer and ULK layers is biological.But it is clear in wet method Wash in technique, hydrofluoric acid solution can corrode the ULK layers 11 of a part, OMCTS layers 12, TEOS layers 13, and TiN layer 14.But phase Than with other materials, the etch-rate of TEOS layers 14 is slower, thus on the side wall in perforate 15, positioned at the part meeting of TEOS layers 14 Form projection 16.Based on raised 16 reason, the bore above perforate in ULK layers 11 is smaller, thus in ULK layers 11 The upper end of the metal plug of interior formation is thinner, and structural form is poor；In addition, when filling metal material subsequently into perforate 15, The density for the metal material that raised 16 influence is formed below.For these reasons, the metal ultimately formed can be reduced The performance of connector.
In order to solve the above problems, the invention provides a kind of forming method of semiconductor devices, ULK layers are being prevented effectively from It is impaired effectively to optimize the structural form of the ULK layers of interior perforate formed simultaneously, and then optimize the follow-up shape in ULK layers of perforate Into metal plug structural form.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
Fig. 4 to Fig. 7 is the cross-sectional view of the forming process of the semiconductor devices of the embodiment of the present invention.
Referring initially to shown in Fig. 4 there is provided Semiconductor substrate 20, in Semiconductor substrate 20 formed dielectric layer 21, in dielectric layer The first hard mask layer 22 of upper formation, and form on the first hard mask layer 22 second hard mask layer 23, first hard mask layer 22 and second hard mask layer 22 be used as hard mask layer to be overall.
In the present embodiment, the Semiconductor substrate 20 includes：Semiconductor base or semiconductor base and being formed at partly is led In body substrate or semiconductor substrate surface semiconductor device device, the semiconductor devices includes cmos device, the CMOS devices Part includes transistor, memory, capacitor or electric part, and for making the electric interconnection structure of the semiconductor devices electrical connection, with And the structure such as the insulating barrier for being electrically isolated the semiconductor devices and electric interconnection structure.
The semiconductor base is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator（SOI）Substrate, insulator Upper germanium（GOI）Substrate, glass substrate or III-V substrate.
In the present embodiment, the material of the dielectric layer 21 is ultralow K dielectric materials, specifically, the material of the dielectric layer 21 The K values of material are less than or equal to 2.6.It is follow-up to be formed in the dielectric layer 21 after conductive structure, using the dielectric layer 21 of ultra low-K material The parasitic capacitance between adjacent conductive structures can be effectively reduced, so as to reduce the resistance occurred when signal is transmitted in conductive structure Capacitance delays（RC Delay）Effect.
In the present embodiment, the dielectric layer 26 is generally loose structure, the silica of such as loose structure, its formation process bag Include：Non-porous silicon oxide layer is formed on the surface of Semiconductor substrate 20 using chemical vapor deposition method；Using porous handling process （Such as UV treatment technique）The non-porous silicon oxide layer is handled, the dielectric of porous ultralow K dielectric materials is formed Layer 21.
In other embodiments, the material of the dielectric layer 21 can also be other ultralow K dielectric materials, such as boron nitride （BN）, it does not limit protection scope of the present invention.
It should be noted that before the dielectric layer 21 is formed, can also form etching resistance on the surface of Semiconductor substrate 20 Barrier（Do not shown in figure）, the dielectric layer 21 is formed at the etch stopper layer surface, the material of the etching barrier layer with The material of dielectric layer 21 is different.The material on the barrier layer of the present embodiment is carbonitride of silicium, and the etching barrier layer is used for follow-up The stop position of etching technics is defined during etch dielectric layer 21, and protects the surface of Semiconductor substrate 20 from damage.
The material of first hard mask layer 22 is the silica of carbon dope, and thickness is
In the present embodiment, the material of first hard mask layer 22 is SiOC, and formation process is PECVD, detailed process bag Include：
It is 100~2000W to control the power in reaction chamber, and temperature is 100~400 DEG C, and SiH is passed through into reaction chamber4With CO2It is used as reacting gas.Wherein, the flow of the SiH4 is 100~3000sccm, the CO2Flow for 100~ 2000sccm, the air pressure of reacting gas is 1~10torr.
In the present embodiment, form the technique of first hard mask layer 22 to use SiH4And CO2For reacting gas Pecvd process, does not produce oxygenous plasma, thus can be prevented effectively from and produced based on oxygen gas plasma and caused described The impaired defect of dielectric layer 21.
In the present embodiment, the material of second hard mask layer 23 is carbon dope and the silica of fluorine, and thickness isThe formation process of second hard mask layer 23 is PECVD, is specifically included：
It is 100~2000W to control the power in reaction chamber, and temperature is 100~400 DEG C, and SiH is passed through into reaction chamber4With CO2, and Fluorine source gas is as reacting gas, so as to form the silicon oxide layer of carbon dope and fluorine（SiOCF layers）.
In the present embodiment, the SiH4Flow be 100~3000sccm, CO2Flow be 100~2000sccm, Fluorine source The flow of gas is 100~2000sccm, and the air pressure of each reacting gas is 1~10torr.
In the present embodiment, the Fluorine source gas is CF4, NF3Or SiF4。
In the present embodiment, the material of the first hard mask layer 22 is the silica of carbon dope, the material of second hard mask layer 23 For carbon dope and the silica of fluorine, there is preferable bonding strength between the hard mask layer 23 of the first hard mask layer 22 and second, because And the performance with the first hard mask layer 22 and the second hard mask layer 23 for overall hard mask layer can be effectively improved, after effectively improving Continue the hard mask pattern accuracy formed in hard mask layer.In addition, first hard mask layer uses SiH4And CO2For reaction Gas, the second hard mask layer is with SiH4And CO2It is reacting gas with Fluorine source gas, above-mentioned technical proposal can use in-situ deposition work Skill forms the hard mask layer 23 of the first hard mask layer 22 and second, to simplify the formation process of the second hard mask layer 23, so that Reduction prepares cost.
With continued reference to shown in Fig. 4, in the present embodiment, after second hard mask layer 23 is formed, covered firmly described second The 3rd hard mask layer 24 using metal nitride as material is formed on mould 23, afterwards the accompanying drawing photoresist on the 3rd hard mask layer 24 Layer 25, and through exposure and development after technique, photoetching agent pattern is formed in the photoresist layer 25.
In the present embodiment, the 3rd hard mask layer 24 and the second hard mask layer 23 have preferable bonding strength, described second Hard mask layer 23 can effectively improve the bonding strength of the first hard mask layer 22, the second hard mask layer 23 and the 3rd hard mask layer 24, And then it is overall that can effectively improve subsequent etching with the first hard mask layer 22, the second hard mask layer 23 and the 3rd hard mask layer 24 After hard mask layer, the accuracy of the hard mask pattern of formation.
Certainly, if photoresist layer is directly formed on second hard mask layer can also realize the purpose of the present invention, it is simultaneously Do not influence protection scope of the present invention.
In the present embodiment, the material of the 3rd hard mask layer 24 is titanium nitride（TiN）.
It is mask with the photoresist layer 35 referring next to shown in Fig. 5, is sequentially etched the 3rd hard mask layer 24, Two hard mask layers 23 and the first hard mask layer 22, form hard mask pattern, wherein including perforate 26 in the hard mask pattern.
In the present embodiment, the technique for etching each hard mask layer is dry etch process, and it is the mature technology of this area, This is repeated no more.
With reference to shown in Fig. 6, afterwards, with hard mask layer（3rd hard mask layer 24, the second hard mask layer 23 and the first hard mask Layer 22 is overall）Interior hard mask pattern is mask, the dielectric layer 21 is etched along perforate 26, so as to be covered firmly the described 3rd Perforate 27 is formed in mold layer 24, the second hard mask layer 23 and the first hard mask layer 22 and the dielectric layer 21.
Afterwards, the photoresist layer 25 is removed.The technique for removing the photoresist layer 25 is wet processing, and the technique is this Maturation process in field, will not be repeated here.
In the present embodiment, after the photoresist layer 25 is removed, before conductive structure is formed, institute is cleaned using cleaning solution State the 3rd hard mask layer 24, the perforate 27 in the second hard mask layer 23 and the first hard mask layer 22 and dielectric layer 21.
During etching each layer hard mask layer, dielectric layer 21 and removing photoresist layer 25, accessory substance 30, institute can be produced State accessory substance 30 and be easily attached to the side wall and lower surface of the perforate 27, so as to cause to be subsequently formed in the perforate of dielectric layer 21 The performance of interior conductive structure is bad.The side wall and lower surface of the perforate 27 are cleaned with cleaning solution, be can remove Accessory substance 30 in perforate 27.
In the present embodiment, the speed that the cleaning solution cleans second hard mask layer is covered firmly more than cleaning described first The speed of mold layer.
Alternatively, the cleaning solution is hydrofluoric acid solution.Still optionally further, in the hydrofluoric acid solution, water and The volume ratio of hydrofluoric acid is 300:1~1000:1.The cleaning solution cleans the speed of first hard mask layer and cleaning the The ratio of the speed of two hard mask layers is 1:2 to 1:3.
With reference to shown in Fig. 7, in the present embodiment, the material of first mask layer 22 is the silica of carbon dope, and dielectric layer 21 material is porous low-K dielectric material, and cleaning solution is cleaned during the perforate 27, and cleaning solution cleans the first mask layer 22 speed is close with the speed for cleaning dielectric layer 21, therefore after by wet-cleaning, described first in the perforate 27 The side wall of mask layer 22 can keep flushing with the sidewall surfaces of dielectric layer 21；And the material of second hard mask layer 23 is carbon dope With the silica of fluorine, the material of the 3rd hard mask layer 24 is TiN.In cleaning process, the 3rd hard mask layer 24 and second The speed that the cleaning of hard mask layer 23 is removed is greater than the speed that the cleaning of first hard mask layer 22 is removed, the 3rd hard mask The cleaning removal rate of layer is greater than the cleaning removal rate of second hard mask layer 23.For this perforate is cleaned in cleaning solution After 27, in the 3rd hard mask layer 24, the second hard mask layer 23, the first hard mask layer 22 and dielectric layer 21 in cleaning process Cleaning rate successively decrease according to this so that perforate 28 is in the larger trumpet type of upper end open, and the side wall of perforate 28 have it is good Flatness.
In the present embodiment after wet clean process, the filling metal material in the perforate 28, in dielectric layer 21 Interior formation metal plug.
In the present embodiment, the metal material is copper.Its formation process includes, first using PVD（Physical vapour deposition (PVD)）Work Skill forms copper seed layer on the surface of the 3rd hard mask layer 24, and the side wall of perforate 28 and bottom, is electroplated afterwards using copper Method forms the metal level of the full perforate 28 of filling on the basis of the copper seed layer.
In the present embodiment, it is the larger flared structure of upper end open based on the perforate 28, in PVD, is easy to Copper atom enters in the perforate 28, and the copper seed layer being had good uniformity in the bottom of perforate 28 and the formation of side wall, so as to Effectively improve the density of the final metal level formed in the perforate 28.
In the present embodiment, if the thickness of second hard mask layer 23 is too small, the opening of the top of the first hard mask layer 22 DeGrain that is not big enough, being easy to copper atom to enter in the perforate 28；If thickness is thicker, the top of the first hard mask layer 22 Opening is enough big, but causes the waste of the second hardmask layer.
In the present embodiment, the thickness of second hard mask layer 23 is
Fig. 8 is uses the present embodiment, the electron microscope of the metal plug formed in the dielectric layer 21.Contrast and Fig. 2 institutes The electron microscope for the metal plug that the prior art shown is formed in ULK layers, using the metal plug shown in the present embodiment Fig. 8 Structural form is substantially better than the structural form of the metal plug shown in Fig. 2.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims (13)

1. a kind of forming method of semiconductor devices, it is characterised in that：Including：
Semiconductor substrate is provided；
Dielectric layer is formed on the semiconductor substrate；
The first hard mask layer is formed on the dielectric layer, the material of first hard mask layer is the silica of carbon dope；
The second hard mask layer is formed on first hard mask layer, the material of second hard mask layer is carbon dope and the oxygen of fluorine SiClx；
Second hard mask layer and the first hard mask layer are etched, hard mask pattern is formed；
The dielectric layer is etched along the hard mask pattern, perforate is formed in the dielectric layer；
The perforate is cleaned using cleaning solution, the speed that the cleaning solution cleans second hard mask layer is more than cleaning the The speed of one hard mask layer.
2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the cleaning solution is that hydrofluoric acid is molten Liquid.
3. the forming method of semiconductor devices as claimed in claim 2, it is characterised in that in the hydrofluoric acid solution, water Volume ratio with hydrofluoric acid is 300:1~1000:1.
4. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the cleaning solution cleaning described the The ratio of the speed of one hard mask layer and the speed of the second hard mask layer of cleaning is 1:2 to 1:3.
5. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the thickness of first hard mask layer For
6. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the thickness of second hard mask layer For
7. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the formation of first hard mask layer Technique is PECVD, and the technological parameter of the PECVD includes：
Reacting gas includes SiH4And CO2, the SiH4Flow be 100~3000sccm, the CO2Flow for 100~ 2000sccm, power is 100~2000W, and air pressure is 1~10torr, and temperature is 100~400 DEG C.
8. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the formation of second hard mask layer Technique is PECVD, and the technological parameter of the PECVD includes：
Reacting gas includes SiH4、CO2With Fluorine source gas, the SiH4Flow be 100~3000sccm, the CO2Flow For 100~2000sccm, the flow of Fluorine source gas is 100~2000sccm, and power is 100~2000W, air pressure is 1~ 10torr, temperature is 100~400 DEG C.
9. the forming method of semiconductor devices as claimed in claim 8, it is characterised in that the Fluorine source gas is：CF4, NF3 Or SiF4。
10. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the material of the dielectric layer is super Low-K dielectric material.
11. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that also include：
The 3rd hard mask layer is formed on second hard mask layer, the material of the 3rd hard mask layer is metal nitride；
Etching the technique of second hard mask layer and the first hard mask layer includes：
Photoresist layer is formed on the 3rd hard mask layer；
Pattern after the photoresist layer, using the photoresist layer described in mask etching the 3rd hard mask layer, the second hard mask Layer and the first hard mask layer.
12. the forming method of semiconductor devices as claimed in claim 11, it is characterised in that the material of the 3rd hard mask layer Expect for TiN layer.
13. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that also including to the dielectric layer Filling metal material in perforate, to form metal plug.
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