CN105336678B - The forming method of interconnection structure - Google Patents
The forming method of interconnection structure Download PDFInfo
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- CN105336678B CN105336678B CN201410381338.6A CN201410381338A CN105336678B CN 105336678 B CN105336678 B CN 105336678B CN 201410381338 A CN201410381338 A CN 201410381338A CN 105336678 B CN105336678 B CN 105336678B
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Abstract
The present invention provides a kind of forming methods of interconnection structure.After forming dielectric layer on a semiconductor substrate, silicon oxide mask layer is formed on the dielectric layer, to form hard mask.The forming step of the silicon oxide mask layer includes：Tetraethyl orthosilicate layer is first formed on dielectric layer, later, oxygen plasma treatment is carried out to the tetraethyl orthosilicate layer, so that oxygen plasma is reacted with the tetraethyl orthosilicate layer, to form silicon oxide mask layer.Carbon content in the silicon oxide layer being formed by the above-mentioned technique is substantially reduced, to after subsequent dielectric layers form through-hole, during wet-cleaning through-hole, alleviate the defect for causing the wear rate of silicon oxide mask layer to be significantly less than dielectric layer based on carbon atom, it is effectively improved the flatness of the through-hole side wall entirety in the opening being formed in the hard mask and dielectric layer, the filling capacity for improving the conductive material subsequently filled into the through-hole in turn, to improve the performance of the conductive plunger formed.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of forming method of interconnection structure.
Background technology
As semiconductor technology develops, the integrated level of semiconductor devices is continuously increased, feature sizes of semiconductor devices
(Critical Dimension, CD) is smaller and smaller.
And being gradually reduced with feature sizes of semiconductor devices, RC retardation ratio (RC delay) problem of interconnection structure is half-and-half
The influence of conductor device is increasing.The K values for reducing interconnection structure dielectric layer material are effective sides for reducing RC retardation ratio effect
Method.In recent years, in the back segment preparation process of semiconductor devices (Back End of The Line, BEOL), low-K dielectric constant
(Low K, LK) material (K ＜ 3) and ultralow K dielectric constants (Ultra Low K, ULK) material have been increasingly becoming the master of dielectric layer
Material is flowed, and with semiconductor device development demand, the K values of used dielectric layer material constantly reduce.
Fig. 1 and Fig. 2 is the formation process schematic diagram of existing interconnection structure, and the formation process of interconnection structure includes：
Refering to what is shown in Fig. 1, after forming dielectric layer 11 on the substrate 10, low-K dielectric is formed according to this on the dielectric layer 11
Mask layer 12, with tetraethyl orthosilicate (Tetraethyl 0rthosilicate, TEOS) be reaction gas (TEOS-
Based the silicon oxide layer 13 and metallic mask layer 14 (such as using titanium nitride as material)) formed is covered etching the low-K dielectric
After mold layer 12, silicon oxide layer 13 and metallic mask layer 14 form hard mask 15, given an account of by mask etching with the hard mask 15
Matter layer 11 forms through-hole 16.
Shown in Fig. 2, conductive material layer 17 is formed in the hard mask 15, the conductive material layer 17 is filled
The full through-hole 16, to form conductive plunger in dielectric layer 11.
However, being found in actual mechanical process, the performance by the conductive plunger of prior art formation is poor, Wu Faman
The demand for development of sufficient semiconductor technology, how to improve conductive plunger performance thus is asking for those skilled in the art's urgent need to resolve
Topic.
Invention content
Problems solved by the invention is to provide a kind of forming method of interconnection structure, and leading in dielectric layer is formed in improve
The performance of electric plug.
To solve the above problems, the forming method of interconnection structure provided by the invention includes：
Substrate is provided；
Dielectric layer is formed on the substrate；
Tetraethyl orthosilicate layer is formed on the dielectric layer；
Oxygen plasma treatment, the oxygen plasma and the tetrem base are carried out to the tetraethyl orthosilicate layer
Silicate layer reacts to form silicon oxide mask layer；
Metallic mask layer is formed on the silicon oxide mask layer；
The metallic mask layer and silicon oxide mask layer are etched, hard mask is formed；
Using the hard mask as dielectric layer described in mask etching, through-hole is formed in the dielectric layer；
Conductive material is filled in the through-hole, to form conductive plunger.
Optionally, the amount for oxygen used by oxygen plasma treatment being carried out to the tetraethyl orthosilicate layer is more than shape
The amount of the tetraethyl orthosilicate used when at tetraethyl orthosilicate layer.
Optionally, the oxygen used in oxygen plasma treatment and tetrem used when formation tetraethyl orthosilicate layer are carried out
The amount ratio of the substance of base silicate is 1:5~1:50.
Optionally, the method for forming tetraethyl orthosilicate layer is chemical vapour deposition technique.
Optionally, the flow of tetraethyl orthosilicate is less than or equal in the step of forming tetraethyl orthosilicate layer
200mg/min。
Optionally, the synthesis speed of tetraethyl orthosilicate layer is in the step of forming tetraethyl orthosilicate layer
Optionally, the thickness of the tetraethyl orthosilicate layer is
Optionally, include to the step of tetraethyl orthosilicate layer progress oxygen plasma treatment：Being passed through flow is
The oxygen of 10000~20000sccm.
Optionally, the step of formation tetraethyl orthosilicate layer includes：Air pressure be 0.1~10torr, power be 100~
The flow of 5000W, tetraethyl orthosilicate are 10~150mg/min；
Include to the step of tetraethyl orthosilicate layer progress oxygen plasma treatment：Air pressure is 0.1~10torr,
Power is 100~5000W, and the flow of oxygen is 15000~20000sccm.
Optionally, before forming the metallic mask layer, the forming method of the interconnection structure includes：
It is repeatedly formed the tetraethyl orthosilicate layer and oxygen plasma is carried out to the tetraethyl orthosilicate layer
The step of processing, to form silicon oxide mask layer.
Optionally, step 1~6 time for forming tetraethyl orthosilicate layer and carrying out oxygen plasma treatment are executed, with
Form silicon oxide mask layer.
Optionally, oxygen plasma treatment is carried out to the tetraethyl orthosilicate layer, to form silicon oxide mask layer
Step includes：The content for forming carbon atom is less than or equal to 1.0 × 1018The silicon oxide mask layer of a atoms per cubic centimeter.
Optionally, after forming through-hole in the dielectric layer, before filling conductive material in the through-hole, the mutual connection
The forming method of structure further includes carrying out wet clean step to through-hole.
Optionally, before forming silicon oxide mask layer on the dielectric layer, the forming method of the interconnection structure further includes
Low-K dielectric mask layer is formed on the dielectric layer, the K values of the low-K dielectric mask layer are less than or equal to 3；
The step of etching the metallic mask layer and silicon oxide mask layer, forming hard mask include：
The metallic mask layer, silicon oxide mask layer and low-K dielectric mask layer are etched, to form hard mask.
Compared with prior art, technical scheme of the present invention has the following advantages：
Include first being formed on dielectric layer in the step of forming silicon oxide mask layer on dielectric layer after forming dielectric layer
Tetraethyl orthosilicate layer carries out oxygen plasma treatment so that oxygen plasma to the tetraethyl orthosilicate layer later
It is reacted with tetraethyl orthosilicate layer, forms silicon oxide layer.It is formed based on tetraethyl orthosilicate in compared with the prior art
Silicon oxide layer, the present invention are initially formed tetraethyl orthosilicate layer, later with tetraethyl orthosilicate described in oxygen plasma treatment
Layer so that tetraethyl orthosilicate forms silica with oxygen plasma precursor reactant, while oxygen plasma is more easy to and tetrem base
Carbon atom in silicate layer reacts to form carbon dioxide (or carbon monoxide), to shift in original tetraethyl orthosilicate layer
Carbon atom, effectively reduce and be formed by carbon content in silica, to subsequent etching silicon oxide layer, dielectric layer and
After forming through-hole in dielectric layer, during wet-cleaning through-hole, being effectively relieved makes silicon oxide mask layer because of carbon atom
Wear rate is significantly less than the phenomenon that dielectric layer, improves the wear rate of silicon oxide mask layer, makes silicon oxide mask layer and Jie
The wear rate of matter layer is close, and then can reduce the bump defects being susceptible in dielectric layer through-hole side wall so that described hard
The opening of mask and the through-hole side wall in dielectric layer integrally have preferable flatness, can be effectively improved subsequently to described logical
The filling capacity for the conductive material filled in hole, to improve the performance for the conductive plunger being subsequently formed.
Description of the drawings
Fig. 1 and Fig. 2 is a kind of structural schematic diagram of conductive plunger forming method of the prior art；
Fig. 3 is semiconductor devices schematic diagram of the existing conductive plunger forming method after etch media layer forms through-hole；
Fig. 4~Figure 15 is the structural schematic diagram of one embodiment of forming method of interconnection structure of the present invention；
Figure 16 and 17 is the structural schematic diagram of another embodiment of forming method of interconnection structure of the present invention.
Specific implementation mode
As stated in the background art, in the last part technology of existing semiconductor devices, the conductive plunger that is formed in dielectric layer
Performance is poor.Its reason is analyzed, refering to what is shown in Fig. 3, etch media layer to be to form in the technique of through-hole, the hard mask on dielectric layer
15 silicon oxide layers 13 for including low-K dielectric mask layer 12, being formed as reaction gas (TEOS-based) using tetraethyl orthosilicate
With metallic mask layer 14.Wherein, it during etch media layer forms through-hole, and follow-up cleaning through-hole, is easy described
Protrusion 18 is formed on the silicon oxide layer 13 above 16 inner wall of through-hole in dielectric layer 11, and conductive material is subsequently being filled into through-hole
When, described raised 18 the defects of influencing the filling effect of conductive material, forming gap in the conductive material in through-hole 16, in turn
Influence the performance for the conductive plunger being subsequently formed.
Further analysis etch media layer forms the reason of protrusion：The existing silica formed using tetraethyl orthosilicate
In the difficulty that all can improve the hardness of silica doped with the carbon atom of high level, carbon atom and be etched, therefore
During etch media layer and progress wet-cleaning through-hole, the carbon atom in silicon oxide layer 13 can reduce silicon oxide layer 13
Wear rate so that the consumption of silicon oxide layer 13 is significantly less than the consumption of the metallic mask layer 14 of 13 top of oxide layer, also
Less than the consumption of the low-K dielectric mask layer 12 and dielectric layer 11 of 13 lower section of silicon oxide layer, to because of 13 consumption of silicon oxide layer
It is less and formed at 13 position of silicon oxide layer protrusion 18.
For this purpose, the present invention provides a kind of forming methods of interconnection structure, including：
After forming dielectric layer on a semiconductor substrate, silicon oxide layer is formed on the dielectric layer, the silicon oxide layer
Forming step includes：Tetraethyl orthosilicate layer is first formed on dielectric layer, and later, the tetraethyl orthosilicate layer is carried out
Oxygen plasma treatment makes oxygen plasma be reacted with the tetraethyl orthosilicate layer, to form silicon oxide mask layer；It
Afterwards, metallic mask layer is formed on the silicon oxide layer, and etches the metallic mask layer and silicon oxide layer formation hard mask, and
Using the hard mask as mask etching dielectric layer, after forming through-hole in dielectric layer, conductive material is filled into through-hole, with shape
At conductive plunger.
The silicon oxide layer formed based on tetraethyl orthosilicate in compared with the prior art, the present invention are initially formed tetrem base
Silicate layer, later with tetraethyl orthosilicate layer described in oxygen plasma treatment so that tetraethyl orthosilicate layer and oxygen etc.
Ion precursor reactant forms silica, while oxygen plasma is more easy to react to form two with the carbon atom in tetraethyl orthosilicate layer
Carbonoxide (or carbon monoxide) shifts the carbon atom in original tetraethyl orthosilicate layer, and oxygen is formed by effectively reduce
Carbon content in SiClx, and then during subsequent etching, silicon oxide layer and dielectric layer, and in dielectric layer after formation through-hole
Wet-cleaning through-hole during, alleviation so that the wear rate of silicon oxide mask layer is significantly less than dielectric layer because of carbon atom
The phenomenon that, the wear rate of silicon oxide mask layer is improved, keeps the wear rate of silicon oxide mask layer and dielectric layer close, effectively
Improve and be formed in the flatness of the opening in the hard mask and entirety of the through-hole side wall in dielectric layer, so raising subsequently to
The filling capacity for the conductive material filled in the through-hole, to improve the performance of the conductive plunger formed.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Embodiment 1
Fig. 4~Figure 15 is the structural schematic diagram of one embodiment of forming method of interconnection structure of the present invention.
The forming method of interconnection structure provided in this embodiment includes：
Shown in Fig. 4, substrate 20 is provided.
In the present embodiment, the substrate 20 includes：Semiconductor substrate.Or the substrate 20 include semiconductor substrate and
It is formed in semiconductor substrate or the semiconductor components and devices of semiconductor substrate surface.
The semiconductor substrate is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, insulator
Upper germanium (GOI) substrate, glass substrate or other III-V compound substrates, the semiconductor substrate materials do not limit this hair
Bright protection domain.
Form the first insulating layer 21 and second insulating layer 22 according to this in the substrate 20.
In the present embodiment, first insulating layer 21 can be used as diffusion impervious layer, be subsequently formed dielectric layer, and in dielectric layer
After interior formation interconnection structure, the metallic atom that first insulating layer 21 can inhibit in interconnection structure expands into semiconductor base
It dissipates.
The material of first insulating layer 21 is the silica (NDC) of nitrating, and the material of the second insulating layer 22 is low K
Dielectric material, such as the silica (SiOCH) of carbon dope (C) and hydrogen (H).The formation of first insulating layer 21 and second insulating layer 22
Technique is chemical vapor deposition (Chemical Vapor Deposition, CVD).
It is mostly low-K dielectric material based on existing dielectric layer, it is poor with NDC material adhesions, in first insulating layer
It is formed by the second insulating layer 22 of low-K dielectric material on 21, insulating layer 21 and the dielectric layer that is subsequently formed for improving first
Between bond strength.
Later, dielectric layer 23 is formed in the second insulating layer 21.
In the present embodiment, the material of the dielectric layer 23 is low-K dielectric material (K values are less than 3) or ultralow K dielectric materials
(K values are less than 2.6).After subsequently forming interconnection structure in the dielectric layer 23, low-K dielectric material can effectively reduce interconnection structure
Parasitic capacitance, to reduce the RC delays occurred when signal transmits in interconnection structure (RC Delay) effect.
Optionally, in the present embodiment, the dielectric layer 23 uses ultralow K dielectric materials, such as the oxygen of the carbon dope of porous structure
SiClx.
In conjunction with reference to 5~Figure 10 of figure, layer of hard mask material is formed on the dielectric layer 23, etches the hard mask later
Material layer forms hard mask.The layer of hard mask material includes silicon oxide mask layer 26, and is located at the silicon oxide mask layer
Metallic mask layer on 26.
Specifically, as shown in figure 5, in the present embodiment, the layer of hard mask material further includes low-K dielectric mask layer.To
It is formed before silicon oxide mask layer 26 on the dielectric layer 23, the forming method of the interconnection structure further includes：In the medium
Low-K dielectric material layer is formed on layer 23, to form low-K dielectric mask layer 24, the material of the low-K dielectric mask layer is low K
Dielectric material.The binding force of the dielectric layer 23 and silicon oxide mask 26 subsequently can be improved in the low-K dielectric mask layer.
In conjunction with reference to figure 5 and Fig. 6, in the present embodiment, the formation process of the silicon oxide mask layer 26 includes：
The first tetraethyl orthosilicate layer (TEOS layers) 251 is first formed in the low-K dielectric material layer 24, it is right again later
The first tetraethyl orthosilicate layer 251 carries out oxygen plasma treatment so that oxygen plasma and first tetraethyl
Orthosilicic acid salt deposit 251 reacts, to form the first silicon oxide mask layer 261.
Be passed directly into tetraethyl orthosilicate and oxygen compared to existing so that oxygen and tetraethyl orthosilicate reaction with
The method for forming silica is initially formed the first tetraethyl orthosilicate layer, later to the first tetrem base silicon in of the invention
Silicate layer carries out oxygen plasma treatment technique, and tetraethyl orthosilicate forms silica, while oxygen with oxygen plasma precursor reactant
Plasma also reacts to form carbon dioxide (or carbon monoxide) with the carbon atom in tetraethyl orthosilicate layer, transfer original four
Carbon atom in ethyl original silicate layer effectively reduces the carbon content being formed by the first silicon oxide mask layer 261.
In the present embodiment, the formation process of the first tetraethyl orthosilicate layer 251 is chemical vapor deposition
(Chemical Vapor Deposition, CVD).
If the first tetraethyl orthosilicate layer 251 is blocked up, it is unfavorable for follow-up oxygen plasma and the first tetraethyl
Orthosilicic acid salt deposit 251 reacts.In the present embodiment, the thickness of the first tetraethyl orthosilicate layer 251 is
In addition, in 251 forming process of the first tetraethyl orthosilicate layer, if the flow for the tetraethyl orthosilicate being passed through
Excessive, synthesis speed is too fast, is unfavorable for the thickness control of the first tetraethyl orthosilicate layer 251, while can also reduce formation
The uniformity of first tetraethyl orthosilicate layer, 251 each section thickness.The flow of tetraethyl orthosilicate is less than or equal to
200mg/min。
In the present embodiment, the specific technological parameter for forming the first tetraethyl orthosilicate layer 251 includes：Control pressure is
0.1~10torr, power are 100~5000W, and the flow of tetraethyl orthosilicate is 10~150mg/min.
In the present embodiment, the synthesis speed of the first tetraethyl orthosilicate layer 251 is chosen asIt can
Ensure that the first tetraethyl orthosilicate layer 251 has more uniform thickness.
In the present embodiment, oxygen used by oxygen plasma treatment is carried out to the first tetraethyl orthosilicate layer 251
The amount of gas is more than the amount for forming the first tetraethyl orthosilicate used when the first tetraethyl orthosilicate layer 251, to provide
Enough oxygen plasmas are fully reacted with the first tetraethyl orthosilicate layer, to reduce the silicon oxide mask layer being subsequently formed
Interior carbon content.
Optionally, the volume of the oxygen used in oxygen plasma treatment is carried out to the first tetraethyl orthosilicate layer,
It is with the amount ratio (molar ratio) of substance of tetraethyl orthosilicate used in 251 when forming the first tetraethyl orthosilicate layer
5:1~50:1.
In the present embodiment, the concrete technology packet of oxygen plasma treatment is carried out to the first tetraethyl orthosilicate layer
It includes：It is passed through oxygen into plasma producing apparatus, power control is 100~5000W, the flow of oxygen is 10000~
20000sccm is further chosen as 15000~20000sccm.
In the present embodiment, in the first silicon oxide mask layer 26 being formed by the above-mentioned technique, the content of carbon atom be less than or
Equal to 1.0 × 1018A atoms per cubic centimeter.
Optionally, refering to what is shown in Fig. 7, after forming the first silicon oxide mask layer 261, above-mentioned formation the one or four is repeated
The technique of ethyl original silicate layer 251 forms the second tetraethyl orthosilicate layer on the first silicon oxide mask layer 261
252；Later, refering to what is shown in Fig. 8, carrying out oxygen plasma treatment technique again so that the second tetraethyl orthosilicate layer
252 with oxygen plasma precursor reactant to form silicon oxide mask layer 262.
The formation process of the second tetraethyl orthosilicate layer 252, and subsequently use oxygen plasma treatment technique
So that the second tetraethyl orthosilicate layer 252 forms the technique of silica with oxygen plasma precursor reactant, with the above-mentioned 1st
Ethyl original silicate layer 251 is similar to the technique of the first silicon oxide mask layer 261, and details are not described herein.
Refering to what is shown in Fig. 9, after forming the silicon oxide mask layer 262, then at the silicon oxide mask layer
Third tetraethyl orthosilicate layer is formed on 262, and oxygen plasma treatment is carried out to the third tetraethyl orthosilicate layer
Technique forms third silicon oxide mask layer 263.
In the present embodiment, the first silicon oxide mask layer 261, silicon oxide mask layer 262 and third silica are covered
Mold layer 263 forms final silicon oxide mask layer 26.
It, can be by repeating above-mentioned to be initially formed tetrem it is worth noting that, in other embodiment in addition to the present embodiment
Base silicate layer and the step 2 time for carrying out oxygen plasma treatment, or be more than 3 times, to which superposition forms multilayered structure
Silica, until ultimately form thickness silicon oxide mask layer 26 appropriate.Form the tetrem base of thinner thickness every time in this way
Silicate layer so that in subsequent oxygen plasma treatment technique, oxygen can be filled with the tetraethyl orthosilicate layer of thinner thickness
Divide reaction, to improve the performance of finally formed silicon oxide mask layer 26.Optionally, it can perform and form tetraethyl orthosilicate layer
And step 2~6 time of oxygen plasma treatment are carried out, to form the silicon oxide mask layer of 2~6 layers of structure.
In the present embodiment, optionally, the thickness of finally formed silicon oxide mask layer 26 is
Shown in Figure 10, after forming the silicon oxide mask layer 26, the shape on the silicon oxide mask layer 26
At metallic mask layer 27.
In the present embodiment, the metallic mask layer 27 is titanium nitride (TiN) layer, formation process CVD.
In conjunction with reference to shown in figure 11, photoresist mask 25 is formed in the metallic mask layer 27, and with the photoresist
Mask 25 is metallic mask layer 27, silicon oxide mask layer 26 and low-K dielectric material layer 24 described in mask etching, forms hard mask.
The hard mask includes metallic mask layer 271, silicon oxide mask layer 36 and the low-K dielectric material layer 241 after etching.
In the present embodiment, the metal mask material layer 24, silicon oxide mask layer 26 and low-K dielectric material layer 24 are etched
Technique is dry etching.The dry etch process specifically can be with carbon tetrafluoride (CF4) and hydrogen (H2) mixed gas be
Dry etching agent.
Shown in Figure 12, using the hard mask as dielectric layer described in mask etching 23, the first insulating layer 21 and
Two insulating layers 22, form through-hole 28 in the dielectric layer 23, and the through-hole 28 exposes the substrate 20, subsequently led to be formed
Electric plug.
The technique for etching the dielectric layer 23, the first insulating layer 21 and second insulating layer 22 is this field maturation process,
This is repeated no more.
The carbon content in silicon oxide mask layer 26 formed using the present embodiment is smaller, thus effectively increases etching
When dielectric layer 23, the wear rate ratio of silicon oxide mask layer 26 and dielectric layer 23, so as to so that silicon oxide mask layer 26 and Jie
The wear rate of matter layer 23 is suitable, and then the through-hole side wall top for reducing the dielectric layer 23 forms the defect of protrusion.
The through-hole 28 is being formed, and after removing the photoresist mask 28, wet clean step is being carried out, to remove etching
When the dielectric layer 23, remain on the etch by-products in the through-hole 28, is led with reducing subsequently to fill into the through-hole 28
When electric material is to form conductive plunger, the etch by-products being entrained in conductive material reduce etch by-products to conductive plunger
Performance influence.
In the present embodiment, the wet clean step is used as cleaning agent using diluted hydrofluoric acid solution (DHF).Specifically
Ground, the volume ratio of hydrofluoric acid and water is 1 in the diluted hydrofluoric acid solution:300 or so.
Wherein, the diluted hydrofluoric acid solution of above-mentioned concentration can have compared with high definition ensuring the etch by-products except effect
Rate, while also reducing and the dielectric layer 23 is damaged.
As described above, the formation process using silicon oxide mask layer 26 in the present embodiment can effectively reduce in oxide layer 26
Carbon content keeps the silicon oxide mask layer 36 in wet cleaning processes suitable with the wear rate of dielectric layer 23, thus, it can reduce wet
Method cleaning forms raised 18 defects above the side wall of the through-hole 28 of the dielectric layer 23, is filled out in the through-hole 28 to improve
Fill the performance of the conductive plunger formed after conductive material.
With reference to shown in figure 13, after the wet clean step, described cover in the metallic mask layer 271 and firmly
Diffusion impervious layer 29 is formed on the opening of mould and 28 side wall of through-hole of dielectric layer 23 and bottom.
In the present embodiment, the material of the diffusion impervious layer 29 is tantalum nitride (TaN), formation process CVD.
In other embodiments of the invention, the material of the diffusion impervious layer 29 can also be tantalum (Ta) etc., forming method
For physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) etc., the material of the diffusion impervious layer 29 and formation
Method does not limit protection scope of the present invention.
Compared to prior art, in the present embodiment, after wet clean process, in the through-hole 28 in the dielectric layer 23
Without apparent raised 18 defects above wall, thus the stripping for the diffusion impervious layer 29 being covered on 28 inner wall of through-hole can be effectively reduced
Problem is fallen, so as to effectively improve the binding force of the diffusion impervious layer 29 and dielectric layer 23.
Later, the diffusion impervious layer for removing 28 bottom of the through-hole retains the diffusion impervious layer 29 of 28 side wall of the through-hole,
Expose the substrate 20.
With reference to shown in figure 14, conductive material layer 30, in the present embodiment, the conduction are formed on the diffusion impervious layer 29
The material of material layer 30 is metallic copper.The filling of the conductive material layer 30 completely through-hole 28.
With reference to shown in figure 15, using techniques such as chemical mechanical grindings (CMP), the conductive material of 20 top of the substrate is removed
Layer and hard mask, expose 20 surface of the substrate so that conductive material layer surface and 23 table of the dielectric layer in the through-hole 28
Face flushes, and conductive plunger 31 is formed in the dielectric layer 22.
Compared to the silicon oxide layer formed by prior art, in the present embodiment, the carbon in the silicon oxide mask layer 26
Content is substantially reduced, thus in such as etch media layer and in wet cleaning processes, improves silicon oxide mask layer 36
Wear rate keeps the wear rate of silicon oxide mask layer 36 and dielectric layer 23 close, on the side wall so as to reduce through-hole 28
The structures such as protrusion are formed, and then improve the filling capacity that the conductive material layer 30 is filled in the through-hole 28, are effectively subtracted
Few gap formed in the conductive material layer 30, to improve 31 performance of the conductive plunger.
Embodiment 2
Figure 16 and 17 is participated in, the structural schematic diagram of another embodiment of forming method of interconnection structure of the present invention is illustrated.
The forming method of the interconnection structure of the present embodiment and the something in common of Fig. 4 to embodiment illustrated in fig. 15 repeat no more,
Its difference lies in：
In the present embodiment, the silicon oxide mask layer being formed on the low-K dielectric mask layer 24 is single layer structure, shape
Include at step：
With reference to figure 16, tetraethyl orthosilicate layer 361 is first formed in the low-K dielectric material layer 24, later again to institute
It states tetraethyl orthosilicate layer 361 and carries out oxygen plasma treatment so that oxygen plasma and the tetraethyl orthosilicate layer
361 reactions, to form silicon oxide mask layer 362.
In order to reduce the carbon atom in the silicon oxide mask layer 362, the stream of oxygen in oxygen plasma treatment can be improved
The process conditions such as the time of amount and oxygen plasma treatment keep oxygen plasma fully anti-with tetraethyl orthosilicate layer 361
It answers, to efficiently shift the carbon atom in original tetraethyl orthosilicate layer 361, effectively reduces and be formed by silicon oxide mask
Carbon content in layer 362.The present embodiment can reduce the complexity of technological process.
After forming the silicon oxide mask layer 362, directly metal mask can be formed on the silicon oxide mask layer 362
Layer 37 performs etching the techniques such as dielectric layer, filling conductive material, to form interconnection structure, the step of these subsequent techniques again later
Rapid similar to the aforementioned embodiment, details are not described herein.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (14)
1. a kind of forming method of interconnection structure, which is characterized in that including：
Substrate is provided；
Dielectric layer is formed on the substrate；
Tetraethyl orthosilicate layer is formed on the dielectric layer；
Oxygen plasma treatment, the oxygen plasma and the tetraethyl orthosilicic acid are carried out to the tetraethyl orthosilicate layer
Salt deposit reacts to form silicon oxide mask layer；
Metallic mask layer is formed on the silicon oxide mask layer；
The metallic mask layer and silicon oxide mask layer are etched, hard mask is formed；
Using the hard mask as dielectric layer described in mask etching, through-hole is formed in the dielectric layer；
Conductive material is filled in the through-hole, to form conductive plunger.
2. the forming method of interconnection structure as described in claim 1, which is characterized in that
The amount of oxygen used by tetraethyl orthosilicate layer progress oxygen plasma treatment is more than and forms tetrem base
The amount of the tetraethyl orthosilicate used when silicate layer.
3. the forming method of interconnection structure as claimed in claim 2, which is characterized in that carry out used in oxygen plasma treatment
The amount ratio of oxygen and the substance of tetraethyl orthosilicate used when forming tetraethyl orthosilicate layer is 5:1~50:1.
4. the forming method of interconnection structure as described in claim 1, which is characterized in that form the side of tetraethyl orthosilicate layer
Method is chemical vapour deposition technique.
5. the forming method of interconnection structure as claimed in claim 4, which is characterized in that form the step of tetraethyl orthosilicate layer
The flow of tetraethyl orthosilicate is less than or equal to 200mg/min in rapid.
6. the forming method of interconnection structure as described in claim 1, which is characterized in that form the step of tetraethyl orthosilicate layer
The synthesis speed of tetraethyl orthosilicate layer is in rapid
7. the forming method of interconnection structure as described in claim 1, which is characterized in that the thickness of the tetraethyl orthosilicate layer
Degree is
8. the forming method of interconnection structure as described in claim 1, which is characterized in that the tetraethyl orthosilicate layer into
The step of row oxygen plasma treatment includes：It is passed through the oxygen that flow is 10000~20000sccm.
9. the forming method of the interconnection structure as described in claim 5 or 8, which is characterized in that form tetraethyl orthosilicate layer
The step of include：Air pressure is 0.1~10torr, and power is 100~5000W, the flow of tetraethyl orthosilicate is 10~
150mg/min；
Include to the step of tetraethyl orthosilicate layer progress oxygen plasma treatment：Air pressure is 0.1~10torr, power
Flow for 100~5000W, oxygen is 15000~20000sccm.
10. the forming method of interconnection structure as described in claim 1, which is characterized in that before forming the metallic mask layer,
The forming method of the interconnection structure includes：
It is repeatedly formed the tetraethyl orthosilicate layer and oxygen plasma treatment is carried out to the tetraethyl orthosilicate layer
The step of, to form silicon oxide mask layer.
11. the forming method of interconnection structure as described in claim 1, which is characterized in that execution forms tetraethyl orthosilicate
Layer and step 1~6 time for carrying out oxygen plasma treatment, to form silicon oxide mask layer.
12. the forming method of interconnection structure as described in claim 1, which is characterized in that the tetraethyl orthosilicate layer
Oxygen plasma treatment is carried out, includes the step of silicon oxide mask layer to be formed：The content for forming carbon atom is less than or equal to 1.0
×1018The silicon oxide mask layer of a atoms per cubic centimeter.
13. the forming method of interconnection structure as described in claim 1, which is characterized in that form through-hole in the dielectric layer
Afterwards, before filling conductive material in the through-hole, the forming method of the interconnection structure further includes carrying out wet-cleaning to through-hole
Step.
14. the forming method of interconnection structure as described in claim 1, which is characterized in that form oxidation on the dielectric layer
Before mask layer, the forming method of the interconnection structure further includes the formation low-K dielectric mask layer on the dielectric layer, described low
The K values of K dielectric mask layers are less than or equal to 3；
The step of etching the metallic mask layer and silicon oxide mask layer, forming hard mask include：
The metallic mask layer, silicon oxide mask layer and low-K dielectric mask layer are etched, to form hard mask.
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