CN104979271B - The forming method of interconnection structure - Google Patents
The forming method of interconnection structure Download PDFInfo
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- CN104979271B CN104979271B CN201410133369.XA CN201410133369A CN104979271B CN 104979271 B CN104979271 B CN 104979271B CN 201410133369 A CN201410133369 A CN 201410133369A CN 104979271 B CN104979271 B CN 104979271B
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Abstract
The invention provides a kind of forming method of interconnection structure, including：After forming dielectric layer on a semiconductor substrate, the first mask using metal mask as material is formed on the dielectric layer, forms the second mask on the first mask afterwards, and carries out the first etching by mask of the second mask, and through hole is formed in dielectric layer；Remove afterwards after the second mask exposes the first mask, carry out the second etching by mask of the first mask, groove is formed in dielectric layer, and the second etching uses non-fluorine-based etching agent.In the second etching process, the etching agent used is non-fluorine-based etching agent, so as to effectively avoid in the second etching technics, fluorine ion reacts to form the accessory substance containing metal fluoride with metal mask, and avoid this part metals fluoride from further being reacted with dielectric layer and cause dielectric layer to damage, damaged so as to reduce etching technics for dielectric layer.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of forming method of interconnection structure.
Background technology
As semiconductor technology develops, the integrated level of device is continuously increased, device feature size（Critical
Dimension, CD）It is less and less.
And as characteristic size must be gradually reduced, the reason such as parasitic capacitance between interconnection structure and caused RC retardation ratio（RC
delay）Influence to semiconductor devices is increasing.The K values for reducing interconnection structure dielectric layer material are that effective RC that reduces prolongs
The method of slow effect.In recent years, low-K dielectric material（K ＜ 3）To be increasingly becoming the mainstay material of dielectric layer, and with semiconductor
Device development demand, the K values of used dielectric layer material constantly reduce.
Prior art also substitutes traditional aluminium as the metal plug in interconnection structure using the smaller copper of resistance coefficient
Material, to reduce the resistance of metal plug itself.Simultaneously as the fusing point of copper is high, and anti-electromigration ability is also stronger,
Relative to the metal plug of traditional aluminum, higher current density can be carried, is entered and is advantageous to and improves the chip of formation
Packaging density.Specifically, prior art uses Damascus（Damascene）Or dual damascene (Dual
Damascene) technique forms the metal plug of copper.
Generally required in dual damascene process by photoresist to define the groove for needing to be formed（Trench）And
Through hole（Via）, low-K dielectric material or super low-K dielectric material are mostly loose porous structure, and the process for removing photoresist is easy
The low-K dielectric material or super low-K dielectric material are caused to damage.Impaired low-K dielectric material becomes more hygroscopic, and easily
In with other processing contaminants react and change the electrology characteristic of dielectric layer, so as to cause low-K dielectric material K values increase and reduce
Performance of semiconductor device.
For this how to reduce low-K dielectric material it is impaired be those skilled in the art's urgent need to resolve the problem of.
The content of the invention
Of the invention to solve the problems, such as to be to provide a kind of forming method of interconnection structure, reduction low-K dielectric material is impaired to ask
Topic, improve the performance of the semiconductor devices of formation.
To solve the above problems, the present invention provides a kind of forming method of interconnection structure, there is Damascus for being formed
The interconnection structure of structure, the forming method include：
Semiconductor substrate is provided；
Dielectric layer is formed on the semiconductor substrate；
The first mask for forming groove in the dielectric layer is formed on the dielectric layer, first mask is metal
Mask；
The second mask for forming through hole in the dielectric layer is formed on first mask；
The first etching is carried out to the dielectric layer by mask of second mask, it is logical to be formed in the dielectric layer
Hole；
Remove second mask and expose first mask；
The second etching is carried out to the dielectric layer by mask of first mask, to form ditch in the dielectric layer
Groove, second etching use non-fluorine-based etching agent.
Alternatively, the step of carrying out the second etching to the dielectric layer with first mask includes：Using hydrogen, nitrogen
It is one or more to dielectric layer progress dry etching in gas, oxygen or argon gas.
Alternatively, in the step of second etching, in the etching gas, the percent by volume of hydrogen for 10%~
90%。
Alternatively, the step of second etching includes：
Power is 50~1000W, and gas flow is 10~1000sccm, and air pressure is 5mtorr~500mtorr, and temperature is
50~150 DEG C.
Alternatively, the material of the metal mask is titanium nitride, boron nitride or aluminium nitride.
Alternatively, the step of also including wet-cleaning after the second etching.
Alternatively, the step of wet-cleaning includes：Wet-cleaning is carried out using hydrogen fluoride solution.
Alternatively, the step of carrying out the first etching to the dielectric layer as mask using second mask includes：Using non-
Fluorine-based etching agent carries out the first etching to the dielectric layer.
Alternatively, the step of carrying out the first etching to the dielectric layer using non-fluorine-based etching agent includes：Using including hydrogen
The etching gas of gas carry out dry etching to the dielectric layer, to form through hole.
Alternatively, second mask is photoresist.
Alternatively, after the groove is formed, also include repairing step before the cleaning step, in the groove of formation
Protective layer is formed with the side wall of through hole and bottom.
Alternatively, it is the gas that 100~1000sccm contains He or Ar that the reparation step, which includes being passed through flow, is continued
Time is 10s~30min.
Alternatively, the material of the dielectric layer is low-K dielectric material or super low-K dielectric material.
Compared with prior art, technical scheme has advantages below：
After forming dielectric layer on a semiconductor substrate, the first mask using metal mask as material is formed on the dielectric layer,
The second mask is formed on the first mask afterwards, and the first etching is carried out by mask of the second mask, is formed in dielectric layer logical
Hole；Remove afterwards after the second mask exposes the first mask, carry out the second etching by mask of the first mask, formed in dielectric layer
Groove, and second etching uses non-fluorine-based etching agent.In the second etching process, the etching agent used is non-fluorine-based quarter
Agent is lost, so as to effectively avoid in the second etching technics, fluorine ion reacts to be formed containing metal fluoride with metal mask
（MeFx）Accessory substance, can also reducing this part metals fluoride and dielectric layer, further reaction causes dielectric layer to damage, and enters
And reduce etching technics and damaged for dielectric layer；In addition, second etching using non-fluorine-based etching agent can also effectively avoid fluorine from
Son, metal fluoride and dielectric layer further react and form new etch by-products, and reduce and produced in etching process
Raw accessory substance influences for the interconnection structure of formation, in turn results in the interconnection structure performance impact for being subsequently formed.
Further, in the first etch step, using dielectric layer described in non-fluorine-based etchant, so as to further drop
The accessory substance to be formed is reacted based on fluorine ion, metal mask, dielectric layer in low etching process；In addition, the first etch step and
In two etch steps, avoid effectively avoiding fluorine ion in the etching process of dielectric layer as etching agent using fluorine base gas
Remain in dielectric layer or hard mask layer, so as to avoid fluorine ion in the subsequent technique of semiconductor devices preparation from causing dielectric layer
Damage, and then influence the performance of semiconductor devices being subsequently formed.
Further, after forming groove the step of second etches, also include repairing step before the cleaning step,
The step of repairing can realize the side wall of the through hole in dielectric layer, and the side wall of groove and bottom densification, in the through hole
Side wall, and protective layer is formed on the side wall of groove and bottom, can be kept away using the compact surfaces sealing dielectric material of protective layer
Exempt from the problem of dielectric material makes moist in semiconductor preparation；It is filled in groove moreover, the protective layer can also be reduced effectively and leads to
The problem of being spread in metal material in hole in metallic atom dielectric layer, improve the reliability of the interconnection structure being subsequently formed and steady
It is qualitative.
Brief description of the drawings
The structural representation formed in a kind of existing low-K dielectric material layers of Fig. 1 after groove；
Fig. 2~Fig. 4 be it is existing form groove in low-K dielectric material layer, and after filling metal material in groove
Electron microscope；
Fig. 5~Fig. 9 is the structural representation using one embodiment of the forming method of interconnection structure of the present invention.
Embodiment
As stated in the Background Art, in the prior art, in low-K dielectric material（K ＜ 3）Dielectric layer in formed groove process
In, low-K dielectric material easily sustains damage, so as to reduce the performance for the interconnection structure being subsequently formed.With reference to reference to shown in figure 1
Prior art and referring to figs. 2 to its reason of the Electronic Speculum map analysis of metal material in the groove shown in Fig. 4：
As shown in figure 1, prior art is in low-K dielectric material（K ＜ 3）Dielectric layer in formed groove 13 when, mostly use
Fluorine（F）Base gas performs etching as the dielectric layer 11 that etching gas are pointed in Semiconductor substrate 10.In etching process, F
Base gas can react formation with metal hard mask 12 and contain metal fluoride（MeFx）Accessory substance, and with F bases gas etch be situated between
During electric layer 11, F bases gas, metal fluoride, and dielectric layer further react, and so as to cause dielectric layer 11 to damage, cause brokenly
The defects of 14 flatness of the side wall of bad groove 13 and bottom.As shown in Fig. 2（Fig. 2 is after filling metal material 15 into groove 13
Electron microscope）, the existing material of metal hard mask layer 12 is mostly the metal nitrides such as TiN, and F bases gas can react with TiN, is formed
All kinds of accessory substances such as TiFx, this part accessory substance are mixed in metal material, so as to influence the electricity of the interconnection structure ultimately formed
Performance is learned, such as reduces the TDDB of semiconductor devices.
In addition, existing low-K dielectric material is mostly multi-pore structure, during using F base gas etchings dielectric layer 11,
Part F ion is remained in dielectric layer 11, so as in semiconductor devices subsequent preparation process, cause dielectric layer to damage.With reference to
Fig. 3（The bottom electron microscope of groove 13）And Fig. 4（The side wall electron microscope of groove 13）, the side wall 14 of groove 13 and bottom 15 easily occur
Damage, the inwall flatness of groove 13 is reduced, influences the form of interconnection structure being subsequently formed.
In order to solve the above problems, the invention provides a kind of forming method of interconnection structure, effectively alleviate low k dielectric layer
The damage being subject to.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 5~Fig. 9 is the structural representation of forming method one embodiment of interconnection structure of the present invention.
The forming method for the interconnection structure that the present embodiment provides includes：
Referring initially to shown in Fig. 5, there is provided Semiconductor substrate 30, dielectric layer 31 is formed in the Semiconductor substrate 30.
In the present embodiment, the Semiconductor substrate 30 includes：Semiconductor base or semiconductor base and being formed at partly is led
Body substrate is interior or the semiconductor components and devices of semiconductor substrate surface, the semiconductor components and devices include cmos device, the CMOS
Device includes transistor, memory, capacitor or electric part, and for making the electrical interconnection knot of the semiconductor components and devices electrical connection
Structure, and the structure such as insulating barrier for being electrically isolated the semiconductor components and devices and electric interconnection structure.
The semiconductor base is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator（SOI）Substrate, insulator
Upper germanium（GOI）Substrate, glass substrate or III-V substrate, the semiconductor base materials do not limit the present invention's
Protection domain.
In the present embodiment, the material of the dielectric layer 31 is low-K dielectric material（K values are less than 3）Or super low-K dielectric material
（K values are less than 2.6）.After subsequently forming interconnection structure in the dielectric layer 30, low-K dielectric material can effectively reduce interconnection structure
Parasitic capacitance, so as to reduce the RC delays occurred when signal transmits in interconnection structure（RC Delay）Effect.
Alternatively, in the present embodiment, the dielectric layer 31 uses super low-K dielectric material.
In the present embodiment, the dielectric layer 31 is mostly loose structure, such as the silica of the carbon dope of loose structure.It is described porous
The formation process of the silica of the carbon dope of structure includes：First formed and mixed in Semiconductor substrate 30 using chemical vapor deposition method
Silicon oxycarbide layer, afterwards using porous handling process（Such as UV treatment technique）At the silicon oxide layer of the carbon dope
Reason, form the silicon oxide layer of porous carbon dope.
Afterwards, the dielectric layer 31 is etched, through hole and groove, the through hole and groove are formed in the dielectric layer 31
It is subsequently used for filling metal material, to form interconnection structure.
In the present embodiment, through hole and the method for groove are formed in the dielectric layer 31 to be included：
With continued reference to shown in Fig. 5, the first hard mask layer 32 is first formed on dielectric layer 31, afterwards, is covered firmly described first
Silicon oxide layer 39, light optimization are sequentially formed in mold layer 32 from the bottom to top（Optical Development Layer, ODL）Layer 37,
Silicon antireflection（Si-anti Reflection Coating, Si-ARC）The photoresist layer 33 of layer 38 and first；It is exposed afterwards aobvious
After shadow technique, channel patterns are formed in first photoresist layer 33, and along the channel patterns, etch the silicon anti-reflective
Penetrate（Si-anti Reflection Coating, Si-ARC）Layer 38, light optimization（Optical Development Layer,
ODL）Layer 37, the hard mask layer 32 of silicon oxide layer 39 and first, channel patterns 41 are transferred in first hard mask layer 32.
First hard mask layer 32 is metal hard mask layer, and specific material includes titanium nitride（TiN）, boron nitride（BN）Or
Aluminium nitride（AlN）.
In the present embodiment, the material of first hard mask layer 32 is TiN.
It is worth noting that, in the present embodiment, the ODL layers 37, Si-ARC layers 38, it can effectively improve and be covered firmly first
The precision of the pattern formed in mold layer 32；The silicon oxide layer 39 can improve first hard mask layer 32 and the ODL layers 37
Bond strength, if but do not formed the silicon oxide layer 39, ODL layers 37, Si-ARC layers 38 have no effect on the purpose of the present invention reality
It is existing.The silicon oxide layer 39, ODL layers 37, Si-ARC layers 38 whether is formed to have no effect within the scope of the present invention, herein
Repeat no more.
In the present embodiment, alternatively, the etching gas that above-mentioned the first hard mask layer of etching 32 uses is non-fluorine（F）Base gas
Body, the gas containing HBr can be specifically used to etch first hard mask layer 32 for etching gas, so as to avoid fluorine base gas
The compound of titanium and fluorine is formed with the reaction of the first hard mask layer 32（TiFx）, so that in follow-up interconnection structure formation process, titanium
Reacted with the compound of fluorine with etching gas or dielectric layer, reduce the amount that etch by-products are formed；In addition, it can also avoid etching
During, caused F ion remains in first photoresist layer 33, or first hard mask layer 32 and dielectric layer 31
In, so as in follow-up interconnection structure formation process, avoid F ion from causing dielectric layer 31 to damage.
Then with reference to reference to shown in figure 6, after forming the channel patterns 41 in first hard mask layer 32, institute is removed
State the first photoresist layer 33, ODL layers 37 and Si-ARC layers 38, and on the surface of the silicon oxide layer 39, from the bottom to top again successively
Form light optimization（Optical development layer, ODL）Layer 34, silicon antireflection（Si-ARC）The photoetching of layer 35 and second
Glue-line 36.The full channel patterns 41 of the filling of ODL layers 34.Exposed developing process afterwards, in second photoresist layer
Through-hole pattern 42 is formed in 36.
With reference to reference to shown in figure 7, the first etching technics is carried out along the through-hole pattern 42, is sequentially etched the Si-arc
Layer 35, ODL layers 34, the hard mask layer 32 of silicon oxide layer 39 and first and dielectric layer 31, through hole 43 is formed in the dielectric layer 31.
In the present embodiment, the through hole 43 runs through the dielectric layer 31, until Semiconductor substrate 30 described in exposed portion.
It is worth noting that, in the present embodiment, the Si-arc layers 35, ODL layers 34, which can effectively improve, to be subsequently formed in institute
The precision of through hole 43 in electric layer 31 is given an account of, but in the other embodiment in addition to the present embodiment, the Si-arc layers can not be formed
35 and ODL layers 34, the purpose of the present invention equally can be achieved in it, and the Si-arc layers 35, ODL layers 34 have no effect on the present invention
Protection domain.
First etching technics is dry etch process.
Alternatively, in the present embodiment, the dry etch process uses non-F bases etching agent, and the non-F bases etching agent is free of
There is F gas.So as to avoid the accessory substance formed in the first hard mask layer 32, dielectric layer 31 and previous etching technics, with F
Ionic reaction forms the accessory substance containing F, and then reduces when etching the dielectric layer 31 to damage caused by dielectric layer 31, drops simultaneously
These low accessory substances containing F are for the performance impact for the interconnection structure being subsequently formed；In addition can also be effective using non-F bases etching agent
F ion is avoided to remain in second photoresist layer 36 and dielectric layer 31, so as to which avoid interconnection structure is subsequently formed work
In skill, F ion causes dielectric layer 31 to damage.
Specifically, in the present embodiment, the technological parameter of dielectric layer 31 includes described in the first etching technics：
Using containing hydrogen（H2）Gas as etching gas, power is 50~1000W, gas flow is 10~
1000sccm, air pressure are 5mtorr~500mtorr, and temperature is 50~150 DEG C.
Still optionally further, in the present embodiment, the dry etching gas may also include auxiliary gas, the auxiliary gas
Contain N2、O2Or the one or more in Ar.Wherein, in the etching gas, H2Percent by volume be 10%~90%, institute
Stating the specific composition of etching gas and ratio can require to determine according to the thickness of dielectric layer 31, and etching.
With reference to described in reference diagram 8, after forming the through hole 43 in dielectric layer 31, the photoresist layer 36, Si-arc are removed
Layer 35 and ODL layers 34, expose the silicon oxide layer 39, and along the groove in the hard mask layer 32 of silicon oxide layer 39 and first
Pattern 41（As shown in Figure 5）The second etching technics is carried out, continues to etch the dielectric layer 31, is formed on the surface of dielectric layer 31
Groove 44.
In the present embodiment, the dielectric layer 31 is etched, the second etching technics for forming the groove 44 is dry etching work
Skill, and second etching technics uses non-F bases etching agent, the non-F bases etching agent is free of F base gases.
In the present embodiment, second etching technics includes：To contain hydrogen（H2）Gas be dry etching, power is
50~1000W, gas flow are 10~1000sccm, and air pressure is 5mtorr~500mtorr, and temperature is 50~150 DEG C.
Still optionally further, the etching gas may also include auxiliary gas, and the auxiliary gas includes N2、O2Or in Ar
One or more.Wherein, in the etching gas, H2Percent by volume be 10%~90%.
In one alternative embodiment of second etching technics, by the temperature control of etching technics in 50~60 DEG C.
At this temperature, the etch rate of the silicon oxide layer 39 is more than the etch rate of first hard mask layer 32, after increasing
Continue the opening of the groove 44 formed in silicon oxide layer 39, be easy to fill metal material into the groove 44 and through hole 43, and
The density of groove 44 and the metal material in through hole 43 can be improved, so as to improve the performance for the interconnection structure being subsequently formed.
In another alternative embodiment of second etching technics, by the temperature control of etching technics in 100~150
℃.At such a temperature, when can effectively reduce the etching dielectric layer, etching gas, dielectric layer, and before in each etching technics
The amount for the polymer that reaction between the accessory substance formed is formed.
In the present embodiment, the technique for removing the first photoresist layer 33 and the second photoresist layer 36 is chosen as wet etching work
Skill, or cineration technics, it is the mature technology of this area, be will not be repeated here.
With reference to shown in figure 9, in the present embodiment, after the groove 44 is formed, reparation step is carried out, is given an account of so as to realize
The surface densification of electric layer 31, protection is formed in the side wall of the through hole 43 of the dielectric layer 31, and the side wall of groove 44 and bottom
Layer 45.
In the present embodiment, the concrete technology for repairing step includes：
It is 100~2000W to control the power in reaction chamber, be continually fed into flow be 100~1000sccm contain He or
Ar gas 10 seconds（s）~30 minutes（min）.
In the present embodiment, the first photoresist layer and the second photoresist layer, and etching are removed using cineration technics removing
In the technique of the dielectric layer 31, the dielectric layer 31 is unavoidably caused to damage.Especially under the high temperature conditions, such as 100
~150 DEG C, the damage of low-K dielectric material is larger.
Low-K dielectric material after impaired is more easy to the moisture absorption, and with other pollutant reactions, it is overall so as to influence dielectric layer 31
Electric property.In the present embodiment, through it is described reparation step after, can the through hole 43 side wall, and the side wall of groove 44 and
After the protective layer 45 is formed on bottom, the low-K dielectric material that can effectively alleviate the lower section of protective layer 45 is damaged by wet environment
Wound；In addition, after metal material is filled subsequently into the through hole 43 and groove 44, the protective layer 45 can effectively avoid metal
Atom spreads into the dielectric layer 31, so as to improve the stability for the interconnection structure being subsequently formed.
In the present embodiment, after the reparation step, semiconductor devices is taken out into reaction chamber, and to the described logical of formation
Hole 43 and groove 44 carry out cleaning step.
In above-mentioned etch step, etching residue, the cleaning step can be formed in the side wall of the through hole 43 and groove 44
Suddenly this partial etching residual can be effectively removed, mutual link is formed to reduce the filling metal material in the through hole 43 and groove 44
The etching residue remained in after structure in interconnection structure, and thus reduce electric property shadow of the etching residue to interconnection structure
Ring.
In the present embodiment, the cleaning fluid that the cleaning step uses includes DHF solution（Dilute hydrofluoric acid solution）, dilution
EKC solution（The solute main component of EKC solution includes：Azanol（HDA）；2-（2- amino ethoxies）Ethanol（DGA）；Lead benzene two
Phenol（Catechol））Or H2O2Solution（Hydrogen peroxide solution）.
In the present embodiment, the cleaning fluid of use uses DHF solution, and wherein in DHF solution, the volume ratio of HF and water is 1：
300~1:1000.
The above-mentioned protective layer 45 in through hole 43 and groove 44, the cleaning solution can be also effectively reduced for low-K dielectric
The corrosion of material.
Compared in the prior art, after the gas etching of base containing F dielectric layer 31, part F ion can remain the dielectric
In layer 31, and by taking out the semiconductor devices in reaction chamber after, the F bases gas that remains in dielectric layer 31 can with air
Steam react to form HF solution, so as to corrode dielectric layer 31.The first etching technics and the second etching technics in the present invention are adopted
With non-F bases etching agent, so as to effectively alleviate the damage to dielectric layer 31 for these reasons.
In addition, in the preparation technology of semiconductor devices, after the groove 44 is formed, obtain and carry out cleaning rapidly,
So as to avoid residuing in the reaction of the water in F ion and air in dielectric layer 31.This example can be effectively increased to form groove 44 after,
With the residence time among cleaning step, so as to increase process window, reduce semiconductor devices and prepare cost.
After the cleaning step, metal material can be filled in the through hole 43 and groove 44, and use chemical machinery
Grinding（CMP）Unnecessary metal material, and the first hard mask layer 32 and silicon oxide layer 39 on dielectric layer 31 are removed etc. technique,
Expose the dielectric layer 31 so that the surface of dielectric layer 31 flushes with the layer on surface of metal in the groove 44, mutually links to be formed
Structure.The step is the mature technology of this area, be will not be repeated here.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (13)
- A kind of 1. forming method of interconnection structure, for forming the interconnection structure with damascene structure, it is characterised in that institute Stating forming method includes：Semiconductor substrate is provided；Dielectric layer is formed on the semiconductor substrate；The first mask for forming groove in the dielectric layer is formed on the dielectric layer, first mask is covered for metal Mould；Wherein, the generation type of the first mask for forming groove in the dielectric layer is:The first hard mask is formed on the dielectric layer Layer, sequentially forms silicon oxide layer, light optimization layer, silicon anti-reflecting layer and the first photoetching from the bottom to top on first hard mask layer Glue-line；Afterwards after exposed developing process, channel patterns are formed in first photoresist layer, and along the groove figure Case, the silicon anti-reflecting layer, light optimization layer, silicon oxide layer and the first hard mask layer are etched, channel patterns are transferred to described In one hard mask layer, to form the first mask for being used for forming groove in the dielectric layer；Formed and be used on first mask The second mask of through hole is formed in the dielectric layer；The first etching is carried out to the dielectric layer by mask of second mask, to form through hole in the dielectric layer；Remove second mask and expose first mask；The second etching, to form groove in the dielectric layer, institute are carried out to the dielectric layer by mask of first mask State the second etching and use non-fluorine-based etching agent.
- 2. forming method as claimed in claim 1, it is characterised in that second is carried out to the dielectric layer with first mask The step of etching, includes：Using one or more to dielectric layer progress dry etching in hydrogen, nitrogen, oxygen or argon gas.
- 3. forming method as claimed in claim 2, it is characterised in that it is described second etching the step of in, in etching gas, hydrogen The percent by volume of gas is 10%~90%.
- 4. forming method as claimed in claim 1, it is characterised in that described second includes the step of etching：Power be 50~ 1000W, gas flow are 10~1000sccm, and air pressure is 5mtorr~500mtorr, and temperature is 50~150 DEG C.
- 5. forming method as claimed in claim 1, it is characterised in that the material of the metal mask is titanium nitride, boron nitride Or aluminium nitride.
- 6. forming method as claimed in claim 1, it is characterised in that also include the step of wet-cleaning after the second etching Suddenly.
- 7. forming method as claimed in claim 6, it is characterised in that include the step of the wet-cleaning：Using hydrogen fluoride Solution carries out wet-cleaning.
- 8. forming method as claimed in claim 1, it is characterised in that enter using second mask as mask to the dielectric layer The step of row first etches includes：First etching is carried out to the dielectric layer using non-fluorine-based etching agent.
- 9. forming method as claimed in claim 8, it is characterised in that the is carried out to the dielectric layer using non-fluorine-based etching agent The step of one etching, includes：Dry etching is carried out to the dielectric layer using the etching gas comprising hydrogen, to form through hole.
- 10. the forming method as described in claim 1 or 8, it is characterised in that second mask is photoresist.
- 11. forming method as claimed in claim 6, it is characterised in that after the groove is formed, the cleaning step it It is preceding also to include repairing step, form protective layer in the groove of formation and the side wall of through hole and bottom.
- 12. forming method as claimed in claim 11, it is characterised in that the reparation step include being passed through flow for 100~ 1000sccm contains He or Ar gas, and the duration is 10s~30min.
- 13. forming method as claimed in claim 1, it is characterised in that the material of the dielectric layer is low-K dielectric material or surpassed Low-K dielectric material.
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| CN106409751B (en) * | 2015-07-27 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105845624A (en) * | 2016-05-11 | 2016-08-10 | 上海华虹宏力半导体制造有限公司 | Manufacturing methods of through hole and conductive plug |
| CN107731745B (en) * | 2017-10-18 | 2020-03-10 | 武汉新芯集成电路制造有限公司 | Preparation method of vase-shaped contact hole |
| CN117976685B (en) * | 2024-03-29 | 2024-06-14 | 合肥晶合集成电路股份有限公司 | Image sensor and preparation method thereof |
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| CN103165518A (en) * | 2011-12-08 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of interconnected structure |
| CN103474342A (en) * | 2012-06-06 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing damaged dielectric layer |
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