CN104967297A - Trilinear buffer driving type asymmetric bipolar logic amplification power supply device - Google Patents
Trilinear buffer driving type asymmetric bipolar logic amplification power supply device Download PDFInfo
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Abstract
The invention discloses a trilinear buffer driving type asymmetric bipolar logic amplification power supply device, comprising a direct current power supply S, a diode D1, an electronic switch K connected with the diode D1 in parallel, a passive pi-shaped filter circuit connected in series between the N pole of the diode D1 and the negative pole of the direct current power supply S, an emitter coupling type asymmetric circuit connected with the passive pi-shaped filter circuit, and light beam excitation type logic amplification circuit connected in series between the emitter coupling type asymmetric circuit and the direct current power supply S; and at the same time, a trilinear buffer drive circuit is connected in series between the negative pole of the direct current power supply S and the light beam excitation type logic amplification circuit. The trilinear buffer driving type asymmetric bipolar logic amplification power supply device provided by the invention contains multiple stages of filter circuits and the logic amplification circuit, and thus can effectively remove multiple harmonic waves caused by a load change, can ensure detection accuracy, and can ensure that relatively large attenuation of an amplified signal does not occur, thereby guaranteeing quality and performance of the amplified signal.
Description
Technical field
The present invention relates to a kind of bipolar power supply device, specifically refer to a kind of emitter-base bandgap grading manifold type asymmetric double polarity power for testing the function of battery protection circuit and calibrate.
Background technology
At present; whether battery manufacturer generally all needs the various functions detecting this battery protection circuit with bipolar power supply up to standard after having made battery protection circuit, namely utilizes bipolar power supply to realize the quickly calibrated and test of overvoltage to battery protection circuit, under-voltage, overcurrent fast.When so-called bipolar power supply refers to this corona discharge, the electric current of its power source internal flows to positive pole from negative pole, and be flow to negative pole (when the electric current of traditional its inside of common power all can only flow to positive pole from negative pole, and can not flow to negative pole from positive pole) from positive pole to the electric current of its power source internal during this power source charges.But, not only structure is comparatively complicated, volume is comparatively huge for bipolar power supply sold on the market at present, its cost is extremely expensive, average every platform price can reach 5 ~ 100,000 yuan, and through traditional power amplification circuit after carrying out power drive amplification, not only the attenuation amplitude of its amplifying signal is comparatively large, also can be subject to outside electromagnetic interference, and then make amplifying signal performance comparatively unstable.Therefore, bipolar power supply existing on the market at present can not meet the demand of numerous clients, can not be promoted widely and use.
Although the Chinese invention patent that the patent No. is 200920243086.5 proposes a kind of bipolar power supply, its unstable properties, effectively can not overcome external electromagnetic interference and related load and change the nonlinear temperature change brought, can cause detecting inaccurate.
Summary of the invention
The object of the invention is to overcome current bipolar power supply unstable properties, can cause detecting inaccurate defect, provide a kind of three linear buffer drive-type asymmetric double polarity logics to amplify supply unit.
Object of the present invention is achieved through the following technical solutions: a kind of three linear buffer drive-type asymmetric double polarity logics amplify supply unit, by DC power supply S, P pole is connected with the positive pole of DC power supply S, N pole forms the diode D1 in loop after load resistance with the negative pole of DC power supply S, and the electronic switch K to be in parallel with diode D1, passive π type filter circuit is serially connected with between the N pole and the negative pole of DC power supply S of diode D1, and the emitter-base bandgap grading manifold type asymmetric circuit to be connected with passive π type filter circuit, the beam excitation formula logic amplifying circuit be serially connected between the asymmetric circuit of emitter-base bandgap grading manifold type and DC power supply S forms, three linear buffer drive circuits are also serially connected with between the negative pole and beam excitation formula logic amplifying circuit of DC power supply S, described three linear buffer drive circuits are by integrated package U1, field effect transistor MOS, triode Q4, triode Q5, negative pole is connected with the collector electrode of triode Q5, positive pole is in turn through resistance R22, polar capacitor C12, the polar capacitor C10 be connected with the source electrode of field effect transistor MOS after resistance R20, positive pole is connected with the emitter of triode Q5 after resistance R24, the polar capacitor C9 that negative pole is connected with the CS pin of integrated package U1, positive pole is connected with the DIM pin of integrated package U1 after inductance L 2, the polar capacitor C11 that negative pole is connected with the HYS pin of integrated package U1 after resistance R23, one end is connected with the tie point of polar capacitor C12 with resistance R22, the resistance R21 that the other end is connected with the base stage of triode Q5 after inductance L 1, positive pole is connected with the collector electrode of triode Q4, the polar capacitor C13 that negative pole is connected with the LIM pin of integrated package U1 after resistance R19, P pole ground connection, the diode D4 that N pole is connected with the drain electrode of field effect transistor MOS, and one end is connected with the base stage of triode Q4, the resistance R18 that the other end is connected with the SNS pin of integrated package U1 forms, the HG pin of described integrated package U1 is connected with the grid of field effect transistor MOS, its GND pin ground connection, and its IN pin is connected with the tie point of inductance L 1 with resistance R21, the positive pole of described polar capacitor C11 is connected with beam excitation formula logic amplifying circuit, the described emitter of triode Q4 is connected with the negative pole of DC power supply S.
Described beam excitation formula logic amplifying circuit, primarily of power amplifier P, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the electrode input end of power amplifier P, the polar capacitor C6 of positive pole ground connection after optical diode D2, one end is connected with the positive pole of polar capacitor C6, the resistance R13 of other end ground connection after diode D3, positive pole is connected with the tie point of diode D3 with resistance R13, the polar capacitor C7 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R14 that the other end is connected with the electrode input end of power amplifier P, be serially connected in the resistance R15 between the negative input of power amplifier P and output, one end is connected with the output of NAND gate IC1, the resistance R16 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C8 that negative pole is connected with the negative input of NAND gate IC3, and one end ground connection after polar capacitor C7, the resistance R17 that the other end is connected with the negative input of NAND gate IC2 forms, the electrode input end of described NAND gate IC1 is connected with the negative input of power amplifier P, and its output is connected with the electrode input end of NAND gate IC2, the electrode input end of NAND gate IC3 is connected with the output of power amplifier P, and its output is then connected with the positive pole of polar capacitor C11, the electrode input end of described power amplifier P is connected with emitter-base bandgap grading manifold type asymmetric circuit item.
Described passive π type filter circuit is low-pass filter circuit, and it is by electric capacity C1, electric capacity C2, and the resistance R5 be serially connected between the positive pole of electric capacity C1 and the positive pole of electric capacity C2 forms; Be connected with the negative pole of DC power supply S after the negative pole of described electric capacity C1 and the negative pole of electric capacity C2 are connected in series; The positive pole of electric capacity C1 is then connected with the N pole of diode D1.
Described emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, be serially connected in the first-level filtering wave circuit between the emitter of triode Q2 and the base stage of triode Q3, be serially connected in the resistance R6 between the collector electrode of triode Q3 and the collector electrode of diode Q2, be serially connected in the resistance R12 between the collector electrode of triode Q1 and the collector electrode of triode Q2, be serially connected in the secondary filter circuit between the emitter of triode Q1 and the negative pole of electric capacity C2, be serially connected in three grades of filters between the base stage of triode Q1 and the negative pole of electric capacity C2, and the resistance R10 be serially connected between the base stage of triode Q1 and the negative pole of electric capacity C2 and the resistance R7 be serially connected between the base stage of triode Q3 and the negative pole of electric capacity C2 forms, the base stage of described triode Q2 is connected with the collector electrode of triode Q1, and its collector electrode is connected with the positive pole of electric capacity C2, the emitter of described triode Q2 and the equal ground connection of emitter of triode Q3.
For guaranteeing result of use, described load resistance is connected in series by resistance R1, resistance R2, resistance R3 and resistance R4 that resistance is identical and forms, and described first-level filtering wave circuit, secondary filter circuit and three grades of filter circuits are RC filter circuit.
Described integrated package U1 employing model is the driving integrated package of LM3401.
The present invention compared with prior art, has the following advantages and beneficial effect:
(1) overall structure of the present invention is simple, and it makes and very easy to use.
(2) the present invention adopts three linear buffer drive circuits to have step-down, voltage stabilizing, programmable current restriction, overcurrent protection.
(3) stable performance of the present invention, effectively can overcome external electromagnetic interference, and can guarantee that larger decay can not occur the signal after it amplifies, thus can guarantee the quality and performance of amplifying signal.
(4) the present invention contains multi-stage filter circuit, therefore effectively can remove the multiple harmonic because load variations causes, and can guarantee the accuracy detected.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
As shown in Figure 1, the present invention is by three linear buffer drive circuits, DC power supply S, and diode D1, electronic switch K, passive π type filter circuit, the asymmetric circuit of emitter-base bandgap grading manifold type and beam excitation formula logic amplifying circuit form.During connection, the P pole of diode D1 is connected with the positive pole of DC power supply S, and its N pole forms loop with the negative pole of DC power supply S after load resistance, and electronic switch K and diode D1 is in parallel.
For guaranteeing result of use, this load resistance is be resistance R1, the resistance R2 of 10K Ω, resistance R3 and resistance R4 by resistance to be connected in series and to form.
Described three linear buffer drive circuits by integrated package U1, field effect transistor MOS, triode Q4, triode Q5, resistance R18, resistance R19, resistance R20, resistance R21, resistance R22, resistance R23, resistance R24, polar capacitor C9, polar capacitor C10, polar capacitor C11, polar capacitor C12, polar capacitor C13, and diode D4 forms.
For guaranteeing result of use, resistance R28 adopts current setting resistor, and its resistance value is 25K Ω; Resistance R23 adopts current-limiting resistor.
During connection, the negative pole of polar capacitor C10 is connected with the collector electrode of triode Q5, positive pole is connected with the source electrode of field effect transistor MOS in turn after resistance R22, polar capacitor C12, resistance R20.The positive pole of polar capacitor C9 is connected with the emitter of triode Q5 after resistance R24, negative pole is connected with the CS pin of integrated package U1.The positive pole of polar capacitor C11 is connected with the DIM pin of integrated package U1 after inductance L 2, negative pole is connected with the HYS pin of integrated package U1 after resistance R23.One end of resistance R21 is connected with the tie point of polar capacitor C12 with resistance R22, the other end is connected with the base stage of triode Q5 after inductance L 1.The positive pole of polar capacitor C13 is connected with the collector electrode of triode Q4, negative pole is connected with the LIM pin of integrated package U1 after resistance R19.The P pole ground connection of diode D4, N pole are connected with the drain electrode of field effect transistor MOS.And one end of resistance R18 is connected with the base stage of triode Q4, the other end is connected with the SNS pin of integrated package U1.
During use, described integrated package U1 employing model is the driving integrated package of LM3401, and it adopts MSOP-8 to encapsulate; It is the controllable current source that a kind of buck regulator derives, and by controlling external MOS2 field effect transistor switch pipe, output current can up to 4A.Its input supply voltage scope is 4.5 ~ 35V, and during work, electric current is 1.05mA, and reference voltage is 200mV, maximum operation frequency 3MHz.
During connection, the HG pin of integrated package U1 is connected with the grid of field effect transistor MOS, its GND pin ground connection, and its IN pin is connected with the tie point of inductance L 1 with resistance R21; The positive pole of described polar capacitor C11 is connected with beam excitation formula logic amplifying circuit; The emitter of described triode Q4 is connected with the negative pole opening DC power supply S.
Described passive π type filter circuit is low-pass filter circuit, and it is made up of electric capacity C1, electric capacity C2 and resistance R5.During connection, be connected with the negative pole of DC power supply S after the negative pole of electric capacity C1 is connected in series with the negative pole of electric capacity C2, resistance R5 is then serially connected between the positive pole of electric capacity C1 and the positive pole of electric capacity C2.Meanwhile, the positive pole of electric capacity C1 is also connected with the N pole of diode D1.
Emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, be serially connected in the first-level filtering wave circuit between the emitter of triode Q2 and the base stage of triode Q3, be serially connected in the resistance R6 between the collector electrode of triode Q3 and the collector electrode of diode Q2, be serially connected in the resistance R12 between the collector electrode of triode Q1 and the collector electrode of triode Q2, be serially connected in the secondary filter circuit between the emitter of triode Q1 and the negative pole of electric capacity C2, be serially connected in three grades of filters between the base stage of triode Q1 and the negative pole of electric capacity C2, and the resistance R10 be serially connected between the base stage of triode Q1 and the negative pole of electric capacity C2 and the resistance R7 be serially connected between the base stage of triode Q3 and the negative pole of electric capacity C2 forms.
Meanwhile, the base stage of this triode Q2 is connected with the collector electrode of triode Q1, and its collector electrode is connected with the positive pole of electric capacity C2; The emitter of described triode Q2 and the equal ground connection of emitter of triode Q3.
For guaranteeing operational effect, this first-level filtering wave circuit is be formed in parallel by the electric capacity C3 of resistance to be the resistance R8 of 10K Ω and capacity be 20 μ F; Described secondary filter circuit is be formed in parallel by the electric capacity C4 of resistance to be the resistance R9 of 8K Ω and capacity be 10 μ F; Three grades of described filter circuits are then for the electric capacity C5 of to be the resistance R11 of 5K Ω and capacity by resistance be 5 μ F is formed in parallel.
Described beam excitation formula logic amplifying circuit is primarily of power amplifier P, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the electrode input end of power amplifier P, the polar capacitor C6 of positive pole ground connection after optical diode D2, one end is connected with the positive pole of polar capacitor C6, the resistance R13 of other end ground connection after diode D3, positive pole is connected with the tie point of diode D3 with resistance R13, the polar capacitor C7 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R14 that the other end is connected with the electrode input end of power amplifier P, be serially connected in the resistance R15 between the negative input of power amplifier P and output, one end is connected with the output of NAND gate IC1, the resistance R16 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C8 that negative pole is connected with the negative input of NAND gate IC3, and one end ground connection after polar capacitor C7, the resistance R17 that the other end is connected with the negative input of NAND gate IC2 forms.
The electrode input end of described NAND gate IC1 is connected with the negative input of power amplifier P, and its output is connected with the electrode input end of NAND gate IC2.
Meanwhile, the electrode input end of NAND gate IC3 is connected with the output of power amplifier P, and its output is then connected with the positive pole of polar capacitor C11.
The N pole of diode D1 is connected with one end of resistance R1, and forms an output of the present invention; The other end of resistance R4 is then connected with the negative pole of DC power supply S, and forms an input of the present invention.
The battery protection circuit that will calibrate or test only is needed to be connected with input with output during use.When two termination external loading of battery protection circuit; then discharged by the present invention; now electronic switch K disconnects; the electric current flowed out from DC power supply S forms two loops after diode D1; wherein DC power supply S is flowed back in a road after passive π type filter circuit and the asymmetric circuit of emitter-base bandgap grading manifold type, and flows back to DC power supply S after another Lu Zejing battery protection circuit and external loading.When the two ends external power supply of this battery protection circuit; then the present invention is charged; namely now electronic switch K closes; diode D1 short circuit; because the voltage of DC power supply S is much smaller than external power supply; therefore the electric current of external power supply is after battery protection circuit and output of the present invention, then flows out from the input of battery protection circuit through passive π type filter circuit and the asymmetric circuit of emitter-base bandgap grading manifold type, thus realizes the function of bipolar power supply.
As mentioned above, just the present invention can be realized preferably.
Claims (7)
1. a linear buffer drive-type asymmetric double polarity logic amplifies supply unit, by DC power supply S, P pole is connected with the positive pole of DC power supply S, N pole forms the diode D1 in loop after load resistance with the negative pole of DC power supply S, and the electronic switch K to be in parallel with diode D1, passive π type filter circuit is serially connected with between the N pole and the negative pole of DC power supply S of diode D1, and the emitter-base bandgap grading manifold type asymmetric circuit to be connected with passive π type filter circuit, the beam excitation formula logic amplifying circuit be serially connected between the asymmetric circuit of emitter-base bandgap grading manifold type and DC power supply S forms, it is characterized in that, between the negative pole and beam excitation formula logic amplifying circuit of DC power supply S, be also serially connected with three linear buffer drive circuits, described three linear buffer drive circuits are by integrated package U1, field effect transistor MOS, triode Q4, triode Q5, negative pole is connected with the collector electrode of triode Q5, positive pole is in turn through resistance R22, polar capacitor C12, the polar capacitor C10 be connected with the source electrode of field effect transistor MOS after resistance R20, positive pole is connected with the emitter of triode Q5 after resistance R24, the polar capacitor C9 that negative pole is connected with the CS pin of integrated package U1, positive pole is connected with the DIM pin of integrated package U1 after inductance L 2, the polar capacitor C11 that negative pole is connected with the HYS pin of integrated package U1 after resistance R23, one end is connected with the tie point of polar capacitor C12 with resistance R22, the resistance R21 that the other end is connected with the base stage of triode Q5 after inductance L 1, positive pole is connected with the collector electrode of triode Q4, the polar capacitor C13 that negative pole is connected with the LIM pin of integrated package U1 after resistance R19, P pole ground connection, the diode D4 that N pole is connected with the drain electrode of field effect transistor MOS, and one end is connected with the base stage of triode Q4, the resistance R18 that the other end is connected with the SNS pin of integrated package U1 forms, the HG pin of described integrated package U1 is connected with the grid of field effect transistor MOS, its GND pin ground connection, and its IN pin is connected with the tie point of inductance L 1 with resistance R21, the positive pole of described polar capacitor C11 is connected with beam excitation formula logic amplifying circuit, the described emitter of triode Q4 is connected with the negative pole of DC power supply S.
2. a kind of three linear buffer drive-type asymmetric double polarity logics according to claim 1 amplify supply unit, it is characterized in that, described beam excitation formula logic amplifying circuit, primarily of power amplifier P, NAND gate IC1, NAND gate IC2, NAND gate IC3, negative pole is connected with the electrode input end of power amplifier P, the polar capacitor C6 of positive pole ground connection after optical diode D2, one end is connected with the positive pole of polar capacitor C6, the resistance R13 of other end ground connection after diode D3, positive pole is connected with the tie point of diode D3 with resistance R13, the polar capacitor C7 of minus earth, one end is connected with the negative input of NAND gate IC1, the resistance R14 that the other end is connected with the electrode input end of power amplifier P, be serially connected in the resistance R15 between the negative input of power amplifier P and output, one end is connected with the output of NAND gate IC1, the resistance R16 that the other end is connected with the negative input of NAND gate IC3, positive pole is connected with the output of NAND gate IC2, the electric capacity C8 that negative pole is connected with the negative input of NAND gate IC3, and one end ground connection after polar capacitor C7, the resistance R17 that the other end is connected with the negative input of NAND gate IC2 forms, the electrode input end of described NAND gate IC1 is connected with the negative input of power amplifier P, and its output is connected with the electrode input end of NAND gate IC2, the electrode input end of NAND gate IC3 is connected with the output of power amplifier P, and its output is then connected with the positive pole of polar capacitor C11, the electrode input end of described power amplifier P is connected with emitter-base bandgap grading manifold type asymmetric circuit item.
3. a kind of three linear buffer drive-type asymmetric double polarity logics according to claim 2 amplify supply unit, it is characterized in that, described passive π type filter circuit is low-pass filter circuit, it is by electric capacity C1, electric capacity C2, and the resistance R5 be serially connected between the positive pole of electric capacity C1 and the positive pole of electric capacity C2 forms; Be connected with the negative pole of DC power supply S after the negative pole of described electric capacity C1 and the negative pole of electric capacity C2 are connected in series; The positive pole of electric capacity C1 is then connected with the N pole of diode D1.
4. a kind of three linear buffer drive-type asymmetric double polarity logics according to claim 3 amplify supply unit, it is characterized in that, described emitter-base bandgap grading manifold type Asymmetric Electric route triode Q1, triode Q2, triode Q3, be serially connected in the first-level filtering wave circuit between the emitter of triode Q2 and the base stage of triode Q3, be serially connected in the resistance R6 between the collector electrode of triode Q3 and the collector electrode of diode Q2, be serially connected in the resistance R12 between the collector electrode of triode Q1 and the collector electrode of triode Q2, be serially connected in the secondary filter circuit between the emitter of triode Q1 and the negative pole of electric capacity C2, be serially connected in three grades of filters between the base stage of triode Q1 and the negative pole of electric capacity C2, and the resistance R10 be serially connected between the base stage of triode Q1 and the negative pole of electric capacity C2 and the resistance R7 be serially connected between the base stage of triode Q3 and the negative pole of electric capacity C2 forms, the base stage of described triode Q2 is connected with the collector electrode of triode Q1, and its collector electrode is connected with the positive pole of electric capacity C2, the emitter of described triode Q2 and the equal ground connection of emitter of triode Q3.
5. the one three linear buffer drive-type asymmetric double polarity logic according to any one of Claims 1 to 4 amplifies supply unit, it is characterized in that: described load resistance is connected in series by resistance R1, resistance R2, resistance R3 and resistance R4 that resistance is identical and forms.
6. a kind of three linear buffer drive-type asymmetric double polarity logics according to claim 5 amplify supply unit, and it is characterized in that, described first-level filtering wave circuit, secondary filter circuit and three grades of filter circuits are RC filter circuit.
7. one three linear buffer drive-type asymmetric double polarity logic according to claims 1 to 6 amplifies supply unit, it is characterized in that, described integrated package U1 employing model is the driving integrated package of LM3401.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510317380.6A CN104967297A (en) | 2014-11-25 | 2015-06-11 | Trilinear buffer driving type asymmetric bipolar logic amplification power supply device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410687623.0A CN104467694A (en) | 2014-11-25 | 2014-11-25 | Emitter coupling type asymmetric bipolar logic amplifier power supply device |
| CN2014106876230 | 2014-11-25 | ||
| CN201510317380.6A CN104967297A (en) | 2014-11-25 | 2015-06-11 | Trilinear buffer driving type asymmetric bipolar logic amplification power supply device |
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| CN104967297A true CN104967297A (en) | 2015-10-07 |
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| CN201410687623.0A Pending CN104467694A (en) | 2014-11-25 | 2014-11-25 | Emitter coupling type asymmetric bipolar logic amplifier power supply device |
| CN201510317380.6A Withdrawn CN104967297A (en) | 2014-11-25 | 2015-06-11 | Trilinear buffer driving type asymmetric bipolar logic amplification power supply device |
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| CN201410687623.0A Pending CN104467694A (en) | 2014-11-25 | 2014-11-25 | Emitter coupling type asymmetric bipolar logic amplifier power supply device |
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