CN104966711A - Chip device and manufacturing method thereof - Google Patents
Chip device and manufacturing method thereof Download PDFInfo
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- CN104966711A CN104966711A CN201510388846.1A CN201510388846A CN104966711A CN 104966711 A CN104966711 A CN 104966711A CN 201510388846 A CN201510388846 A CN 201510388846A CN 104966711 A CN104966711 A CN 104966711A
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- chip
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- signal transmission
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- electric conducting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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Abstract
The invention provides a chip device and a manufacturing method thereof, which solve the problems that in the prior art, the signal loss between a chip and a circuit board is large, and in the manufacturing process, the equipment cost is high, and the quality control risk is large. The chip device includes a substrate, a chip, and at least one signal transmission port, the substrate includes a first surface and a second surface opposite to the first surface, the first surface includes a chip area and a non-chip area, the chip area is provided with the chip and the at least one signal transmission port electrically connected with the chip, the non-chip area includes at least one through hole, conductive materials are arranged on the first surface and in the at least one through hole, and the at least one signal transmission port is in electrical connection with the second surface through the conductive materials on the first surface and in the at least one through hole.
Description
Technical field
The present invention relates to technical field of semiconductor device preparation, particularly a kind of chip apparatus and preparation method thereof.
Background technology
Semiconductor chip for carrying out the semiconductor device that can realize certain function made by etch, wiring on semiconductor sheet material.Semiconductor chip needs to be encapsulated in a chip apparatus in use, and is connected with a circuit board by this chip apparatus, to complete specific function.Such as, when being encapsulated in the semiconductor chip in a chip apparatus and possessing bio-identification function (as fingerprint recognition, face resemble identification, iris recognition etc.), this semiconductor chip needs, by chip apparatus, identified physiological characteristic information is passed to circuit board, to complete the functions such as follow-up authentication.
The schematic diagram of a kind of chip apparatus that Fig. 1 provides for prior art.As shown in Figure 1, this chip apparatus comprises: the metallic support 11 being provided with through hole, the bonding wire 14 that sapphire cover plate 12 in metallic support through hole, fingerprint recognition chip 13 are electrically connected with fingerprint recognition chip 13, be filled in capsulation material 15 between metallic support 11 and fingerprint recognition chip 13, and by circuit board 16 that bonding wire 14 is electrically connected with fingerprint recognition chip 13; Wherein, circuit board 16 is electrically connected with metallic support 11.As can be seen here, be realize being electrically connected by the bonding wire 14 of plastic packaging in capsulation material 15 between fingerprint recognition chip 13 with circuit board 16.But long by the signal transmission length of bonding wire realization electrical connection like this, the signal that fingerprint recognition chip 13 transmits can have larger loss in the process transmitted, and this can reduce the fingerprint recognition sensitivity of whole device.
Prior art also provides a kind of chip apparatus, by preparing through hole on chip, and utilizes the electric conducting material prepared in through-holes to realize the electrical connection between chip and circuit board.Although the signal transmission length between chip and circuit board can be reduced like this, reduce the loss of signal; But prepare through hole and can reduce the final mechanical performance and the electrical performance that form product on chip, the function that even likely can have influence on chip itself is run, and the equipment cost of the course of processing is high, quality control has a big risk.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of chip apparatus and preparation method thereof, solves the loss of signal between prior art chips and circuit board large, and the problem that the equipment cost of the course of processing is high, quality control has a big risk.
A kind of chip apparatus that the embodiment of the present invention provides, comprising:
Substrate, chip and at least one signal transmission port; The second surface that described substrate comprises first surface and is oppositely arranged with described first surface;
Described first surface comprises chip area and non-chip area; At least one signal transmission port that described chip area is provided with chip and connects with described chip electrical; Described non-chip area comprises at least one through hole;
Prepare on described first surface and at least one through hole described and have electric conducting material; At least one signal transmission port described is formed with described second surface by the electric conducting material on described first surface and at least one through hole described and is electrically connected.
Wherein, described substrate is semiconductor substrate, described chip and described substrate integration system standby.
Wherein, described chip area is surrounded by described non-chip area at least partly.
Wherein, on the sidewall of at least one through hole described, preparation has insulating barrier, and in the hole that described insulating barrier is formed, preparation has electric conducting material.
Wherein, described electric conducting material is filled up in the hole that described insulating barrier is formed; Or,
Electric conducting material in the hole that described insulating barrier is formed is the conductive layer prepared at described surface of insulating layer.
Wherein, between the electric conducting material in the hole that formed of described insulating barrier and described insulating barrier, preparation has barrier layer and/or Seed Layer successively.
Wherein, described conductive layer surface preparation has anti-oxidation metal conducting layer.
Wherein, insulating material or electric conducting material is filled with further in the hole that described conductive layer is formed.
Wherein, the shape of at least one through hole described comprises: vertical through hole or oblique cone through hole up and down.
Wherein, comprise further: at least one conductive projection and the circuit board being provided with at least one electrical port;
Electric conducting material at least one through hole described to be formed with at least one electrical port described respectively by least one conductive projection described and is electrically connected.
Wherein, the position of at least one through hole described and/or at least one conductive projection is arranged according to the position correspondence of at least one electrical port on described circuit board.
Wherein, the gap filling between described second surface and described circuit board has insulating material.
Wherein, comprise further: static release device and/or touch induction device; Described static release device is electrically connected with described circuit board; Described touch induction device and described chip electrical connect.
Wherein, described static release device and described touch induction device are integrated into a quoit, and described quoit is fixed on described circuit board, the described substrate of encirclement in whole or in part of described quoit.
Wherein, comprise further: tack coat and cover sheet; Described tack coat is prepared on described first surface; Described tie layer surface preparation has described cover sheet.
Wherein, the Mohs' hardness scope of described cover sheet is 5H-10H; And/or,
The dielectric constant of described cover sheet under 1MHz test frequency is greater than 4.
Wherein, the material of described cover sheet comprises the one in following material: nano material, lipid materials, sapphire, glass material or ceramic material.
Wherein, described lipid materials comprises one or more in following compound: epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyurethane, polyurethane.
Wherein, comprise further: hardened layer, described hardened layer is prepared in above described first surface.
Wherein, described chip is biological identification chip.
Embodiments provide a kind of preparation method of chip apparatus, comprising:
Prepare substrate, chip and at least one signal transmission port; The second surface that described substrate comprises first surface and is oppositely arranged with described first surface; Wherein, described first surface comprises chip area and non-chip area; At least one signal transmission port that described chip area is provided with chip and connects with described chip electrical;
At described non-chip area, for the preparation of at least one through hole be electrically connected between at least one signal transmission port with described second surface described in formation, and the electric conducting material on described first surface and at least one through hole.
Wherein, batch prepares described chip apparatus; Then described method comprises:
Prepare a semiconductor crystal wafer; Described semiconductor crystal wafer comprises at least one break area, the substrate of the corresponding described chip apparatus of each described break area; The first surface step of described substrate comprises chip area and non-chip area; At least one signal transmission port that described chip area is provided with chip and connects with described chip electrical;
At each non-chip area, for the preparation of at least one through hole be electrically connected between at least one signal transmission port with described second surface described in formation, and the electric conducting material on described first surface and at least one through hole described;
Described semiconductor crystal wafer is cut at least one chip apparatus according at least one break area described.
Wherein, for the preparation of at least one through hole be electrically connected between at least one signal transmission port with described second surface described in formation, and the electric conducting material on described first surface and at least one through hole described, comprising:
At least one blind hole is prepared at described non-chip area;
Insulating barrier is prepared in described first surface and at least one blind hole described;
Etch described insulating barrier to expose at least one signal transmission port described;
Electric conducting material is prepared at described insulating barrier and at least one signal transmission port surface described;
Thinning described second surface forms at least one through hole to get through at least one blind hole described.
Wherein, prepare electric conducting material at described insulating barrier and at least one signal transmission port surface described, comprising:
Deposits conductive material is until fill the hole that described insulating barrier formed; Or,
Deposits conductive material is until form one deck conductive layer at described surface of insulating layer.
Wherein, before described insulating barrier and at least one signal transmission port surface described prepare electric conducting material, comprise further:
Barrier layer and Seed Layer is prepared successively at described insulating barrier and at least one signal transmission port surface described.
Wherein, comprise further:
Fill insulant or electric conducting material in the hole that described conductive layer is formed.
Wherein, comprise further:
On described second surface, conductive projection is prepared in the position of corresponding at least one through hole described, to form the electrical connection at least one through hole described between electric conducting material and described conductive projection;
At least one conductive projection described is connected with at least one electrical port of a circuit board.
Wherein, comprise further:
Corresponding at least one electrical port described prepares at least one conductive projection with a circuit board;
Form the electrical connection between electric conducting material and at least one conductive projection described at least one through hole described.
Wherein, comprise further:
Fill insulant in gap between described second surface and described circuit board.
Wherein, comprise further: a static release device is set and is electrically connected with described circuit board; And/or,
A touch induction device is set and described chip electrical connects.
Wherein, comprise further:
One deck tack coat is prepared at described first surface;
One deck cover sheet is prepared in described tie layer surface.
Wherein, adopt gluing process on the first surface of one single chip device, prepare described tack coat; Or,
Coating technique is adopted to prepare described tack coat on the first surface of wafer.
Wherein, one deck hardened layer is prepared by side on the first surface.
Wherein, the one in following technique is adopted to prepare described hardened layer: physical gas-phase deposition, atom layer deposition process, spraying coating process or coating technique.
A kind of chip apparatus that the embodiment of the present invention provides and preparation method thereof, the first surface of institute's employing substrate divides in order to chip area and non-chip area.Chip area is for the preparation of chip and signal transmission port, and non-chip area is for the preparation of forming the through hole be electrically connected between chip and circuit board.The signal transmission port of such chip directly can form the electrical connection between circuit board by the through hole of non-chip area, and the Signal transmissions length that this electrical connection realizes is short, and thus messenger transmission loss is little; Meanwhile, prepare through hole at non-chip area, the function that can not have influence on chip itself is run, and also can not have influence on the final mechanical performance and the electrical performance that form product, difficulty of processing reduces greatly, and thus course of processing equipment cost is low, quality control risk is little.
Accompanying drawing explanation
The schematic diagram of a kind of chip apparatus that Fig. 1 provides for prior art.
Fig. 2 is the structural representation of the chip apparatus that one embodiment of the invention provides.
Fig. 3 is the structural representation of the chip apparatus that one embodiment of the invention provides.
Fig. 4 is the structural representation of the chip apparatus that another embodiment of the present invention provides.
Fig. 5 is preparation method's flow chart of a kind of chip apparatus that the embodiment of the present invention provides.
Fig. 6 is the structural representation of substrate in the preparation method of a kind of chip apparatus that the embodiment of the present invention provides.
Fig. 7 is the flow chart preparing electric conducting material at least one through hole and at least one through hole in the preparation method of a kind of chip apparatus that the embodiment of the present invention provides.
Fig. 8 a ~ 8g is the decomposition principle schematic diagram of the preparation method of a kind of chip apparatus that the embodiment of the present invention provides.
Fig. 9 is preparation method's flow chart that another kind that the embodiment of the present invention provides prepares chip apparatus.
Figure 10 is that the another kind that the embodiment of the present invention provides prepares the crystal circle structure schematic diagram used in the preparation method of chip apparatus.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
To it will be understood by those skilled in the art that in the embodiment of the present invention involved some architectural feature determiners (such as " first surface " and " second surface ") only for clear and definite relative position relation in a particular embodiment.The literal meaning of these architectural feature determiners can not be used for limiting other architectural features of the present invention.
Fig. 2 is the structural representation of the chip apparatus that one embodiment of the invention provides.As shown in Figure 2: this chip apparatus comprises: substrate 21, chip 215 and at least one signal transmission port 216; The second surface 212 that substrate 21 comprises first surface 211 and is oppositely arranged with first surface 211.In the embodiment shown in Figure 2, first surface 211 refers to the upper surface of substrate 21, and second surface 212 refers to the lower surface of substrate 21.
First surface 211 comprises chip area 213 and non-chip area 214.At least one signal transmission port 216 that chip area 213 is provided with chip 215 and is electrically connected with chip 215.In an embodiment of the present invention, this at least one signal transmission port 216 is that integration is prepared on chip 215.
It will be understood by those skilled in the art that chip 215 can be a part for substrate 21, and now chip 215 can directly be prepared on the first surface of substrate when substrate 21 itself adopts semi-conducting material.But chip 215 also can be encapsulated in the third-party chip below substrate 21 first surface chip area.The present invention does not limit the set-up mode of chip 215 in substrate 21.
Those skilled in the art are still appreciated that, chip 215 can be a kind of bio-identification chip (such as, possess fingerprint recognition, face resemble identification and the bio-identification function such as iris recognition) or behavioural characteristic identification chip is (such as, possess the behavioural characteristic recognition functions such as person's handwriting, sound and gait), by the physiological characteristic information collected or behavior characteristic information being passed to circuit board 22 with the electrical connection of circuit board 22, circuit board 22 carries out process to this physiological characteristic information or behavior characteristic information and can carry out authentication fast and accurately or complete other functions.The present invention does not limit the model of chip 215, concrete structure and the concrete function that realizes.
Non-chip area 214 comprises at least one through hole 217, does not comprise any MOS device for constructing chip 215.In an embodiment of the present invention, the shape of at least one through hole 217 can be upper and lower vertical through hole or oblique cone through hole, and the shape of the present invention to through hole 217 does not limit.
Have electric conducting material owing to preparing on first surface 211 and at least one through hole 217, therefore at least one signal transmission port 216 is electrically connected by first surface 211 is formed with second surface 212 with the electric conducting material at least one through hole 217.Specifically, in the actual fabrication process of one embodiment of the invention, the electric conducting material on first surface 211 and at least one through hole 217 is formed by deposition process integration.Now, at least one signal transmission port 216 can form the electrical connection with the electric conducting material at least one through hole 217 by the conductive material layer on first surface 211, and forms the electrical connection with second surface 212 further by the electric conducting material at least one through hole 217.But it will be understood by those skilled in the art that at least one signal transmission port 216 and the electric conducting material at least one through hole 217 also can be formed by other means and be electrically connected, the present invention does not limit this.
In an embodiment of the present invention, on the sidewall of at least one through hole 217, preparation has insulating barrier 2171.In the hole that insulating barrier 2171 is formed, preparation has electric conducting material.Now, at least one signal transmission port 216 is the electrical connection formed by electric conducting material and the second surface 212 of preparation at least one through hole 217 in fact.
In an embodiment of the present invention, as shown in Figure 2, at least one through hole 217, in the hole that insulating barrier 2171 is formed, electric conducting material 2172 is filled with.
In an alternative embodiment of the invention, as shown in Figure 3, electric conducting material at least one through hole 217 also can be hollow, and now insulating barrier 2171 surface only needs to prepare one deck conductive layer 2173, and also preparing on conductive layer 2173 surface has anti-oxidation metal conducting layer (such as layer gold).In one embodiment, in order to ensure reliability and the mechanical performance of whole chip apparatus, in the hole that conductive layer 2173 is formed, also packing material 2174 can be prepared.This packing material 2174 can be insulating material or electric conducting material, and the material of the present invention to packing material 2174 does not limit.
In an embodiment of the present invention, between the electric conducting material in the hole that insulating barrier 2171 and insulating barrier 2171 are formed, (electric conducting material 2172 or conductive layer 2173) also can be prepared successively barrier layer and Seed Layer, or only preparation has barrier layer or Seed Layer.Now electric conducting material 2172 is be filled with the hole that Seed Layer formed in fact, and conductive layer 2173 is be prepared in Seed Layer surface in fact.Barrier layer can prevent the electric conducting material of follow-up preparation from forming diffusion to substrate 21, and Seed Layer can improve the electroplating quality of prepared electric conducting material.Due to the thinner thickness of this barrier layer and Seed Layer, therefore do not mark in the drawings.
In an embodiment of the present invention, insulating barrier 2171 can be made up of insulating material, and barrier layer can be titanium coating, and Seed Layer can adopt and the follow-up material identical at the electric conducting material of Seed Layer surface deposition.Such as, when the follow-up electric conducting material at Seed Layer surface deposition is copper, Seed Layer also can corresponding employing layers of copper.Because the material of insulating barrier, barrier layer and Seed Layer can be decided according to the actual requirements, the present invention does not limit this.
So as shown in Figure 2, when the circuit board 22 that this chip apparatus need comprise at least one electrical port 221 with formed be electrically connected time, the electric conducting material at least one through hole 217 can be formed respectively by the electrical port 221 of a conductive projection 218 and at least one and be electrically connected.This at least one conductive projection 218 first can be prepared in the electric conducting material bottom at least one through hole 217, and then forms the electrical connection of this at least one conductive projection 218 and at least one electrical port 221; Also can be directly previously prepared at least one electrical port 221 of circuit board 22.Signal transmission port 216 due to chip 215 can directly be formed by the through hole 217 of non-chip area 212 and electrical connection on circuit board 22 between electrical port 221, and the Signal transmissions length that this electrical connection realizes is shorter, and thus signal transmission loss is little.Simultaneously, prepare through hole 217 at non-chip area 212, the function that can not have influence on chip 215 itself is run, and also can not have influence on the final mechanical performance and the electrical performance that form product, difficulty of processing reduces greatly, and thus course of processing equipment cost is low, quality control risk is little.
In an embodiment of the present invention, in order to strengthen further this chip apparatus be electrically connected with circuit board 22 after mechanical performance, can between second surface 212 and circuit board 22 fill insulant.
In an embodiment of the present invention, the technique that reroutes caused in order to avoid location dislocation between through hole 217 and conductive projection 218, and conductive projection 218 and electrically location dislocation and the technique that reroutes that causes between port 221; The position of this at least one through hole 217 and at least one conductive projection 218 can correspondingly according to the position of at least one electrical port 221 on circuit board 22 be arranged.When being electrically connected between formation signal transmission port 216 with electrical port 221 like this, directly in vertical direction this at least one through hole 217, at least one conductive projection 218 and at least one electrical port 221 are coupled together, without any need for the technique that reroutes, reduce further preparation cost.
It will be appreciated by those skilled in the art that, the quantity of signal transmission port 216 can be determined by the concrete structure of chip 215, the quantity of through hole 217 and conductive projection 218 can correspondingly according to the quantity of signal transmission port 216 be arranged, and the quantity of conductive projection 218 also can be arranged according to the quantity correspondence of the electrical port 221 on circuit board 22.The quantity of the present invention to signal transmission port 216, through hole 217 and conductive projection 218 does not all limit.
Those skilled in the art are still appreciated that the division for chip area 213 and non-chip area 214 on first surface 211 can be determined according to the concrete structure of chip 215.Such as, in an embodiment of the present invention, it is inner that chip area 213 partly can be enclosed in non-chip area 214, and so no matter the chip 215 in chip area 213 will realize the electrical connection of which horizontal direction, only need prepare through hole in the relevant position of non-chip area 214.The present invention does not limit the dividing mode of chip area 213 and non-chip area 214 on first surface 211.
In an embodiment of the present invention, this chip apparatus also can comprise further: static release device and touch induction device.This static release device is electrically connected with circuit board 22, by with circuit board 22 in electrical contact come the electrostatic that produces in signals transmission of release circuit plate 22.Touch induction device is electrically connected with chip 215, and for the touch of perception staff, notice chip 215 starts to identify staff touch signal.
Fig. 4 is the structural representation of the chip apparatus that another embodiment of the present invention provides.As shown in Figure 4, different from the chip apparatus shown in Fig. 2 or Fig. 3, this chip apparatus comprises further: quoit 23, tack coat 24, cover sheet 25 and hardened layer 26.
Quoit 23 is for being integrated with the integrated apparatus of above-mentioned static release device function and touch induction device function.Quoit 23 is fixed on circuit board 22, like this when the hand contacting metal circle 23 of user, by the electric connection release electrostatic of quoit 23 with circuit board 22, can not cause the surge to chip 215 simultaneously.Simultaneously, the substrate of encirclement in whole or in part 21 of quoit 23 (such as, can be only have the top of Metal Ball 23 to surround substrate 21), will contact with quoit 23 when staff attempts the induction zone touching chip 215 like this, with the electric connection of chip 215, quoit 23 is by notifying that chip 215 starts to identify staff touch signal.
Tack coat 24 is prepared on first surface 211, and cover sheet 25 is prepared in tack coat 24 surface, and cover sheet 25 is for protecting the damage of larger external force to chip 215.Hardened layer 26 is prepared in cover sheet 25 surface, and hardened layer 26 affects attractive in appearance for avoiding because cover sheet 25 is scratched.The material of cover sheet 25 can comprise the one in following material: nano material, lipid materials, sapphire, glass material or ceramic material.Lipid materials wherein can comprise one or more in following compound: epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyurethane, polyurethane.
In an embodiment of the present invention, in order to ensure the mechanical performance of formed final products, the Mohs' hardness scope of cover sheet 25 is 5H-10H.When chip 215 is the bio-identification chip identifying fingerprint, the image fed back to make fingerprint is more clear, and the dielectric constant of cover sheet 25 under 1MHz test frequency is greater than 4.
In an alternative embodiment of the invention; in order to reduce preparation cost, Simplified flowsheet further; under the prerequisite that the mechanical strength of made chip apparatus allows, also directly can prepare hardened layer 26 on first surface 211, and tack coat 24 and cover sheet 25 need not be prepared.
Fig. 5 is preparation method's flow chart of a kind of chip apparatus that the embodiment of the present invention provides.As shown in Figure 5, the preparation method of this chip apparatus comprises:
Step 501: as shown in Figure 6, prepares substrate 21, chip 215 and at least one signal transmission port 216; The second surface 212 that substrate 21 comprises first surface 211 and is oppositely arranged with first surface 211; Wherein, first surface 211 comprises chip area 213 and non-chip area 214; At least one signal transmission port 216 that chip area 213 is provided with chip 215 and is electrically connected with chip 215.As can be seen here, prepared substrate 21 divides chip area 213 and non-chip area 214, and prepared in chip area 213 and complete chip 215 and at least one signal transmission port 216.
Step 502: at non-chip area 214, for the preparation of forming at least one through hole 217 of be electrically connected between at least one signal transmission port 216 with second surface 212, and on first surface 211 with the electric conducting material at least one through hole 217.
Step 503: when this chip apparatus needs to use, second surface 212 is formed the electrical connection of electric conducting material and at least one conductive projection 218 at least one through hole 217, and this conductive projection 218 is formed with the electrical port 221 of circuit board 22 further and is electrically connected.
In an embodiment of the present invention, this at least one conductive projection 218 can correspondingly in advance be prepared at least one electrical port 221 of a circuit board 22, and the electrical connection forming at least one through hole 217 and at least one conductive projection 218 so directly can realize the electrical connection of chip 215 and circuit board 22.
In an alternative embodiment of the invention, also can be that conductive projection 218 is prepared, to form the electrical connection at least one through hole 217 between electric conducting material and conductive projection 218 in the position of first at least one through hole 217 corresponding on second surface 212; Now, then also need this at least one conductive projection 218 to be connected with at least one electrical port 221 of a circuit board the electrical connection that could realize chip 215 and this circuit board 22.
In an embodiment of the present invention, in order to ensure the mechanical performance finally forming product, also can fill insulant in the gap between second surface 212 and circuit board 22.
In an embodiment of the present invention, in order to the electrostatic that release circuit plate 22 produces in signals transmission, a static release device also can be set and be electrically connected with circuit board 22, with release electrostatic; Meanwhile, a touch induction device also can be set and be electrically connected with chip 215, identify touch signal with the notice chip 215 when perceiving staff and touching.
In an embodiment of the present invention, in order to protect the damage of larger external force to chip 215, also can prepare one deck tack coat 24 at first surface, then preparing one deck cover sheet 25 on tack coat 24 surface.
In an embodiment of the present invention, in order to avoid affecting attractive in appearance because cover sheet 25 surface is scratched, also one deck hardened layer 26 can just be prepared on the first surface.This hardened layer 26 can be located immediately on first surface, now also can not need tack coat 24 and cover sheet 25; Or this hardened layer 26 also can be prepared on cover sheet 25.In one embodiment, the one in following technique can be adopted to prepare this hardened layer 26: physical gas-phase deposition, atom layer deposition process or coating technique.
Fig. 7 is the flow chart preparing electric conducting material at least one through hole and at least one through hole in the preparation method of a kind of chip apparatus that the embodiment of the present invention provides.As shown in Figure 7, the preparation process of the electric conducting material at least one through hole 217 and at least one through hole 217 can comprise the steps:
Step 5021: as shown in Figure 8 a, prepares at least one blind hole 219 at non-chip area 214.At least one prepared blind hole 219 is for finally forming at least one through hole 217.
Step 5022: as shown in Figure 8 b, prepares insulating barrier 2171 in first surface 211 and at least one blind hole 219.
Step 5023: as shown in Figure 8 c, etches this insulating barrier 2171 to expose at least one signal transmission port 216.Detailed process can be on position corresponding with signal transmission port 216 on this insulating barrier 2171 and etches, and exposes signal transmission port 216.
Step 5024: prepare electric conducting material at insulating barrier 2171 and at least one signal transmission port 216 surface.The electric conducting material that insulating barrier 2171 surface deposits is for the formation of the electric connection between signal transmission port 216 and second surface 212.
In an embodiment of the present invention, need to fill up electric conducting material 2172, as shown in figure 8d in the hole that insulating barrier 2171 is formed.Deposits conductive material is so then needed directly completely to fill the hole that formed of insulating barrier 2171.
In an alternative embodiment of the invention, only one deck conductive layer 2173 need be prepared on insulating barrier 2171 surface, as figure 8 e shows.So only need deposits conductive material until form one deck conductive layer 2173 on insulating barrier 2171 surface.In one embodiment, in order to ensure reliability and the mechanical performance of whole chip apparatus, also need to prepare packing material 2174 in the hole formed at conductive layer 2173, as illustrated in fig. 8f.This packing material 2174 can be insulating material or electric conducting material.Follow-up preparation process is set forth for the structure shown in Fig. 8 f.
In an embodiment of the present invention, before insulating barrier 2171 and at least one signal transmission port 216 surface prepare electric conducting material, also first can prepare barrier layer and Seed Layer successively on insulating barrier 2171 surface, and then prepare electric conducting material on Seed Layer surface.Now, this electric conducting material prepared can fill the hole that Seed Layer is formed, or is only one deck conductive layer on Seed Layer surface.
In an alternative embodiment of the invention, in order to meet the concrete function needs of chip 215 (such as when chip 215 is for biological identification chip, just need the induction zone of chip 215 to come out), also need etch further at the chip area 213 on this chip apparatus surface, the barrier layer on the position of corresponding chip 215, Seed Layer and electric conducting material are etched away with exposed chip 215.But the present invention does not limit the need of this further etch step.
Step 5025: as illustrated in fig.8g, thinning second surface 212 forms at least one through hole 217 to get through at least one blind hole 219.Now, the electric conducting material had for the formation of being electrically connected between signal transmission port 216 and second surface 212 has been prepared in this at least one through hole 217.
The chip apparatus of formation like this in use, as shown in Figure 3, second surface 212 is formed the electrical connection of electric conducting material and at least one conductive projection 218 at least one through hole 217, and this conductive projection 218 is formed with the electrical port 221 of circuit board 22 further and is electrically connected.
Fig. 9 is preparation method's flow chart that another kind that the embodiment of the present invention provides prepares chip apparatus.Utilize the method shown in Fig. 9 can prepare this chip apparatus in batches, as shown in Figure 9, this preparation method specifically comprises:
Step 901: as shown in Figure 10, prepares a semiconductor crystal wafer 81; Semiconductor crystal wafer 81 comprises at least one break area 82, the substrate of the corresponding chip apparatus of each break area 82; And the first surface of this substrate step comprises chip area 213 and non-chip area 214, at least one signal transmission port that chip area is provided with chip and connects with chip electrical.That is, divided chip area 213 and non-chip area 214 in advance in each break area 82, and prepared in chip area 213 and complete chip and at least one signal transmission port.
This area is that technical staff is appreciated that, the mode that a wafer 81 divides break area 82 can be determined according to the size of substrate corresponding to break area 82, wafer such as shown in Figure 10 comprises 4 onesize break area 82, has completed chip and at least one signal transmission port in each break area 82.The present invention does not limit the mode dividing break area 82 on a wafer 81.
Step 902: at each non-chip area, for the preparation of forming at least one through hole be electrically connected between at least one signal transmission port with second surface, and the electric conducting material on first surface and at least one through hole.Now, each break area chip apparatus that correspondence one is complete.
Step 903: semiconductor crystal wafer is cut at least one chip apparatus according at least one break area.Just achieve the batch preparation of chip apparatus thus, further increase preparation efficiency, reduce preparation cost.
It will be appreciated by those skilled in the art that; prepare as above conductive projection 218 with formed the electrical connection of chip 215 and circuit board 22, the preparation of static release device, the preparation of touch induction device, the preparation of tack coat 24, the preparation of cover sheet 25 and hardened layer 26 preparation both can carry out on the first surface of one single chip device, also can on wafer the chip apparatus of multiple break area first surface on carry out simultaneously.Such as, gluing process can be adopted on the first surface of one single chip device to prepare tack coat 24, coating technique also can be adopted on the first surface of wafer simultaneously to prepare tack coat 24 for multiple break area.The execution of the present invention to such as above-mentioned preparation process does not limit opportunity.
These are only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a chip apparatus, is characterized in that, comprising: substrate, chip and at least one signal transmission port; The second surface that described substrate comprises first surface and is oppositely arranged with described first surface;
Described first surface comprises chip area and non-chip area; At least one signal transmission port that described chip area is provided with described chip and connects with described chip electrical; Described non-chip area comprises at least one through hole;
Prepare on described first surface and at least one through hole described and have electric conducting material; At least one signal transmission port described is formed with described second surface by the electric conducting material on described first surface and at least one through hole described and is electrically connected.
2. device according to claim 1, is characterized in that, described substrate is semiconductor substrate, described chip and described substrate integration system standby.
3. device according to claim 1, is characterized in that, described chip area is surrounded by described non-chip area at least partly.
4. device according to claim 1, is characterized in that, on the sidewall of at least one through hole described, preparation has insulating barrier, and in the hole that described insulating barrier is formed, preparation has electric conducting material.
5. device according to claim 4, is characterized in that,
Described electric conducting material is filled up in the hole that described insulating barrier is formed; Or,
Electric conducting material in the hole that described insulating barrier is formed is the conductive layer prepared at described surface of insulating layer.
6., according to described device arbitrary in claim 1 to 5, it is characterized in that, described chip is biological identification chip.
7. a preparation method for chip apparatus, is characterized in that, comprising:
Prepare substrate, chip and at least one signal transmission port; The second surface that described substrate comprises first surface and is oppositely arranged with described first surface; Wherein, described first surface comprises chip area and non-chip area; At least one signal transmission port that described chip area is provided with chip and connects with described chip electrical;
At described non-chip area, for the preparation of at least one through hole be electrically connected between at least one signal transmission port with described second surface described in formation, and the electric conducting material on described first surface and at least one through hole described.
8. method according to claim 7, is characterized in that, batch prepares described chip apparatus; Then described method comprises:
Prepare a semiconductor crystal wafer; Described semiconductor crystal wafer comprises at least one break area, the substrate of the corresponding described chip apparatus of each described break area; The first surface step of described substrate comprises chip area and non-chip area; At least one signal transmission port that described chip area is provided with chip and connects with described chip electrical;
At each non-chip area, for the preparation of at least one through hole be electrically connected between at least one signal transmission port with described second surface described in formation, and the electric conducting material on described first surface and at least one through hole described;
Described semiconductor crystal wafer is cut at least one chip apparatus according at least one break area described.
9. the method according to claim 7 or 8, it is characterized in that, for the preparation of at least one through hole be electrically connected between at least one signal transmission port with described second surface described in formation, and the electric conducting material on described first surface and at least one through hole described, comprising:
At least one blind hole is prepared at described non-chip area;
Insulating barrier is prepared in described first surface and at least one blind hole described;
Etch described insulating barrier to expose at least one signal transmission port described;
Electric conducting material is prepared at described insulating barrier and at least one signal transmission port surface described;
Thinning described second surface forms at least one through hole to get through at least one blind hole described.
10. method according to claim 9, is characterized in that, prepares electric conducting material, comprising at described insulating barrier and at least one signal transmission port surface described:
Deposits conductive material is until fill the hole that described insulating barrier formed; Or,
Deposits conductive material is until form one deck conductive layer at described surface of insulating layer.
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| CN201510388846.1A CN104966711A (en) | 2015-06-30 | 2015-06-30 | Chip device and manufacturing method thereof |
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| CN201510388846.1A CN104966711A (en) | 2015-06-30 | 2015-06-30 | Chip device and manufacturing method thereof |
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