CN104966703A - 集成电路封装体及其形成方法 - Google Patents
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Abstract
本发明涉及一种集成电路封装体及其形成方法。根据本发明一实施例的集成电路封装体包括:芯片;芯片座,经配置以承载芯片;信号引脚,设置于芯片座外围且经配置以与芯片电连接;接地引脚,设置于芯片座外围且经配置以接地;绝缘壳体,其遮蔽芯片、芯片座、信号引脚、以及接地引脚;屏蔽金属层,其覆盖在绝缘壳体上方;以及屏蔽导电柱,设置于接地引脚上方并位于绝缘壳体内,屏蔽导电柱的上端经配置以与屏蔽金属层电连接,屏蔽导电柱的下端经配置以与接地引脚电连接。根据本发明实施例的集成电路封装体及其形成方法可以简化制造工艺、降低制造成本。
Description
技术领域
本申请涉及一种集成电路封装体及形成该集成电路封装体的方法。
背景技术
因越来越多的无线通信装置被高度集成在一有限面积的手机中,使得原本较不受重视、且采用低成本的导线框架加工的射频组件如:射频功率放大器(RF Power Amplifier,RF PA)、低噪声功率放大器(Low Noise Amplifier,LNA)、天线开关(Antenna Switch)等面临的电磁场干扰问题也越来越多。
在公开号为CN102479767A的专利申请中,利用先设计好的高低配置好的导线框架将信号(Signal)与地(GND)分开。在这种技术中,信号引脚与导线框架的外缘平齐,而接地引脚内缩于导线框架的外缘内。为了使位于芯片外围的屏蔽金属层能够与接地引脚电连接形成电磁场屏蔽,需要使接地引脚具有高于信号引脚的部分,利用半切(hall-cut)方式切到高于信号引脚的接地引脚(GND引脚)露出后,即停止切割,之后完成金属涂层,如此完成电磁场屏蔽。
在CN102479767A的专利申请中,在将各导线框单元分割时,如果利用一次性切下去的简单的全切(full-cut)方式,除接地引脚外,信号引脚也将露出。那么,在完成金属涂层时,将错误地使信号引脚之间短路,这是不允许的。但是,这种半切的方式相较于全切工艺复杂,不易控制。
因此,现有的具有电磁场屏蔽功能的集成电路封装体及其制作方法仍需进一步改进。
发明内容
本发明的目的之一在于提供集成电路封装体及形成该集成电路封装体的方法,其可以简单的切割工艺获得具有电磁场屏蔽功能的集成电路封装体。
本发明的一实施例提供了一集成电路封装体,其包括:芯片;芯片座,经配置以承载该芯片;信号引脚,设置于该芯片座外围且经配置以与该芯片电连接;接地引脚,设置于该芯片座外围且经配置以接地;绝缘壳体,其遮蔽该芯片、该芯片座、该信号引脚、以及该接地引脚;屏蔽金属层,其覆盖在该绝缘壳体上方;以及屏蔽导电柱,设置于该接地引脚上方并位于该绝缘壳体内,该屏蔽导电柱的上端经配置以与该屏蔽金属层电连接,该屏蔽导电柱的下端经配置以与该接地引脚电连接。
本发明的另一实施例提供了一形成集成电路封装体的方法,其包括:将芯片固定于芯片座上;用引线连接该芯片与信号引脚;注塑而形成绝缘壳体,该绝缘壳体遮蔽该芯片、该芯片座、该信号引脚、该芯片与该信号引脚之间的该引线、及接地引脚;在该绝缘壳体中自上而下形成位于该接地引脚上方的填充孔;在该填充孔中填充导电材料以形成屏蔽导电柱,该屏蔽导电柱的下端经配置以与该接地引脚电连接;以及在该绝缘壳体上方覆盖屏蔽金属层,该屏蔽金属层经配置以与该屏蔽导电柱的上端电连接。
在本发明的集成电路封装体及形成集成电路封装体的方法中,由于在绝缘壳体中自上而下形成将屏蔽金属层与接地引脚互连的屏蔽导电柱,因此,不再像现有技术那样必须在集成电路封装体侧壁也形成金属涂层来与接地引脚互连而进行屏蔽。也就是说,在本发明中,在集成电路封装体侧壁形成金属涂层并不是必须的。因此,在制造过程中将连在一起的多个集成电路封装体进行分割时,可以采用一次性切下去的简单的全切方式。这时,因集成电路封装体侧壁无需形成金属涂层,所以不用担心在全切时是否会切到信号引脚致其裸露而与后续形成屏蔽金属层互连导致信号引脚短路。相应的,本发明具有制造工艺简单,制造成本低的优点。
附图说明
图1是根据本发明一个实施例的集成电路封装体的纵向截面示意图。
图2是图1中的集成电路封装体的横向截面示意图。
图3是根据本发明一个实施例的形成集成电路封装体的方法的流程图。
图4A-图4G是采用图3的方法制作集成电路封装体的过程的示例性示意图。
图5是根据本发明另一个实施例的集成电路封装体的纵向截面示意图。
图6是根据本发明又一个实施例的集成电路封装体的纵向截面示意图。
图7是根据本发明另一个实施例的集成电路封装体的横向截面示意图。
具体实施方式
图1是根据本发明一个实施例的集成电路封装体100的纵向截面示意图。图2是图1中的集成电路封装体100的横向截面示意图。
如图1、图2所示,根据本发明一个实施例的集成电路封装体100包括芯片101、芯片座102、信号引脚207、接地引脚103、绝缘壳体104、屏蔽金属层105、屏蔽导电柱106。芯片座102经配置以承载该芯片101。信号引脚207设置于芯片座102外围且经配置以与芯片101电连接。接地引脚103设置于芯片座102外围且经配置以接地。绝缘壳体104遮蔽芯片101、芯片座102、信号引脚207以及接地引脚103。屏蔽金属层105覆盖在绝缘壳体104上方。屏蔽导电柱106设置于接地引脚103上方并位于绝缘壳体104内,屏蔽导电柱106的上端经配置以与屏蔽金属层105电连接,屏蔽导电柱106的下端经配置以与接地引脚103电连接。由于在绝缘壳体104中自上而下形成互连屏蔽金属层105与接地引脚103的屏蔽导电柱106,因此,不再像现有技术那样必须在集成电路封装体侧壁上也形成金属涂层来互连屏蔽金属层105与接地引脚103而实现屏蔽。也就是说,在本发明中,在集成电路封装体100侧壁形成金属涂层并不是必须的。因此,在制造过程中将连在一起的多个集成电路封装体100进行分割时,可以采用一次性切下去的简单的全切方式。这时,因集成电路封装体100侧壁不必形成金属涂层,所以不用担心在全切时会切到信号引脚207致其裸露而与金属涂层互连而导致信号引脚207短路。相应的,本发明具有制造工艺简单,制造成本低的优点。
如图1所示,在本实施例中,接地引脚103有多个,其上设置有导电凸块108,多个屏蔽导电柱106设置于相应的导电凸块108上。这样,在制作用于形成屏蔽导电柱106的填充孔时,能够防止损坏下方的接地引脚103。在另一实施例中,导电凸块108为多个并布置成在竖直方向上叠加。在这些实施例中,导电凸块108可以是焊球或其它金属球。在其它实施例中,也可不设置导电凸块108而直接在接地引脚103上设置屏蔽导电柱106。
在本实施例中,接地引脚103与屏蔽导电柱106一一对应设置。屏蔽导电柱106的数目与芯片101的频率有关。芯片101的频率越高,需要的屏蔽导电柱106越多。接地引脚103可以包括位于集成电路封装体100的端角处的接地引脚103。端角处的接地引脚103可以经配置以通过引线107或连接部109与芯片座102电连接。接地引脚103还可以包括至少一个位于集成电路封装体100的相邻端角之间的接地引脚103。如图2所示,集成电路封装体100的相邻端角之间的接地引脚103经配置以通过引线107与芯片座102电连接,或者通过引线107与该端角处的接地引脚103连接。如图2所示,在本实施例中,接地引脚103可以与信号引脚207交替布置。
图3是根据本发明一个实施例的形成集成电路封装体100的方法的流程图,其可形成图1、2所示实施例中的集成电路封装体100。图4A-图4G是采用图3的方法制作集成电路封装体100的过程的示例性示意图。
根据图3所示的实施例,在步骤S301中,如图4A所示,待封装的导线框架条上设有若干阵列排列的导线框单元,其中各导线框单元的接地引脚103相互连接在一起。对于每一导线框单元,将芯片101固定于芯片座102上。在步骤S302中,用引线107连接芯片101与信号引脚207。在步骤S303中,如图4C所示,注塑而形成绝缘壳体104,绝缘壳体104遮蔽芯片101、芯片座102、信号引脚207、芯片101与信号引脚207之间的引线107、及接地引脚103。在图步骤S304中,如图4D所示,在绝缘壳体104中自上而下形成位于接地引脚103上方的填充孔410。在步骤S305中,如图4E所示,在填充孔410中填充导电材料以形成屏蔽导电柱106,屏蔽导电柱106的下端经配置以与接地引脚103电连接。例如,在注塑形成绝缘壳体104之前,先在接地引脚103上对应填充孔410位置形成如图4B所示的导电凸块108,譬如使用打线机在形成引线107的同时形成用作导电凸块108的焊球或金属球;然后待形成填充孔410后于填充孔内填充导电材料即可在导电凸块108上方形成屏蔽导电柱106。屏蔽导电柱106的材料可为导电胶或锡膏,屏蔽金属层106例如但不限于通过溅镀形成或直接采用金属板。这样,在切割形成填充孔410时,可有效地防止损坏下方的接地引脚103。导电凸块108可以多个在竖直方向上叠加。在步骤S306中,如图4F所示,在绝缘壳体101上方覆盖屏蔽金属层105,屏蔽金属层105经配置以与屏蔽导电柱106的上端电连接从而进一步可与接地引脚103电连接。如图4G所示,在将连在一起的多个集成电路封装体100进行分割时,可以采用一次性切下去的简单的全切方式而得到多个分离的集成电路封装体100。因集成电路封装体100侧壁不必形成金属涂层,所以不用担心在全切时是否会切到信号引脚207致其裸露而与金属涂层互连导致信号引脚207短路。相应的,本发明具有制造工艺简单,制造成本低的优点。
由于屏蔽导电柱106的设置使得屏蔽金属层105与接地引脚103可在集成电路封装体100内部实现连接而且屏蔽导电柱106本身会起到一定的屏蔽作用,因而屏蔽金属层105无需设置至集成电路封装体100侧壁底部以与接地引脚103接触,集成封装体100的设计更为灵活。图5是根据本发明另一个实施例的集成电路封装体100的纵向截面示意图。在该实施例中,屏蔽金属层105除覆盖绝缘壳体104顶部外还进一步沿侧壁向下延伸至信号引脚207(未在图5中示出)上方。
图6是根据本发明又一个实施例的集成电路封装体100的纵向截面示意图。在该实施例中,屏蔽金属层105自绝缘壳体104顶部向下延伸包覆绝缘壳体104的全部侧壁。而裸露于绝缘壳体104侧壁外的信号引脚707预先涂覆上绝缘胶,从而防止屏蔽金属层105与信号引脚207接触而短路。
为满足屏蔽要求,每一接地引脚103上的屏蔽导电柱106的数量也可不限于一个。图7是根据本发明另一个实施例的集成电路封装体100的横向截面示意图。在该实施例中,每个接地引脚103上方可以设置多个屏蔽导电柱106。
本发明的技术内容及技术特点已揭示如上,然而熟悉本领域的技术人员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰。因此,本发明的保护范围应不限于实施例所揭示的内容,而应包括各种不背离本发明的替换及修饰,并为本专利申请权利要求书所涵盖。
Claims (23)
1.一种集成电路封装体,其包括:
芯片;
芯片座,经配置以承载所述芯片;
信号引脚,设置于所述芯片座外围且经配置以与所述芯片电连接;
接地引脚,设置于所述芯片座外围且经配置以接地;
绝缘壳体,其遮蔽所述芯片、所述芯片座、所述信号引脚、以及所述接地引脚;
屏蔽金属层,其覆盖在所述绝缘壳体上方;以及
屏蔽导电柱,设置于所述接地引脚上方并位于所述绝缘壳体内,所述屏蔽导电柱的上端经配置以与所述屏蔽金属层电连接,所述屏蔽导电柱的下端经配置以与所述接地引脚电连接。
2.根据权利要求1所述的集成电路封装体,其中所述接地引脚上设置有至少一导电凸块,所述多个屏蔽导电柱设置于所述导电凸块上。
3.根据权利要求2所述的集成电路封装体,其中所述至少一导电凸块为多个并布置成在竖直方向上叠加。
4.根据权利要求2所述的集成电路封装体,其中所述至少一导电凸块为多个非叠加的导电凸块,且在所述多个非叠加的导电凸块上分别设置相应的所述屏蔽导电柱。
5.根据权利要求1所述的集成电路封装体,其中所述至少一导电凸块是焊球或其它金属球。
6.根据权利要求1所述的集成电路封装体,其中所述接地引脚有多个,所述屏蔽导电柱中的每一者设置于该多个接地引脚中的相应一者上。
7.根据权利要求1所述的集成电路封装体,其中所述接地引脚当中包括位于所述集成电路封装体的端角处的接地引脚,所述端角处的接地引脚经配置以通过引线或连接部与所述芯片座电连接。
8.根据权利要求7所述的集成电路封装体,其中所述接地引脚当中还包括至少一个位于所述集成电路封装体的相邻端角之间的接地引脚。
9.根据权利要求7所述的集成电路封装体,其中所述相邻端角之间的接地引脚经配置以通过引线与所述端角处的接地引脚或所述芯片座电连接。
10.根据权利要求1所述的集成电路封装体,其中所述屏蔽金属层自所述绝缘壳体顶部向下延伸到未到达所述信号引脚。
11.根据权利要求1所述的集成电路封装体,其中所述屏蔽金属层自所述绝缘壳体顶部向下延伸包覆所述绝缘壳体的全部侧壁,所述信号引脚当中裸露于所述绝缘壳体侧壁的信号引脚预先涂覆有绝缘胶。
12.根据权利要求1所述的集成电路封装体,其中所述屏蔽导电柱的材料为导电胶或锡膏。
13.一种形成集成电路封装体的方法,其包括:
将芯片固定于芯片座上;
用引线连接所述芯片与信号引脚;
注塑而形成绝缘壳体,所述绝缘壳体遮蔽所述芯片、所述芯片座、所述信号引脚、所述芯片与所述信号引脚之间的所述引线、及接地引脚;
在所述绝缘壳体中自上而下形成位于所述接地引脚上方的填充孔;
在所述填充孔中填充导电材料以形成屏蔽导电柱,所述屏蔽导电柱的下端经配置以与所述接地引脚电连接;以及
在所述绝缘壳体上方覆盖屏蔽金属层,所述屏蔽金属层经配置以与所述屏蔽导电柱的上端电连接。
14.根据权利要求13所述的方法,进一步包括:
在注塑形成所述绝缘壳体之前,在所述接地引脚上形成至少一导电凸块;所述屏蔽导电柱是形成于所述导电凸块上。
15.根据权利要求14所述的方法,其中形成所述至少一导电凸块进一步包含使用打线机形成的焊球或金属球。
16.根据权利要求14所述的方法,其中形成所述至少一导电凸块进一步包含形成多个在竖直方向上叠加的导电凸块。
17.根据权利要求14所述的方法,其中形成所述至少一导电凸块进一步包含形成多个非叠加的导电凸块,且在所述多个非叠加的导电凸块上分别形成相应的所述屏蔽导电柱。
18.根据权利要求13所述的方法,其中所述接地引脚当中包括位于所述集成电路封装体的端角处的接地引脚,所述端角处的接地引脚经配置以通过引线或连接部与所述芯片座电连接。
19.根据权利要求18所述的方法,其中所述接地引脚当中还包括至少一个位于所述集成电路封装体的相邻端角之间的接地引脚。
20.根据权利要求19所述的集成电路封装体,其中所述相邻端角之间的接地引脚经配置以通过引线与所述端角处的接地引脚或所述芯片座电连接。
21.根据权利要13所述的方法,其中覆盖所述屏蔽金属层包括将所述屏蔽金属层自所述绝缘壳体顶部向下延伸到未到达所述信号引脚。
22.根据权利要13所述的方法,其进一步包括在覆盖所述屏蔽金属层之前对所述信号引脚当中裸露于所述绝缘壳体侧壁的信号引脚预先涂覆绝缘胶,其中覆盖所述屏蔽金属层包括将所述屏蔽金属层自所述绝缘壳体顶部向下延伸包覆所述绝缘壳体的全部侧壁。
23.根据权利要求13所述的方法,其中所述多个屏蔽导电柱为导电胶或锡膏。
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