CN104966693B - A kind of three-dimensionally integrated power system of embedded composite radiating structure and preparation method - Google Patents
A kind of three-dimensionally integrated power system of embedded composite radiating structure and preparation method Download PDFInfo
- Publication number
- CN104966693B CN104966693B CN201510296250.9A CN201510296250A CN104966693B CN 104966693 B CN104966693 B CN 104966693B CN 201510296250 A CN201510296250 A CN 201510296250A CN 104966693 B CN104966693 B CN 104966693B
- Authority
- CN
- China
- Prior art keywords
- layer
- high voltage
- power
- power system
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of three-dimensionally integrated power system of embedded composite radiating structure and preparation method, it includes fin（1）, fin（1）Top is High voltage power device layer（2）, High voltage power device layer（2）Top is low-voltage device and sensor component layer（3）, preparation method includes：Step 1, low-voltage device and sensor component layer（3）Make；The thermal vias of step 2, the making of High voltage power device layer and embedded chip layer make；Step 3, High voltage power device layer（2）Chip layer is stacked；Step 4, by High voltage power device layer（2）It is stacked on fin（1）After upper, by low-voltage device and sensor component layer（3）It is stacked on High voltage power device layer（2）On, three-dimensionally integrated power system of embedded composite radiating structure etc. is formed, the present invention solves the heat dissipation problem of three-dimensionally integrated power system, and therefore there is the advantages of integrated level is high, and power capacity is bigger.
Description
Technical field
A kind of the invention belongs to three-dimensionally integrated power system heat dissipation technology, more particularly to the three of embedded composite radiating structure
Dimension integrated power systems and preparation method.
Background technology
The continuous improvement of, intelligent, reliability requirement integrated to power system with Power Electronic Technique, for integrated
Power system (Power System on a Chip, abbreviation PSoC) on the very high monolithic piece of degree, i.e., senser element and control
Circuit processed, signal processing circuit, interface circuit, power device etc. are integrated on same chip block so as to according to load will
Ask fine adjustment output and carry out the intelligent function of self-protection situations such as according to overheated, over-pressed, excessively stream, its superiority do not say and
Analogy.And realize monolithic intelligent power integrated system key be based on HLV compatible IC, high-low pressure interconnection, high and low voltage isolation technology
Intelligent power integrated technology.At present, for silicon substrate smart power device, the BCD of maturation（Bipolar, CMOS, DMOS）
Technique has solved the problems, such as that the high and low pressure isolation structure in high and low pressure process compatible, but BCD techniques limits power system substantially
Development on high power capacity and high power density.And it is based on novel semiconductor material（Such as：SiC, GaN etc.）Power train
The integrated technology difficulty of system is big, and process costs are high.Since nineteen sixty-five, the founder G.Moore of Intel Company delivers Moore's Law
So far, the scale of integrated circuit follows substantially the rule and increases.Predict 2016, by the integrated electricity of batch production 22nm
Road, the characteristic size of transistor have been close to nanoscale.Knowable on physical knowledge, on such dimension scale, quantum effect
Can play a role, the relevant issues of current quantum effect are not addressed；And integrated technique size reduction is to deep-submicron
After magnitude, the performance of integrated circuit is occupied an leading position by device and is changed into interconnection line and occupies an leading position；During with multi-media network
The arriving in generation, people to Large Copacity, the pursuit of multi-functional, High performance electronics, signal delay caused by traditional integrated technology,
A series of problems, such as power consumption increases becomes increasingly conspicuous.Three-dimensional integration technology is acknowledged as the developing direction of following integrated technology, is to rub
The strong guarantee that your law remains valid.Three-dimensionally integrated is a kind of system-level architecture method, and it is using stacking in vertical direction
Transistor or chip or module so that integrated more device counts on unit area chip, and the integrated sharpest edges of 3D
Can be achieved on the multifunction system of highly heterogeneousization, you can to divide the device of difference in functionality, different materials or different process
Stack again to form a performance system of optimizing after not being produced in different chip layers.But as three-dimensional chip is than tradition two
The integrated device density in unit area of dimension chip is bigger, and with higher interconnection density, the multiple-level stack of active device
So that power dissipation density rises rapidly；Again as the heat conductivility of the dielectric layer between stack layer is low, becoming
The bottleneck of the passage of heat.And the power attenuation of the high power transistor under the high pressure in power system and high current working condition is more
Plus prominent, the power consumption of power transistor can be changed into heat makes tube core generate heat, and junction temperature is raised, if can not in time, effectively
By this heat release, the service behaviour of device is just influenced whether, so as to reduce the reliability of system work, or even damage device.
Content of the invention
The technical problem to be solved in the present invention：There is provided a kind of three-dimensionally integrated power system of embedded composite radiating structure and
Preparation method, bigger to solve the existing three-dimensional chip device density more integrated in unit area than conventional two-dimensional chip, and have
The multiple-level stack for having higher interconnection density, active device causes power dissipation density to rise rapidly；Again due to Jie between stack layer
The thermal conductivity of electric layer is very low, becomes the bottleneck of three-dimensional chip internal heat dissipating passage, and the high pressure in power system and high current work
Under the conditions of the power attenuation of high power transistor more project, the power consumption of power transistor can be changed into heat makes tube core
Heating, junction temperature are raised, if in time, effectively can not discharge this heat, just influence whether the service behaviour of device, so as to reduce
The reliability of system work, or even the problems such as damage device.
Technical solution of the present invention：
A kind of three-dimensionally integrated power system of embedded composite radiating structure, it includes fin, is high above fin
Pressure high power device layer, is low-voltage device and sensor component layer above High voltage power device layer.
The High voltage power device layer and low-voltage device and sensor component layer include a piece of or a piece of above core
Connected by through-silicon-via between each chip layer of lamella, High voltage power device layer and low-voltage device and sensor component layer
Connect.
Each power cell periphery in each chip layer of High voltage power device layer is uniformly provided with thermal vias, radiating
Metal material is perfused with through hole as packing material..
The thermal vias of each chip layer correspondence position of High voltage power device layer, power cell size and shape one
Cause.
The preparation method of the three-dimensionally integrated power system of the embedded composite radiating structure, it comprises the steps：
Low-voltage device and senser element in step 1, the control circuit by power system, protection circuit and detection circuit
It is integrated in a piece of or a piece of above chip layer, chip layer is piled up to form low-voltage device and sensor component layer；
Step 2, the High voltage power device in power system is integrated in a piece of or a piece of above chip layer, and
Reserve bore position in the power cell periphery of each chip layer；
Step 3, at the reserved bore position in each power cell periphery using plasma etching method holes drilled through, use low temperature
Chemical gas-phase deposition method generates insulating medium layer in through-holes, then forms barrier layer in through-holes with sputtering technology, finally uses
Galvanoplastic will be complete for the filling of via metal core, forms embedded thermal vias；
Step 4, the upper and lower surface of high-power chip layer for being embedded in thermal vias is entered with Chemical Physics glossing
Row polishing, the upper and lower metal joint face of embedded thermal vias is exposed and smooth, finally adopts low-temperature bonding technology by each high pressure
Each chip layer powerful is stacked in vertical direction, forms High voltage power device layer；
Step 5, by High voltage power device layer stacking on a heat sink after, low-voltage device and sensor component layer are stacked
On High voltage power device layer, the three-dimensionally integrated power system of embedded composite radiating structure is formed.
Beneficial effects of the present invention：
Process compatible of the technical solution of the present invention without the concern for power system mesolow device with high voltage power device is asked
Topic, takes and separates low-voltage device and high voltage power device, be integrated in different chip layers so that the integrated level of system is more
Height, power capacity are bigger；By thermal vias being internally embedded in high-voltage device chip layer, make the heat of high tension apparatus power consumption conversion
It is able to be diffused rapidly on fin, realizes quick heat radiating, is improved the stability and reliability of system；The present invention is solved
Prior art is bigger due to the three-dimensional chip device density more integrated in unit area than conventional two-dimensional chip, and has higher
Interconnection density, the multiple-level stack of active device causes power dissipation density to rise rapidly；Again due to the dielectric layer heat between stack layer
Lead that performance is low, become the bottleneck of three-dimensional chip internal heat dissipating passage, under the high pressure and high current working condition in power system
The power attenuation of high power transistor is more projected, and the power consumption of power transistor can be changed into heat makes tube core generate heat, knot
Temperature rise, if in time, effectively can not discharge this heat, just influences whether the service behaviour of device, so as to reduce system work
The reliability of work, or even the problems such as damage device.
Description of the drawings：
Fig. 1 is schematic structural view of the invention；
Fig. 2 is High voltage power device Rotating fields cross-sectional schematic of the present invention；
Fig. 3 is High voltage power device layer schematic top plan view of the present invention.
Specific embodiment：
A kind of three-dimensionally integrated power system of embedded composite radiating structure（See Fig. 1）, it includes fin 1, fin 1
Top is High voltage power device layer 2, is low-voltage device and sensor component layer 3 above High voltage power device layer 2.
The High voltage power device layer 2 and low-voltage device and sensor component layer 3 include a piece of or a piece of above
Led to by penetrating silicon between each chip layer of chip layer, High voltage power device layer 2 and low-voltage device and sensor component layer 3
Hole connects.The high and low pressure compatibling problem not considered further that in conventional silicon substrate BCD technique of the invention, and the high pressure work(in power system
Rate device, low-voltage device and senser element are separately produced in different chip layers, then pass through through-silicon-via complete layer
Connection between layer, makes interconnection wiring shorten in a large number, and systematic function reaches optimization.
Each 5 periphery of power cell in each chip layer of High voltage power device layer 2 is uniformly provided with thermal vias 4,
Due to high-voltage great-current device, in planar chip, occupied area can be up to the 2/3 of whole chip area, in order to improve chip
Integrated level and power capacity, the present invention are produced on the distribution of high-voltage great-current device in multiple chip layers, and in power device institute
The embedded thermal vias of each chip layer reducing the thermal resistance in heat diffusion path, the heat for allowing power device dissipated power to produce
Amount is quickly diffused into the bottom of three-dimensional chip.
Metal material is perfused with thermal vias 4 as packing material, and the metal material is high heat conductivity metal material,
Thermal vias, gold of the thermal vias packing material from high heat conductance is inserted in each chip layer of High voltage power device layer
Belong to reducing the thermal resistance of heat dissipation channel.
The power transistor being formed in parallel by a large amount of power device cellulars 7 in power system may be partitioned into many power lists
Unit, in each power cell, contained cellular number can be differed, by the temperature field of chip layer depending on, temperature lower position in chip
Power cell number containing cellular more, the power cell number containing cellular of temperature higher position is less；Then in each power
Multiple thermal vias are equably inserted in unit periphery, maximum of the peripheral thermal vias number of each power cell by power cell
Dissipated power determines that in a word, the temperature on power device chip layer after ensureing as far as possible to be embedded in composite radiating technology is basically identical.
For the ease of stacking, the power cell of power device layer each chip correspondence position is consistent with the size of thermal vias, shape.Embedding
Enter the power device Rotating fields top view after composite radiating technology and see Fig. 3.
The preparation method of the three-dimensionally integrated power system of the embedded composite radiating structure, it comprises the steps：
Low-voltage device and senser element in step 1, the control circuit by power system, protection circuit and detection circuit
It is integrated in a piece of or a piece of above chip layer, chip layer is piled up to form low-voltage device and sensor component layer 3；
Step 2, the High voltage power device in power system is integrated in a piece of or a piece of above chip layer, and
Reserve bore position in the power cell periphery of each chip layer；
Step 3, at the reserved bore position in each power cell periphery using plasma etching method holes drilled through, use low temperature
Chemical gas-phase deposition method generates insulating medium layer 6 in through-holes, then forms barrier layer in through-holes with sputtering technology, finally uses
Galvanoplastic will be complete for the filling of via metal core, forms embedded-type heat-dissipating through hole；
Step 4, with Chemical Physics glossing to formed embedded-type heat-dissipating through hole high-power chip layer upper and lower
Surface is polished, and the upper and lower metal joint face of thermal vias is exposed and smooth, finally adopts low-temperature bonding technology by each height
Pressure each chip layer powerful is stacked in vertical direction, forms High voltage power device layer 2；
Step 5, High voltage power device layer 2 is stacked on fin 1 after, by low-voltage device and sensor component layer 3
It is stacked on High voltage power device layer 2, forms the three-dimensionally integrated power system of embedded composite radiating structure.
The thermal conductivity of the wherein number of thermal vias, breadth depth ratio and internal filler metal determines the thermal resistance of heat dissipation channel.
Due to be chip layer blank space make thermal vias, therefore make thermal vias technique adopt low temperature process.Radiating is logical
Hole is determined by the thermal stress that layers of material coefficient of thermal expansion mismatch in thermal vias causes with the distance of power cell.
Claims (4)
1. a kind of preparation method of the three-dimensionally integrated power system of embedded composite radiating structure, the embedded composite radiating knot
The three-dimensionally integrated power system of structure includes fin（1）, fin（1）Top is High voltage power device layer（2）, the big work(of high pressure
Rate device layer（2）Top is low-voltage device and sensor component layer（3）, its preparation method comprises the steps：
Low-voltage device and senser element in step 1, the control circuit by power system, protection circuit and detection circuit is integrated
In a piece of or a piece of above chip layer, chip layer is piled up to form low-voltage device and sensor component layer（3）；
Step 2, the High voltage power device in power system is integrated in a piece of or a piece of above chip layer, and at each
Reserve bore position in the power cell periphery of chip layer；
Step 3, at the reserved bore position in each power cell periphery using plasma etching method holes drilled through, use cryochemistry
Gas-phase deposition method generates insulating medium layer in through-holes, then forms barrier layer in through-holes with sputtering technology, finally with plating
Method will be complete for the filling of via metal core, forms embedded thermal vias；
Step 4, the upper and lower surface of high-power chip layer for being embedded in thermal vias is thrown with Chemical Physics glossing
Light, the upper and lower metal joint face of embedded thermal vias is exposed and smooth, finally adopts low-temperature bonding technology by big for each high pressure work(
Each chip layer of rate is stacked in vertical direction, forms High voltage power device layer（2）；
Step 5, by High voltage power device layer（2）It is stacked on fin（1）After upper, by low-voltage device and sensor component layer
（3）It is stacked on High voltage power device layer（2）On, form the three-dimensionally integrated power system of embedded composite radiating structure.
2. the preparation method of the three-dimensionally integrated power system of a kind of embedded composite radiating structure according to claim 1,
It is characterized in that：The High voltage power device layer（2）With low-voltage device and sensor component layer（3）Include a piece of or a piece of
Above chip layer, High voltage power device layer（2）With low-voltage device and sensor component layer（3）Each chip layer between lead to
Cross through-silicon-via connection.
3. the preparation method of the three-dimensionally integrated power system of a kind of embedded composite radiating structure according to claim 1,
It is characterized in that：High voltage power device layer（2）Each chip layer on to be uniformly provided with radiating logical for each power cell periphery
Hole（4）, thermal vias（4）In be perfused with metal material as packing material.
4. the preparation method of the three-dimensionally integrated power system of a kind of embedded composite radiating structure according to claim 1,
It is characterized in that：High voltage power device layer（2）Each chip layer correspondence position thermal vias（4）, power cell（5）Greatly
Little consistent with shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510296250.9A CN104966693B (en) | 2015-06-03 | 2015-06-03 | A kind of three-dimensionally integrated power system of embedded composite radiating structure and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510296250.9A CN104966693B (en) | 2015-06-03 | 2015-06-03 | A kind of three-dimensionally integrated power system of embedded composite radiating structure and preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104966693A CN104966693A (en) | 2015-10-07 |
| CN104966693B true CN104966693B (en) | 2017-03-15 |
Family
ID=54220711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510296250.9A Active CN104966693B (en) | 2015-06-03 | 2015-06-03 | A kind of three-dimensionally integrated power system of embedded composite radiating structure and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104966693B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098687B (en) * | 2016-08-03 | 2019-04-16 | 贵州大学 | A kind of three-dimensional power VDMOSFET device and its integrated approach |
| CN107990277A (en) * | 2017-12-25 | 2018-05-04 | 上海小糸车灯有限公司 | Car light reflecting LED module system and vehicle lamp assembly |
| JP2021507485A (en) * | 2017-12-25 | 2021-02-22 | 華域視覚科技（上海）有限公司Ｈａｓｃｏ Ｖｉｓｉｏｎ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ． | Vehicle Light Reflective LED Module System and Vehicle Light Assembly |
| CN110137147A (en) * | 2019-07-02 | 2019-08-16 | 贵州大学 | Nested type pipe radiating network structure based on lower thick upper thin type TSV |
| CN110516382B (en) * | 2019-08-30 | 2022-08-12 | 贵州大学 | Thermal analysis method of three-dimensional integrated system based on silicon through hole |
| CN111128980A (en) * | 2019-12-04 | 2020-05-08 | 珠海欧比特宇航科技股份有限公司 | Heat dissipation processing method for three-dimensional packaging internal device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10181454B2 (en) * | 2010-03-03 | 2019-01-15 | Ati Technologies Ulc | Dummy TSV to improve process uniformity and heat dissipation |
| CN102243668A (en) * | 2010-05-12 | 2011-11-16 | 北京师范大学 | Thermal-expandability three-dimensional parallel cooling integration method, namely, on-chip system key technology for massively parallel computation |
| CN204632744U (en) * | 2015-06-03 | 2015-09-09 | 贵州大学 | A kind of three-dimensional integrated power systems of embedded composite radiating structure |
-
2015
- 2015-06-03 CN CN201510296250.9A patent/CN104966693B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104966693A (en) | 2015-10-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104966693B (en) | A kind of three-dimensionally integrated power system of embedded composite radiating structure and preparation method | |
| CN106098637B (en) | It is fanned out to pile system grade encapsulation (SIP) and its manufacturing method with pseudo- tube core | |
| US9905537B2 (en) | Compact semiconductor package and related methods | |
| US10381326B2 (en) | Structure and method for integrated circuits packaging with increased density | |
| CN104716109B (en) | With packaging part of thermal management component for reducing hot crosstalk and forming method thereof | |
| CN102931173B (en) | Multi-chip wafer level package | |
| KR101870931B1 (en) | Dummy tsv to improve process uniformity and heat dissipation | |
| US9240394B1 (en) | Stacked chips attached to heat sink having bonding pads | |
| CN105118823A (en) | Stacked type chip packaging structure and packaging method | |
| Sarvey et al. | Embedded cooling technologies for densely integrated electronic systems | |
| CN102569227B (en) | Integrated circuit radiating system and manufacturing method thereof | |
| Dembla et al. | Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs | |
| CN204632744U (en) | A kind of three-dimensional integrated power systems of embedded composite radiating structure | |
| Sabi | Advanced packaging in the new world of data | |
| CN103377990B (en) | Through-silicon via structure | |
| CN110516382B (en) | Thermal analysis method of three-dimensional integrated system based on silicon through hole | |
| CN109446612B (en) | SOP system integrated thermal management method | |
| US20240213120A1 (en) | Micro-electronic component combining power delivery and cooling from the back side | |
| Miyazawa et al. | CFD Simulation Analysis of Inter/Intra Chip Liquid Cooling for 3D Stacked ICs | |
| Said et al. | Thermal analysis of three-dimensional ICs, investigating the effect of through-silicon vias and fabrication parameters | |
| Harb et al. | Thermal Evaluation of TSVs in 3D-Integration Technology | |
| CN206210778U (en) | A kind of through-silicon via structure | |
| Brunschwiler et al. | Embedded power insert enabling dual-side cooling of microprocessors | |
| US9589937B2 (en) | Semiconductor cooling method and method of heat dissipation | |
| CN102543917B (en) | Integrated circuit heat dissipation device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |