CN102569227B - Integrated circuit radiating system and manufacturing method thereof - Google Patents
Integrated circuit radiating system and manufacturing method thereof Download PDFInfo
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- CN102569227B CN102569227B CN201010606627.3A CN201010606627A CN102569227B CN 102569227 B CN102569227 B CN 102569227B CN 201010606627 A CN201010606627 A CN 201010606627A CN 102569227 B CN102569227 B CN 102569227B
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- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 156
- 239000010410 layer Substances 0.000 claims abstract description 85
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 230000008569 process Effects 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims description 58
- 229910052751 metal Inorganic materials 0.000 claims description 58
- 239000004020 conductor Substances 0.000 claims description 38
- 239000012530 fluid Substances 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 32
- 238000001816 cooling Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 230000005855 radiation Effects 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 5
- 230000003252 repetitive effect Effects 0.000 claims description 5
- 238000004070 electrodeposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000002659 electrodeposit Substances 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 238000010422 painting Methods 0.000 claims description 2
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 230000000694 effects Effects 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 8
- 238000010276 construction Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 206010034960 Photophobia Diseases 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000004883 computer application Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 208000013469 light sensitivity Diseases 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses an integrated circuit radiating system, which comprises at least three layers of substrates including an upper layer substrate, an interlayer substrate and a lower layer substrate, wherein a micro channel is formed between adjacent substrates; current conducting channels are formed in the three layers of substrates; the upper layer substrate is electrically connected with an integrated circuit chip through the current conducting channel; adjacent substrates are electrically connected with each other through the current conducting channel by passing through the micro channel; and the lower layer substrate is electrically connected with external power through the current conducting channel. According to the method, the problem that heat cannot be brought out in a three-dimensional integrated encapsulating model is solved, the radiating performance of the chip is improved greatly, the reliability of the chip is enhanced, and the service life of the chip is prolonged; and the integrated circuit radiating system has the characteristics of simple process, low cost, and the like.
Description
Technical field
The present invention relates to microelectronic packaging technology, MEMS technology and three-dimensional integration technology field, specifically a kind of integrated circuit radiating system and manufacture method.
Background technology
Along with microelectronic chip high speed, high density, high performance development, a very important problem during heat management has become micro-system to encapsulate, so the heat dissipation problem in integrated circuit is very important in many computer applications.In high-performance calculation machine, such as server, large-scale computer and super computer, the radiating efficiency of multi-chip module directly will affect design and the operating characteristics of computer.
The heat of chip flows through resistance by electric current and produces.Resistance heat-dissipating is that the process of being carried out transmitting and power transmits along metal wire by signal on chip produces, and also can be leaked by IC substrate by individual Transistor bias currents and produce in transistor level transfer process.The generation of another kind of heat occur in multi-chip module or and motherboard between carry out on the conductor resistance of signal and power transimission.
Heat radiation in integrated circuit is generally transmitted to the heat diffuser that has high thermal conductivity coefficient by chip, and the fin eventually through high surface area is melt in convection gas.In order to strengthen radiating effect, convection current may be cooled, and wherein integrated circuit carries out by fluid line the focus that liquid radiating becomes present chip package system heat management.
Multi-chip module is generally made up of the electrical insulating material of the embedded interference networks of multilayer, and insulating material is normally ceramic.High-performance multi-chip module generally can comprise 80 ~ 120 layers of metal and electric insulation layer, 6 ~ 8 cm thicks.The conductive coefficient of pottery insulating material is equivalent to 1/30 of silicon, 1/80 of copper.Integrated circuit (IC) chip is typically connected on the electrical connection salient point of chip surface two-dimensional arrangement.
Multi-chip component structure generally comprises substrate connected vertically, the integrated circuit (IC) chip be connected with by salient point.The structure formed thus is commonly called " lamination ".Multiple " lamination " and single integrated circuit (IC) chip also can be connected on salient point, on the multi-chip module surface of traditional two-dimensional arrangement, unless implemented suitable cooling provision, otherwise multiple chip-stacked continuous rising that will bring chip temperature due to heat history.Therefore, high-performance computer system, while realizing providing to multi-chip module necessary interference networks wiring density, only relies on traditional heat dissipating method of chip, is difficult to reach meeting of its design performance.
Summary of the invention
An object of the present invention is the integrated circuit radiating system providing a kind of good heat dissipation effect.
A kind of integrated circuit radiating system is provided according to an aspect of the present invention, comprises at least three laminar substrates: top substrate layer, interlayer substrate and underlying substrate, form microchannel between adjacent substrate;
Establish conductive path in described three laminar substrates are equal, wherein top substrate layer is electrically connected with integrated circuit (IC) chip by described conductive path, is electrically connected between adjacent substrate by described conductive path through microchannel, and underlying substrate is by described conductive path and external electrical connections.
Wherein, described top substrate layer is semiconductor substrate, and interlayer substrate is metal substrate, and underlying substrate is semiconductor substrate.
Wherein, the conductive path of described top substrate layer comprise be arranged at described top substrate layer upper surface with the salient point be electrically connected with described integrated circuit (IC) chip, and be arranged at the lower surface of described top substrate layer and be arranged in the described microchannel formed with described interlayer substrate and the salient point be electrically connected with the conductive path of described interlayer substrate, also comprise and be arranged in described top substrate layer and be electrically connected the electric conductor of the salient point of described upper surface and lower surface.
Wherein, the surface of described top substrate layer is provided with insulating barrier, arranges network of conductors in this insulating barrier, and this network of conductors is electrically connected described integrated circuit (IC) chip and described electric conductor as a part for the conductive path of described top substrate layer.
Wherein, the conductive path of described interlayer substrate comprises and is arranged at the upper surface of this interlayer substrate and/or the salient point of lower surface, this salient point is arranged in the microchannel that formed with adjacent substrate and is electrically connected with the conductive path of described adjacent substrate, also comprises and is arranged in described interlayer substrate and is electrically connected the electric conductor of described salient point.
Wherein, the surface of described interlayer substrate arranges insulating barrier, arranges network of conductors in this insulating barrier, and this network of conductors is electrically connected the conductive path of described top substrate layer and the electric conductor of described interlayer substrate as a part for the conductive paths of described interlayer substrate.
Wherein, the conductive path of described underlying substrate comprises and is arranged at the upper surface of this underlying substrate and the salient point of lower surface, and is arranged at the electric conductor of salient point of the described upper surface of electrical connection and lower surface in described underlying substrate;
Wherein, the salient point being arranged at upper surface described in is arranged in the microchannel that formed with adjacent substrate and is electrically connected with the conductive path of described adjacent substrate; Described salient point and the external electrical connections being arranged at lower surface.
Wherein, the surface of described underlying substrate arranges insulating barrier, arranges network of conductors in this insulating barrier, and this network of conductors is electrically connected the described conductive path of interlayer substrate and the electric conductor of this underlying substrate as a part for the conductive path of described underlying substrate.
Wherein, described salient point and/or electric conductor are formed by electrodeposit metals technique or are formed by electro-deposition multi-element metal technique.
Wherein, described electric conductor is arranged in the electrical connection vias that counterpart substrate is formed, and this electrical connection vias periphery arranges insulating barrier and barrier layer.
Wherein, in described three laminar substrates, at least one laminar substrate inside arranges microchannel.
Wherein, outside heat sink or external fluid radiator structure is also comprised.
Wherein, this cooling system is isolated by seal and external environment condition.
Wherein, this cooling system is applied to the heat radiation of multi-chip module, and described integrated circuit (IC) chip is multi-chip module.
Another aspect of the present invention also provides the manufacture method of interlayer substrate in a kind of integrated circuit radiating system, comprises the following steps:
Steps A: deposit passivation layer, in substrate layer, is coated with light-sensitive material in passivation layer, exposes under the mask of mask;
Step B: remove the light-sensitive material outside described mask masks area;
Step C: deposited seed layer is in the surface of the expose portion of described light-sensitive material and passivation layer;
Step D: depositing metal layers is in Seed Layer;
Step e: described in thinning and planarization, metal level obtains smooth surface;
Step F: remove residue light-sensitive material and obtain metal structure;
Step G: make insulating barrier and Seed Layer in the exposed surface of described metal structure and passivation layer;
Step H: depositing metal layers is in Seed Layer described in previous step;
Step I: described in thinning and planarization previous step, metal level obtains smooth surface, makes passivation layer in this surface;
Step J: remove substrate layer, at the back side painting light-sensitive material of the structure that above-mentioned steps obtains, obtains with the etching technics of passivation layer the hole being communicated with the metal level deposited in described step H by photoetching process, on the exposed surface of this hole, makes Seed Layer;
Step K: make metal level above the Seed Layer described in step J;
Metal level in step L: thinning and planarization treatment step K obtains smooth surface;
Step M: in removal step J, remaining light-sensitive material obtains bump structure.
Wherein, also comprise after step M:
Step N: based on the interlayer substrate formed in step M, make connecting salient points in its one side, another side makes the insulating barrier including built-in conductive network, obtains repetitive;
The described repetitive that several are identical carries out lamination; Wherein, the insulating barrier of a repetitive is connected with the salient point of another repetitive.
The integrated circuit radiating system that the present invention proposes and method improve cooling integrated efficiency.
Accompanying drawing explanation
Fig. 1 is the cross-sectional schematic of an embodiment of integrated circuit radiating system of the present invention;
Fig. 2 is the flow chart of the manufacturing process A-H step of middle interlayer metal substrate embodiment illustrated in fig. 1;
Fig. 3 is the flow chart that hookup 2I-N walks;
Fig. 4 is the schematic diagram of another embodiment of integrated circuit radiating system of the present invention;
Fig. 5 is the schematic diagram of the 3rd embodiment of integrated circuit radiating system of the present invention;
Fig. 6 is the schematic diagram of the 4th embodiment of integrated circuit radiating system of the present invention.
Embodiment
In order to make object of the present invention, it is more clear that technical scheme and advantage describe, and is illustrated below in conjunction with concrete example and accompanying drawing.Multi-chip module described in the present invention is different from existing multi-chip module model, and it not only provides an electrical interconnection network, but also provides multi-chip module and connect the cooling integrated structure of multi-chip module.Multi-chip module model in the present invention utilizes the compressible fluid flowed in microchannel, and is dispelled the heat by the flow velocity of structure control fluid.The fluid passage that Multi-chip component structure in the present invention simultaneously is also formed by the material of high heat conductance manages the heat in package system.In addition, can also be dispelled the heat to system by the passage that increases the incompressible fluid be coupled with inner flow passage in outside or the type of cooling of adding other types.
Method described in the invention in addition, material and manufacture craft also can be applied to the heat radiation in single IC for both and one single chip model.
The present invention is mainly used in highdensity electrical connection network (comprising route integrated circuit and switch integrated circuit), the processor of such as multinuclear and main memory circuit.
Multi-chip module is used to transmit electronic signal, the signal of telecommunication and earth signal between integrated circuit die, and the nude film of these integrated circuits is mainly used for performing specific function, and such as logic compares, addition, memory, the digital signal of switch and route.In normal operation, each integrated circuit produces certain calorimetric, and these heats are mainly produced by the resistance of current path material.If heat can not outwardly distribute at a high speed, so the temperature of integrated circuit will constantly rise, and the work of integrated circuit will be adversely affected at certain temperatures.Therefore dispel the heat and become extremely important for integrated circuit, the present invention provides higher rate of heat dispation, mainly because this structure can be taken away as far as possible near the heat of thermal source for the total system of integrated circuit and multi-chip module.In current science and technology, in order to reduce thermal resistance, nude film is very thin by what subtract.Now main application be that mode at the back of nude film by thermal conductance is dispelled the heat, general employing ceramic substrate or encapsulant nude film before.Heat transfer is mainly undertaken by encapsulant and the metal being embedded into pottery that is connected with wired network, and the cooling duct material thermal conductivity wherein in the conductive coefficient of Ceramic Substrate Material and glass and ceramic substrate relatively.
Microchannel cooling in ceramic substrate material will be difficult to obtain reasonable radiating effect, and the thermal conductivity mainly due to ceramic material itself is very little.Therefore be necessary close to the pyrotoxin of transistor and heat radiation as far as possible efficiently as much as possible.In order to reach this purpose, multi-chip module radiator structure is proposed in the present invention, this radiator structure as much as possible close to the transistor layer of integrated circuit, and is had the composite material of high heat conductance by employing and is dispelled the heat by the mode of directly carrying out dispelling the heat in the inside of multi-chip module.
With reference to figure 1, illustrate the cross-sectional schematic of the multi-chip module encapsulating structure embodiment comprising integrated circuit radiating system of the present invention.Multi-chip module encapsulating structure comprises three laminar substrate structures, is respectively top substrate layer 150, interlayer substrate 170 and underlying substrate 180.In order to set forth more clearly, other extra plays here above board structure are left in the basket.Further, the microchannel 165 of dispelling the heat for passing through for fluid is defined between adjacent substrate.
The material containing the different thermal conductivity of two classes of these three board structures, top substrate layer 150 and underlying substrate 180 use semiconductor substrate, and interlayer substrate 170 uses metal substrate.All the insulating barrier 120 including built-in metal network of conductors is being distributed with at the upper surface of described three substrates.
Wherein, wire 132 in insulating barrier 120 and wire column 130 function form described network of conductors, this network of conductors is also as a part for corresponding conductive path, and this part conductive path forms the conductive path corresponding with described substrate jointly with the electric conductor in the electrical connection vias 140,190 or 155 arranged in counterpart substrate.
Further, for top substrate layer, its conductive path is also included in the salient point 135 between insulating barrier 120 and substrate 150, and object is the electrical connection of electric conductor in the electrical connection vias 140 realizing wire redistributing layer and substrate 150 in insulating barrier 120.And at the upper surface of insulating barrier 120, namely the upper end of the whole conductive path of top substrate layer is also provided with salient point 125, its effect realizes being electrically connected with integrated circuit die 115 and 105, and wherein integrated circuit 105 also may be the integrated circuit 110 having multiple-level stack.And at the lower surface of substrate 150, the namely lower end of top substrate layer conductive path, salient point 145 is provided with in microchannel 165, this salient point 145 provides the space of passage, provide the heat conduction path by microchannel, regulate the mean flow rate of fluid, and also provide the electrical connection through microchannel 165.
In like manner, the microchannel 165 between interlayer substrate and underlying substrate is also provided with salient point 145, and is also provided with salient point 135 between insulating barrier 120 and substrate 170, is also provided with salient point 135 between insulating barrier 120 and substrate 180, same as above with effect.
Further, the lower surface of substrate 180 is provided with salient point 160 to be electrically connected with external connection interface section 185.
So, the conductive path in three laminar substrates and each salient point just achieve the electrical connection of integrated circuit die 105 and 115 and external connection interface section 185.And when passing through fluid in microchannel 165, just can take away heat, and the salient point 145 in microchannel 165 serves the effect regulating flow velocity, adds thermal conductivity, improves radiating effect.
Preferably, distribute one deck electrical insulating material on wire again, and this material has lower thermal conductivity and reasonable electrical insulation capability.
Board structure 150,170 and 180 is used to increase inner conductive coefficient, and the signal of insulating barrier 120 inner conductors and conductive pole part and distribution network.Board structure 180 has thicker substrate layer, can provide stronger machinery support for whole encapsulating structure and provide the interface be electrically connected with the carrying out of substrate stage.The microchannel 165 formed between the layers provides the passage of circulation for compressible fluid, and these fluids generally have low surface tension, low viscosity and high specific heat capacity.
Fig. 2 and Fig. 3 respectively illustrates the flow chart (wherein, the situation of what A-M step obtained is one deck, N step then indicates multilayer laminated situation) of the manufacturing process A-H of middle interlayer metal substrate embodiment illustrated in fig. 1 and I-N step.Mainly the fabrication processing of the conductive through hole in metal substrate structure 170 and conductive wire is described in detail.As shown in Figure 2, the Making programme before formation conductive structure has mainly been set forth.
As shown in Fig. 2 step A, it has set forth the application of photoetching process, utilizes a lithography layout 205 with planar graph, carries out photoetching to photoresist or the material 210 with light sensitivity.On substrate layer 220, form one deck include SiO
2or SiN
1-xpassivation layer 215.Passivation layer is mainly applied to the self-stopping technology layer of electrochemical mechanical polishing.Utilize suitable light after exposing photoresist layer 210, utilize photoresist wet etching solution or dry plasma etching process to remove the material exposed, thus obtain the structure 210 as shown in 2B step.
As shown in Fig. 2 step C, in the Seed Layer 225 that the deposited on silicon layer of metal of structure 210 deposits.Wherein the example of specific implementation is that copper as a Seed Layer for copper metal deposition, also can be able to be other metal deposition, but will apply the Seed Layer of other correspondences, such as nickel and gold etc.
As shown in Fig. 2 D step, metal level 230 needs the thickness utilizing specific process deposits certain, such as Applied Electrochemistry or chemical deposition process method.Metal level 230 needs to have higher thermal conductivity, and the inside of multi-chip module can be made better to dispel the heat.
As shown in Fig. 2 E step, metal level 230 needs to be thinned to required thickness after deposit, forms a more smooth plane, and certain thickness and the reasonable metal level of surface quality can ensure the technique of the semiconductor integrated circuit better carrying out upper strata; Step 2E can apply conventional CMP technique and realize, and the thickness of the thinning depositing metal layers of one side reaches requirement can make surface smooth on the other hand.Fig. 2 E step describes smooth metal level 230 structure, and the thickness of metal level 230 is identical with the thickness of photoresist 210.
As shown in Fig. 2 F step, after removing photoresist layer 210, just can form required metal structure according to the character of the photoresist used.The technique of concrete removal photoresist layer can be applied organic solvent wet etching and also may apply gas chemistry plasma dry etch.
As shown in Fig. 2 G step, at the structured metal layer 230 surface deposition one deck electric insulation layer 225 such as shown in Fig. 2 F step, on insulating barrier 225, deposit one deck Seed Layer 223;
As shown in Fig. 2 H step, deposition layer of metal layer 232 is on Seed Layer, and wherein metal level 230 and metal level 232 can be made up of different metal materials, are isolated each other by insulating barrier 225.
As shown in Fig. 3 I step, the thinning and flatening process of metal level 232 reaches the surface of insulating barrier 225, at the passivation layer 216 that its uppermost deposited on silicon one deck is similar to passivation layer 215.
As shown in Fig. 3 J step, then remove substrate layer 220 until close to passivation layer 215 and metal level 232.The combined material of what substrate layer 220 may adopt is glass material, semi-conducting material, metal material or multiple material.The process removing substrate 220 includes aqueous solution wet method or plasma dry etch, mechanical lapping and polishing.Minimizing technology can not destroy passivation layer 215.At surperficial spin coating one deck photoresist layer 235 of passivation layer 215 after removing substrate layer 220, this layer photoetching glue is similar to photoresist 210, then utilize lithography mask version and combine applicable parameter and carry out photoetching process, and utilize etchant solution to remove the part that can remove, figure required for formation, in addition in order to better remove the parameter that the photoresist be included in below passivation layer suitably can adjust etching process.
Remaining photoresist removes a layer insulating 215 below as the semiconductor fabrication process that mask application is conventional.Thereafter the hole 236 of the photoresist of metal layer is formed in;
Then conducting electricity with metal level 232 to realize, in hole 236, filling a kind of conductor material.Similar to metal deposition process shown in Fig. 2 G, so just obtain the structure as shown in Fig. 3 J step, wherein metal seed layer 240 deposits on the exposed surface, mainly on the surface of hole 236 and photoresist 235.
As shown in Fig. 3 K step, then can adopt electrochemical deposition process plated metal 233 in Seed Layer 240, obtain the result as shown in Fig. 3 K step;
As shown in Fig. 3 L step, then adopt flatening process such as mechanization glossing to be that metal level 233 has a smooth plane, obtain the structure as shown in Fig. 3 L step;
As shown in Fig. 3 M step, remove the bump structure 260 as shown in Fig. 3 M step that then photoresist obtains being connected with 232, this salient point is made up of metal level 233.
Above introduced manufacture method process as shown in Figure 2, the structure that the technical process of A to M obtains, just can obtain interlayer substrate in the present invention by the combination of these techniques and process and only have the situation of one deck, when described interlayer substrate comprises multilayer to form the laminated construction of major part Multi-chip component structure of the present invention, then can repeat said process by stacked for the interlayer metal substrate obtained (embodiment can reference diagram 3N); It is a kind of laminated construction with the heat transfer channel of high-termal conductivity.
As shown in Fig. 3 N step, mainly describing the multi-chip module laminate portion with internal gas passageways, is also major part of the present invention.Described part includes structure I, II, III, IV, and structure I corresponds to Fig. 3 M part shown in Fig. 2, and the structure in Fig. 3 I step is by other the anatomical connectivity of connecting salient points 265 with system.Conducting metal salient point 260 effect is as shown in the figure the mechanical strength increasing structure and the heat-conductive characteristic increased by passage 165, bump structure 260 defines microchannel 165 in structure I and structure I I, salient point 260 and 261 also has and regulates by the effect of the heat radiation of multi-chip module, and realizing two kinds of approach is: (1) is by the flowing of fluid in passage thus to regulate in whole pipeline gaseous fluid in the average flow velocity of local; (2) by it, there is reasonable heat-conductive characteristic and regulate heat-conductive characteristic in the duct.The Embedded network of conductors of the electrical connection wire column Embedded with vertical electrical connection of level is defined in the electrical insulating material on structure I I surface.Structure 255 and 269 represents the wire of formation, and structure 250 then represents the wire column of formation.Structure III is similar to structure I, and realize the connection of electricity and machinery by salient point 260 and salient point 265 with layer IV, structure III and structure I V define microchannel 165 by salient point 260.Wherein structure I V may include the IC semiconductor wafer with being made up of transistor and plain conductor.
That is, the one side of the structure formed in step M in step N makes connecting salient points, and another side makes the insulating barrier including built-in conductive network, then two that obtain identical metal substrate structures is carried out lamination; Wherein the conductive network face of one deck is connected with the salient point surface of another layer, and is connected by metal substrate thicker to the salient point surface of this laminated construction and another, is formed and has three-ply metal and the lamination radiator structure including fluid passage.
Wherein, I and III is equivalent to the stacked of two-layer interlayer metal substrate, and it is two repetitives, and II part is then equivalent to insulating barrier, conductive network (can with reference to above relevant portion) is set in it, metal substrate thicker described in IV part is then equivalent to.
Fig. 4 show comprise integrated circuit heat dissipation device of the present invention and another embodiment schematic diagram of cooling system; Fig. 4 A describes a kind of cross section of package system, and package system comprises the multi-chip module 330 with microchannel 165 (namely fluid passage) and fluid intake and interface channel 305.Syndeton 305 utilizes hermetically-sealed construction (comprising seal 310,315 and 317) and external environment to isolate.Wherein seal 310 realizes the sealing between syndeton 305 and substrate 340, and seal 315 and 317 realizes the sealing between syndeton 305 and multi-chip module 330.
The fin 320 of two integrated circuit dies 325 is placed on the inside of coupling radiator structure 330 as internal heat dissipation structures, substrate 340 provides the mechanical support of whole system, and the electrical connection of System and Circuit plate is realized by contact contact 343 and 345.Fluid is respectively the first temperature T1 at the characteristic parameter at entrance 350 place of syndeton 305, passing through the first flow velocity V1 and first pressure of microchannel 165, the second temperature T2 > T1 is respectively, the second flow velocity V2 and the second pressure P 2 > P1 at the characteristic parameter at outlet 360 place.As shown in Figure 4 B, describe the cross section of package system and seal member 310,315 and 317, this cross section be scheme at such as Fig. 4 A shown in 370 position undertaken observable by cutting line A-B.
Fig. 5 show comprise integrated circuit heat dissipation device of the present invention and the 3rd embodiment schematic diagram of cooling system; What Fig. 5 A illustrated is one and includes multi-chip module 330, the fluid passage 467 (being alternatively microchannel) of the inside of microchannel 165 (namely fluid passage) and setting and board structure in assembly.Fluid in syndeton 420 is respectively the first temperature T1 at the characteristic parameter at entrance 350 place, and gas first flow velocity V1 in microchannel 165 and 467 and the first pressure P 1, also be respectively the second temperature T2 > T1 at the characteristic parameter at outlet 450 place in addition, and gas second flow velocity V2 in microchannel 165 (namely fluid passage) and 467 and the second pressure P 2 > P1.Its middle outlet 450 and entrance 350 isolation are realized by the hermetically-sealed construction (comprising seal 319,315 and 317) of standard.Microchannel 467 (namely fluid passage) makes the uniformity in pipeline of gas/liquid flow.
The microchannel 415 (namely fluid passage) of fluid liquid is included in the external structure 410 of fluid cooling coupled structure 420.Wherein, in microchannel 415, the heat eliminating medium of flowing is a kind of incompressible fluid, and this radiator structure can dispel the heat to circuit chip 325.Contact contact 430 is for providing heat conducting passage between integrated circuit (IC) chip 325 and the cooling structure 410 in fluid cooling coupled structure 420.Integrated circuit (IC) chip is passed through syndeton 343 and 345 with circuit board and realizes being electrically connected at the opening 460 that fluid cools in coupled structure 420.As shown in Figure 5 B, describe the cross section of package system and seal member 315 and 317, this cross section be scheme at such as Fig. 5 A shown in 470 position undertaken observable by cutting line A-B.
Fig. 6 show comprise integrated circuit heat dissipation device of the present invention and the 4th embodiment schematic diagram of cooling system.The sectional view of this embodiment that what Fig. 6 part A was detailed set forth, comprises the transmission channel (summary similar to Fig. 5 embodiment) of multi-chip module 330 and fluid.This view be by the position viewing 570 in Fig. 6 C part along the cutaway view of A-C line, the hermetically-sealed construction 315 between the coupling radiator structure 420 of its fluid passage and substrate 340 can be seen.Realize being electrically connected with circuit board by syndeton 343 and 345, wherein fluid coupling radiator structure 420 is communicated with the external world by opening 460 part.
Fig. 6 part B is the cross-sectional view of the present embodiment, includes the transmission channel of multi-chip module 330 and fluid equally.Second view is at the cutaway view of Fig. 6 C part along B-C line by the position viewing 570.
Shown in Fig. 6 C is the horizontal sectional view of the present embodiment, can see the hermetically-sealed construction 315 between substrate 340 and coupling radiator structure 420.Also can see the bare chip 325 of integrated circuit, and the space 460 of opening on substrate 340 realizes the combination with circuit board by some electrical connections simultaneously.The entrance of refrigerating gas is in figure shown in 350.
The present invention may be used for the multi-chip module of the vertical or planar interconnect of cooling integrated circuit.The present invention can strengthen pipeline pyroconductivity.
The present invention can be further used for processor and processor extension, and level cache nearest on multi core chip carrier carries out transfer of data.External cache and processor chip carry out high speed data transfer by the wide dedicated bus of multidigit in multinuclear module.Outside buffer memory can be placed near multi core chip.
The present invention can be further used in high performance system.Specifically, these high performance systems configuration three-dimensional comprehensive static RAM (SDRAM) or embedded type dynamic random access memory (EDRAM).The memory of this two type is generally all integrated among the processor chip of the confined space.Along with the increase of the quantity of processor, near the high-speed cache that it can be placed on urgent need, but outside processor.This strategy needs in the cooling of multi-chip module enterprising row cache heap superimposition runner.
Invention be also embodied in the overall heat dissipation speed being improved processor and other integrated circuit (IC) chip with multi-chip module by the cooling of pipe interior fluid, in addition, the approach of outside liquid cooling and heat conductivity can help to improve radiating efficiency.
Invention be also embodied in and improve processor thermal conductivity for multi-chip module by having the metal of interior embedded hole and semiconductor layer Conduction cooled.
In the present invention, multi-chip module improves usefulness by shorter through hole.According to structure of the present invention, the integral thickness expectation of multi-chip module can be more much smaller than the ceramic multi-chip module of the metal level with equal number.This can cause stray inductance, electric capacity, resistance to reduce, and thus needs less buffer to revise clock jitter and distorted signals.The less through hole adopted relative to ceramic multi-chip module the present invention causes shorter propagation delay and less memory access latency.
In yet another aspect, due to the factor of materials and structures, it is infeasible that ceramic multi-chip module reaches the wiring density meeting WeiLai Technology requirement.The wire laying mode that the design of multi-chip module of the present invention and structure use, by pneumatic cooling pipe, may be used for realizing integrated circuit height wiring density.
Above-described embodiment is the present invention's preferably execution mode; but embodiments of the present invention are not restricted to the described embodiments; change, the modification done under other any does not deviate from Spirit Essence of the present invention and principle, substitute, combine, simplify; all should be the substitute mode of equivalence, be included within protection scope of the present invention.
Claims (15)
1. the manufacture method of interlayer substrate in integrated circuit radiating system, described integrated circuit radiating system, comprises at least three laminar substrates: top substrate layer, interlayer substrate and underlying substrate, form microchannel between adjacent substrate;
Establish conductive path in described three laminar substrates are equal, wherein top substrate layer is electrically connected with integrated circuit (IC) chip by described conductive path, is electrically connected between adjacent substrate by described conductive path through microchannel, and underlying substrate is by described conductive path and external electrical connections;
It is characterized in that, described manufacture method comprises the following steps:
Steps A: deposit passivation layer, in substrate layer, is coated with light-sensitive material in passivation layer, exposes under the mask of mask;
Step B: remove the light-sensitive material outside described mask masks area;
Step C: deposited seed layer is in the surface of the expose portion of described light-sensitive material and passivation layer;
Step D: depositing metal layers is in Seed Layer;
Step e: described in thinning and planarization, metal level obtains smooth surface;
Step F: remove residue light-sensitive material and obtain metal structure;
Step G: make insulating barrier and Seed Layer in the exposed surface of described metal structure and passivation layer;
Step H: depositing metal layers is in Seed Layer described in previous step;
Step I: described in thinning and planarization previous step, metal level obtains smooth surface, makes passivation layer in this surface;
Step J: remove substrate layer, at the back side painting light-sensitive material of the structure that above-mentioned steps obtains, obtains with the etching technics of passivation layer the hole being communicated with the metal level deposited in described step H by photoetching process, on the exposed surface of this hole, makes Seed Layer;
Step K: make metal level above the Seed Layer described in step J;
Metal level in step L: thinning and planarization treatment step K obtains smooth surface;
Step M: in removal step J, remaining light-sensitive material obtains bump structure.
2. manufacture method according to claim 1, is characterized in that, the top substrate layer of described cooling system is semiconductor substrate, and interlayer substrate is metal substrate, and underlying substrate is semiconductor substrate.
3. manufacture method according to claim 1, it is characterized in that, the conductive path of the top substrate layer of described cooling system comprise be arranged at described top substrate layer upper surface with the salient point be electrically connected with described integrated circuit (IC) chip, and be arranged at the lower surface of described top substrate layer and be arranged in the described microchannel formed with described interlayer substrate and the salient point be electrically connected with the conductive path of described interlayer substrate, also comprise and be arranged in described top substrate layer and be electrically connected the electric conductor of the salient point of described upper surface and lower surface.
4. manufacture method according to claim 3, it is characterized in that, the surface of the top substrate layer of described cooling system is provided with insulating barrier, arrange network of conductors in this insulating barrier, this network of conductors is electrically connected described integrated circuit (IC) chip and described electric conductor as a part for the conductive path of described top substrate layer.
5. manufacture method according to claim 1, it is characterized in that, the conductive path of the interlayer substrate of described cooling system comprises and is arranged at the upper surface of this interlayer substrate and/or the salient point of lower surface, this salient point is arranged in the microchannel that formed with adjacent substrate and is electrically connected with the conductive path of described adjacent substrate, also comprises and is arranged in described interlayer substrate and is electrically connected the electric conductor of described salient point.
6. manufacture method according to claim 5, it is characterized in that, the surface of the interlayer substrate of described cooling system arranges insulating barrier, arrange network of conductors in this insulating barrier, this network of conductors is electrically connected the conductive path of described top substrate layer and the electric conductor of described interlayer substrate as a part for the conductive paths of described interlayer substrate.
7. manufacture method according to claim 1, it is characterized in that, the conductive path of the underlying substrate of described cooling system comprises and is arranged at the upper surface of this underlying substrate and the salient point of lower surface, and is arranged at the electric conductor of salient point of the described upper surface of electrical connection and lower surface in described underlying substrate;
Wherein, the salient point being arranged at upper surface described in is arranged in the microchannel that formed with adjacent substrate and is electrically connected with the conductive path of described adjacent substrate; Described salient point and the external electrical connections being arranged at lower surface.
8. manufacture method according to claim 7, it is characterized in that, the surface of the underlying substrate of described cooling system arranges insulating barrier, arrange network of conductors in this insulating barrier, this network of conductors is electrically connected the described conductive path of interlayer substrate and the electric conductor of this underlying substrate as a part for the conductive path of described underlying substrate.
9. the manufacture method according to any one of claim 3 to 8, is characterized in that, the salient point of described cooling system and/or electric conductor are formed by electrodeposit metals technique or formed by electro-deposition multi-element metal technique.
10. the manufacture method according to any one of claim 3 to 8, is characterized in that, the electric conductor of described cooling system is arranged in the electrical connection vias that counterpart substrate is formed, and this electrical connection vias periphery arranges insulating barrier and barrier layer.
11. manufacture methods according to any one of claim 1 to 8, is characterized in that, in three laminar substrates of described cooling system, at least one laminar substrate inside arranges microchannel.
12. manufacture methods according to any one of claim 1 to 8, is characterized in that, described cooling system also comprises outside heat sink or external fluid radiator structure.
13. manufacture methods according to any one of claim 1 to 8, is characterized in that, described cooling system is isolated by seal and external environment condition.
14. manufacture methods according to any one of claim 1 to 8, is characterized in that, described cooling system is applied to the heat radiation of multi-chip module, and described integrated circuit (IC) chip is multi-chip module.
15. manufacture methods according to claim 1, is characterized in that, also comprise after step M:
Step N: based on the interlayer substrate formed in step M, make connecting salient points in its one side, another side makes the insulating barrier including built-in conductive network, obtains repetitive;
The described repetitive that several are identical carries out lamination; Wherein, the insulating barrier of a repetitive is connected with the salient point of another repetitive.
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| CN104201157B (en) * | 2014-08-08 | 2017-12-19 | 武汉新芯集成电路制造有限公司 | Semiconductor heat-dissipating structures and methods in hybrid bonded technique |
| CN109060865A (en) * | 2018-07-26 | 2018-12-21 | 桂林电子科技大学 | A kind of experimental provision of equivalent heat source |
| EP4218049A1 (en) * | 2020-09-24 | 2023-08-02 | Hrl Laboratories, Llc | Wafer-level integrated micro-structured heat spreaders |
| CN113192915B (en) * | 2021-04-26 | 2024-02-27 | 武汉新芯集成电路制造有限公司 | Three-dimensional integrated circuit module and manufacturing method |
| CN115084059B (en) * | 2022-08-16 | 2022-12-02 | 杭州飞仕得科技有限公司 | Preparation method of insulating substrate and power device packaging method |
| CN116153883B (en) * | 2023-04-10 | 2023-07-07 | 广东仁懋电子有限公司 | IGBT packaging method and IGBT packaging structure |
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| CN1925155A (en) * | 2005-09-02 | 2007-03-07 | 株式会社半导体能源研究所 | Integrated circuit device |
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| US7138064B2 (en) * | 2002-02-15 | 2006-11-21 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| CN1925155A (en) * | 2005-09-02 | 2007-03-07 | 株式会社半导体能源研究所 | Integrated circuit device |
| CN101477971A (en) * | 2007-12-31 | 2009-07-08 | 联发科技股份有限公司 | Semiconductor chip and its production method |
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