CN102543917B - Integrated circuit heat dissipation device - Google Patents
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- CN102543917B CN102543917B CN201010606435.2A CN201010606435A CN102543917B CN 102543917 B CN102543917 B CN 102543917B CN 201010606435 A CN201010606435 A CN 201010606435A CN 102543917 B CN102543917 B CN 102543917B
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- 230000017525 heat dissipation Effects 0.000 title claims abstract description 24
- 239000012530 fluid Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims description 57
- 239000010410 layer Substances 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 238000001816 cooling Methods 0.000 claims description 21
- 238000007789 sealing Methods 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000009828 non-uniform distribution Methods 0.000 claims description 3
- 238000006748 scratching Methods 0.000 claims 1
- 230000002393 scratching effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 24
- 239000000463 material Substances 0.000 description 18
- 230000008569 process Effects 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 230000000694 effects Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000002161 passivation Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 230000005855 radiation Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000033228 biological regulation Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000005764 inhibitory process Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000000112 cooling gas Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
Disclose a kind of integrated circuit heat dissipation device, including being provided with the microchannel of input port and delivery outlet, described microchannel arranges obstruction body.In the present invention, owing to being provided with obstruction body in microchannel, thus can hinder and reduce the flow velocity of fluid in microchannel, such that it is able to take away more heat.
Description
Technical field
The present invention relates to microelectronic packaging technology, MEMS technology and three-dimensional integration technology field, a kind of integrated
Circuit heat abstractor.
Background technology
Along with microelectronic chip high speed, high density, high performance development, heat management has become in micro-system encapsulation
Very important problem, so the heat dissipation problem in integrated circuit is critically important in many computer utilitys.In high-performance
In computing machine, such as server, large scale computer and super computer, the radiating efficiency of multi-chip module will directly affect computer
Design and operating characteristics.
The heat of chip is flowed through resistance by electric current and produces.Resistance heat is to be carried out along metal wire by signal on chip
The process that transmission and power transmit produces, and also can be leaked and transistor by IC substrate by individual Transistor bias currents
Produce during level conversion.The generation of another kind of heat occur multi-chip module or and motherboard between carry out signal and power
On the conductor resistance of transmission.
Heat radiation in integrated circuit is transmitted to a heat diffuser with high thermal conductivity coefficient generally by chip,
It is melt in convection gas by the fin of high surface area eventually.In order to strengthen radiating effect, convection current may be cooled, its
Middle integrated circuit carries out liquid radiating by fluid line and becomes the focus of present chip package system heat management.
Multi-chip module is typically made up of the electrically insulating material of the embedded interference networks of multilamellar, and insulant is typically pottery.
High-performance multi-chip module typically can comprise 80～120 layers of metal and electric insulation layer, 6～8 cm thicks.Pottery electric insulation material
The heat conductivity of material is equivalent to the 1/30 of silicon, the 1/80 of copper.IC chip is typically connected to chip surface two-dimensional arrangement
On electrical connection salient point.
Multi-chip component structure generally comprises substrate connected vertically, and the IC chip connected by salient point.By
This structure formed is commonly called " lamination ".Multiple " laminations " and single IC chip can also be connected to salient point
On, on the multi-chip module surface of traditional two-dimensional arrangement, unless implemented suitable cooling provision, the most multiple chip stack
The folded continuous rising that will bring chip temperature due to heat history.Therefore, high-performance computer system is realizing to multi-chip
While assembly provides necessary interference networks wiring density, rely solely on traditional heat dissipating method of chip, be extremely difficult to it
Meeting of design performance.
Summary of the invention
An object of the present invention is to provide a kind of more preferable integrated circuit heat dissipation device of radiating effect.
A kind of integrated circuit heat dissipation device is proposed according to an aspect of the present invention, including being provided with input port and delivery outlet
Microchannel, arranges obstruction body in described microchannel.
Wherein, described obstruction body is multiple, and the plurality of obstruction body non-uniform Distribution in described microchannel.
Wherein, described obstruction body is vertically arranged relative to the fluid flow direction of described microchannel or inversely arranges.
Wherein, the obstruction face of described obstruction body is vertically arranged relative to the fluid flow direction of described microchannel or inversely sets
Put.
Wherein, also include arranging attachment structure at the input port of described microchannel, the one end open of this attachment structure, another
End connects with the input port of described microchannel, and the joint of this attachment structure and described microchannel arranges sealing structure.
Wherein, the equipped at outlet port of described microchannel arranges attachment structure, the one end open of this attachment structure, the other end and institute
State the delivery outlet connection of microchannel, and the joint of this attachment structure and described microchannel arranges sealing structure.
Wherein, described obstruction body is the salient point being arranged in described microchannel.
Wherein, described obstruction body is conductive material, and its two ends electrically connect the part to be connected outside described microchannel.
Wherein, in described microchannel, the flowing velocity of fluid is more than or equal to 0.1 Mach and less than or equal to 0.5 Mach.
Wherein, fluid inputs the input pressure of this heat abstractor more than or equal to 2bar and less than or equal to 11bar.
Wherein, described microchannel is arranged in the stepped construction of multi-chip module.
The integrated circuit heat dissipation device that the present invention proposes can improve the radiating efficiency of integrated circuit.
Accompanying drawing explanation
Fig. 1 is an embodiment cross-sectional schematic of the cooling system comprising integrated circuit heat dissipation device of the present invention；
Fig. 2 is the flow chart of the manufacturing process A-H step of interlayer metal substrate in embodiment illustrated in fig. 1；
Fig. 3 is the flow chart of hookup 2I-N step；
Fig. 4 is another embodiment schematic diagram of the cooling system comprising integrated circuit heat dissipation device of the present invention；
Fig. 5 is the schematic diagram of the 3rd embodiment of the cooling system comprising integrated circuit heat dissipation device of the present invention；
Fig. 6 is the schematic diagram of the 4th embodiment of the cooling system comprising integrated circuit heat dissipation device of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, it is apparent that technical scheme and advantage describe, below in conjunction with concrete example and attached
Figure is illustrated.Multi-chip module described in the present invention is different from existing multi-chip module model, and it not only provides
One electrical interconnection network, but also multi-chip module is provided and connects the cooling integrated structure of multi-chip module.This
Multi-chip module model in bright utilizes the compressible fluid of flowing in microchannel, and is entered by the flow velocity of structure control fluid
Row heat radiation.The fluid passage that Multi-chip component structure in the present invention is formed also by high thermal conductivity material simultaneously is to package system
In heat be managed.Furthermore it is also possible to by increase in outside the passage of incompressible fluid coupled with inner flow passage or
Person adds the other kinds of type of cooling and dispels the heat system.
Method, material and processing technology the most described in the invention can also be applied to single IC for both and single
Heat radiation in chip model.
Present invention is mainly applied to highdensity electrical connection network (including routeing integrated circuit and switch integrated circuit), than
Processor and main memory circuit such as multinuclear.
Multi-chip module is used to transmit electronic signal, the signal of telecommunication and earth signal between integrated circuit die, and these are integrated
The nude film of circuit is primarily used to perform specific function, such as logic and compares, addition, memorizer, the number switching and routeing
Word signal.In normal operation, each integrated circuit produces certain calorimetric, and these heats are mainly by current path
Produced by the resistance of material.If heat can not outwardly distribute at a high speed, then the temperature of integrated circuit will be continuous
Rising, the work of integrated circuit will be adversely affected at certain temperatures.Therefore dispel the heat and integrated circuit is become non-
The most important, total system that the present invention is integrated circuit and multi-chip module provides higher rate of heat dispation, is primarily due to
This structure can be taken away as far as possible near the heat of thermal source.In current science and technology, in order to reduce thermal resistance, nude film has been subtracted
The thinnest.Primarily now apply is to dispel the heat by the way of thermal conductance at the back of nude film, general employing before nude film
Ceramic substrate or encapsulant.Conduction of heat mainly by encapsulant and be connected with wired network be embedded into pottery
Metal is carried out, wherein the heat conductivity of Ceramic Substrate Material and the cooling duct material thermal conductivity ratio in glass and ceramic substrate
It is closer to.
Microchannel cooling in ceramic substrate material would become hard to obtain reasonable radiating effect, mainly due to pottery
The thermal conductivity of material itself is the least.Therefore pyrotoxin and efficient as far as possible heat radiation as close as transistor are to have very much
Necessary.In order to reach this purpose, proposing multi-chip module radiator structure in the present invention, this radiator structure is as far as possible
Close to the transistor layer of integrated circuit, and there is the mixing material of high heat conductance and by directly in multi-chip group by employing
The mode that the inside of part carries out dispelling the heat is dispelled the heat.
Fig. 1 is an embodiment cross-sectional schematic of the cooling system comprising integrated circuit heat dissipation device of the present invention.This
The cooling system of bright integrated circuit heat dissipation device includes three laminar substrate structures, respectively top substrate layer 150, interlayer substrate 170 and
Underlying substrate 180.For the elaboration become apparent from, here other extra plays above board structure are left in the basket.Further, adjacent
Define between substrate for for fluid by and the microchannel 165 dispelled the heat.
These three board structure contains the material of two class difference thermal conductivities, and top substrate layer 150 and underlying substrate 180 use
Be semiconductor substrate, interlayer substrate 170 uses metal basal board.In the upper surface of three substrates is distributed with and includes
Put the insulating barrier 120 of plain conductor network.
Wherein, the wire 132 in insulating barrier 120 and wire column 130 form network of conductors.This network of conductors also serves as accordingly
A part for conductive path, this partially electronically conductive path and leading in the electrical connection vias 140,190 or 155 of setting in counterpart substrate
Electricity body collectively forms the conductive path corresponding with substrate.
Further, for top substrate layer, its conductive path is additionally included in the salient point between insulating barrier 120 and substrate 150
135, it is therefore an objective to realize being electrically connected of electric conductor in distribution layer with the electrical connection vias 140 of substrate 150 of wire in insulating barrier 120
Connect.And, at the upper surface of insulating barrier 120, namely the upper end of the whole conductive path of top substrate layer also is provided with salient point 125, its
Effect realizes electrically connecting with integrated circuit die 115 and 105.Wherein, integrated circuit 105 is also likely to be the integrated of multiple-level stack
Circuit 110.And at the lower surface of substrate 150, the namely lower end of top substrate layer conductive path, it is provided with convex in microchannel 165
Point 145.This salient point 145 provides the space of passage, it is provided that by the heat conduction path of microchannel, the mean flow of regulated fluid
Speed, and also provide the electrical connection through microchannel 165.
In like manner, the microchannel 165 between interlayer substrate and underlying substrate also is provided with salient point 145, and insulating barrier 120 with
It also is provided with salient point 135 between substrate 170, between insulating barrier 120 and substrate 180, also is provided with salient point 135, with effect and phase above
With.
Further, the lower surface of substrate 180 is provided with salient point 160 to electrically connect with external connection interface section 185.
So, the conductive path in three laminar substrates and each salient point just achieve integrated circuit die 105 and 115 with outside
Connect the electrical connection of interface 185.And when fluid is passed through in microchannel 165, just can take away heat, and in microchannel 165
Salient point 145 serves the effect of regulation flow velocity, adds thermal conductivity, improves radiating effect.
Preferably, one layer of electrically insulating material of redistribution on wire, this material have than relatively low thermal conductivity and
Reasonable electrical insulation capability.
Board structure 150,170 and 180 is used to increase internal heat conductivity, and insulating barrier 120 inner conductors and conduction
The signal of post ingredient and distribution network.Board structure 180 has the substrate layer that comparison is thick, it is possible to carry for whole encapsulating structure
Support for stronger machinery and the interface being electrically connected with substrate stage is provided.The microchannel formed between the layers
165 provide the passage of circulation for compressible fluid, and these fluids typically have low surface tension, low viscosity and high ratio
Thermal capacitance.
Preferably, the salient point 145 in microchannel 165 is non-homogeneous setting, and salient point 145 is relative to the fluid stream of microchannel
Dynamic direction is vertically arranged or inversely arranges.Fluid flowing direction namely from the direction of the input port of microchannel to delivery outlet,
Flow to give in Fig. 4 and Fig. 5 embodiment become apparent from expressing about fluid.
Fig. 2 shows that manufacturing process A-H of interlayer metal substrate in embodiment illustrated in fig. 1 and Fig. 3 show shown in Fig. 1 real
Execute the flow chart of the manufacturing process I-N step of interlayer metal substrate in example.Mainly to the conductive through hole in metal substrate structure 170 and
The fabrication processing of conductive wire has been described in detail.
As shown in Fig. 2 step A, it elaborates the application of photoetching process, utilizes a lithography layout with planar graph
205, to photoresist or there is the material 210 of heliosensitivity carry out photoetching.On substrate 220, formation one layer includes SiO2Or
Person is SiN1-xPassivation layer 215.Passivation layer is mainly applied to the self-stopping technology layer of electrochemical mechanical polishing.Utilize suitable light
After photoresist layer 210 is exposed, photoresist wet etching solution or dry plasma etching process is utilized to remove sudden and violent
The material of dew, thus obtain the structure 210 as shown in 2B step.
As shown in Fig. 2 step C, the surface of structure 210 deposits the Seed Layer 225 of layer of metal deposition.Wherein, a kind of
The example implemented is that copper can be as the Seed Layer of copper metal deposit, it is also possible to is other metal deposit, but to apply
The Seed Layer of other correspondences, such as nickel and gold etc..
As shown in Fig. 2 D step, metal level 230 needs the thickness utilizing specific process deposits certain, such as applies electrification
Learn or chemical deposition process method.Metal level 230 needs have the thermal conductivity that comparison is high, can make the inside of multi-chip module more
Good carrying out is dispelled the heat.
As shown in Fig. 2 E step, metal level 230 needs to be thinned to required thickness after deposit, forms a comparison and puts down
Smooth plane.Certain thickness and the reasonable metal level of surface quality ensure that the integrated electricity of quasiconductor more preferably carrying out upper strata
The technique on road；Step 2E can apply conventional CMP technique to realize, and the thickness of the most thinning deposition metal level reaches
To requiring that another aspect can make surface smooth.Fig. 2 E describes smooth metal level 230 structure, the thickness of metal level 230 and
The thickness of photoresist 210 is identical.
As shown in Fig. 2 F step, just can be formed according to the character of the photoresist used after removal photoresist layer 210 and be wanted
The metal structure asked.The concrete technique removing photoresist layer can apply organic solvent wet etching to be likely to apply gas
Phase chemical plasma dry etching.
As shown in Fig. 2 G step, deposit one layer of electric insulation layer on structured metal layer 230 surface as shown in Fig. 2 F step
225, in one layer of Seed Layer 223 deposited above of insulating barrier 225.
As shown in Fig. 2 H step, deposition layer of metal layer 232 on Seed Layer, wherein metal level 230 and metal level
232 can be made up of different metal materials, are isolated by insulating barrier 225 each other.
As shown in Fig. 3 I step, metal level 232 is thinning and flatening process reaches the surface of insulating barrier 225, goes up most at it
One layer of passivation layer 216 similar to passivation layer 215 is deposited on the surface in face.
As shown in Fig. 3 J step, then remove substrate 220 until close to passivation layer 215 and metal level 232.Substrate layer 220
The combined material of glass material, semi-conducting material, metal material or multiple material may be used.Remove substrate 220
Process include aqueous solution wet method or plasma dry etch, mechanical lapping and polishing.Minimizing technology can not break
Bad passivation layer 215.At the surface spin coating one layer photoetching glue-line 235 of passivation layer 215, this layer photoetching glue after removing substrate layer 220
235 is similar to photoresist 210, then utilizes lithography mask version combination to be suitable for parameter and carries out photoetching process, and utilizes corrosion
Solution removes the part that can remove, the figure required for formation, is included in the light below passivation layer in addition to more preferably remove
Photoresist can suitably adjust the parameter of etching process.
Remaining photoresist removes a following layer insulating 215 as the semiconductor fabrication process that mask application is conventional.
It is subsequently formed the hole 236 of the photoresist in face on the metal layer；
Then in order to realize conducting electricity with metal level 232, hole 236 is filled a kind of conductor material.With gold shown in Fig. 2 G
Belong to depositing operation similar, then just obtaining the structure as shown in Fig. 3 J step, wherein metal seed layer 240 is deposited on the table of exposure
On face, mainly on the surface of hole 236 and photoresist 235.
As shown in Fig. 3 K step, electrochemical deposition process then can be used to deposit metal 233 in Seed Layer 240,
To the result as shown in Fig. 3 K step；
As shown in Fig. 3 L step, then using flatening process such as mechanization glossing is that metal level 233 has one
Individual smooth plane, obtains the structure as shown in Fig. 3 L step；
As shown in Fig. 3 M step, convex as shown in Fig. 3 M step removing that then photoresist obtain being connected with metal level 232
Dot structure 260, this salient point is made up of metal level 233.
Manufacture method process described above as shown in Figures 2 and 3, the structure that the technical process of A to M obtains, logical
The combination crossing these techniques and process can be obtained by the lamination knot of the main major part Multi-chip component structure of the present invention
Structure, it is the laminated construction of a kind of conduction of heat channel with high-termal conductivity.
Shown in Fig. 3 N step, primarily illustrate the multi-chip module laminate portion with internal gas passageways, be also this
Bright major part.Described part includes structure I, II, III, IV, and structure I corresponds to Fig. 3 M step portion shown in Fig. 2
Point, the structure in Fig. 3 I step is connected with other structure of system by connecting salient points 265.Conducting metal as depicted
Salient point 260 effect is to increase the mechanical strength of structure and increases the heat-conductive characteristic by passage 165, and bump structure 260 is at knot
Structure I and structure I I define microchannel 165, and salient point 260 and 261 also has the effect of the regulation heat radiation by multi-chip module, real
Existing two kinds of approach are: (1) by the flowing of fluid in passage thus regulation in whole pipeline gaseous fluid in local
Average flow velocity；(2) by it, there is reasonable heat-conductive characteristic and regulate heat-conductive characteristic in the duct.Structure I I
The electrically insulating material on surface defines level electrically connect Embedded network of conductors and vertical electrical connection is Embedded leads
Terminal.Structure 255 and 269 represents the wire of formation, and structure 250 then represents the wire column of formation.Structure III and structure
I is similar, realizes connection electrically and mechanically, structure III and structure I V by salient point 260 by salient point 260 and salient point 265 with layer IV
Define microchannel 165.The integrated circuit that wherein structure I V may include with being made up of transistor and plain conductor is partly led
Body wafer.
Fig. 4 shows another embodiment schematic diagram of the cooling system comprising integrated circuit heat dissipation device sum of the present invention；
Fig. 4 A illustrates the cross section of a kind of package system, and package system comprises with microchannel 165 (namely fluid passage) and stream
The multi-chip module 330 of body entrance and interface channel 305.Attachment structure 305 utilizes sealing structure (to include sealing member 310,315
With 317) isolate with external environment.Wherein sealing member 310 realizes the sealing between attachment structure 305 and substrate 340, seals
Part 315 and 317 realizes the sealing between attachment structure 305 and multi-chip module 330.
The fin 320 of two integrated circuit dies 325 is placed on coupling radiator structure 330 as internal heat dissipation structures
Inside, substrate 340 provides the mechanical support of whole system, and system is by contacting contact 343 with the electrical connection of circuit board
Realize with 345.Fluid characteristic parameter at the entrance 350 of attachment structure 305 is respectively the first temperature T1, is passing through microchannel
The first flow velocity V1 of 165 and the first pressure, the characteristic parameter at outlet 360 is respectively the second temperature T2 ＞ T1, second flow speed
V2 and the second pressure P2 ＞ P1.As shown in Figure 4 B, illustrate package system and the cross section of seal member 310,315 and 317, this
Cross section is to carry out observable in the position of 370 as shown in Fig. 4 A figure by cutting line A-B.
Fig. 5 shows the 3rd embodiment schematic diagram of the cooling system comprising integrated circuit heat dissipation device sum of the present invention；Figure
Being one and include multi-chip module 330 of 5A explanation, microchannel 165 (namely fluid passage) and setting and substrate in assembly
The fluid passage 467 (could also say that microchannel) of the inside of structure.The fluid in attachment structure 420 spy at entrance 350
Levy parameter and be respectively the first temperature T1, and gas the first flow velocity V1 in microchannel 165 and 467 and the first pressure P1, separately
The most also characteristic parameter at outlet 450 is respectively the second temperature T2 ＞ T1, and in microchannel 165 (namely fluid passage)
With 467 in gas second flow speed V2 and the second pressure P2 ＞ P1.Its middle outlet 450 and entrance 350 are isolated by standard
Seal what structure (including sealing member 319,315 and 317) realized.Microchannel 467 (namely fluid passage) makes gas/liquid
Uniformity flowing in pipeline.
External structure 410 in fluid cooling coupled structure 420 includes the microchannel 415 of fluid liquid and (namely flows
Body passage).Wherein, in microchannel 415, the heat eliminating medium of flowing is a kind of incompressible fluid, and this radiator structure can be right
Circuit chip 325 dispels the heat.Contact contact 430 be IC chip 325 and fluid cool down in coupled structure 420 cold
The passage of conduction of heat is but provided between structure 410.IC chip and circuit board by attachment structure 343 and 345 and
Opening 460 in fluid cooling coupled structure 420 realizes electrical connection.As shown in Figure 5 B, package system and sealing are illustrated
The cross section of part 315 and 317, this cross section is to carry out observation in the position of 470 as shown in Fig. 5 A figure by cutting line A-B to obtain
's.
Fig. 6 shows the 4th embodiment schematic diagram of the cooling system comprising integrated circuit heat dissipation device sum of the present invention.Figure
What 6A part was detailed elaborates the sectional view of this embodiment, and the transmission channel including multi-chip module 330 and fluid is (real with Fig. 5
Execute the similar summary of example).This view is to be watched at Fig. 6 C portion along the sectional view of A-C line by the position 570, it can be seen that
Sealing structure 315 between coupling radiator structure 420 and the substrate 340 of its fluid passage.Real by attachment structure 343 and 345
Now electrically connecting with circuit board, wherein fluid coupling radiator structure 420 is communicated with the external world by opening 460 part.
Fig. 6 part B is the cross-sectional view of the present embodiment, includes the transmission channel of multi-chip module 330 and fluid equally.
Second view is by watching in the position of 570 at Fig. 6 C portion along the sectional view of B-C line.
Shown in Fig. 6 C is the horizontal sectional view of the present embodiment, it can be seen that substrate 340 and coupling radiator structure 420 it
Between sealing structure 315.Simultaneously it can be seen that the bare chip 325 of integrated circuit, and the space of the opening on substrate 340
460 realize the combination with circuit board by some electrical connections.The entrance of cooling gas is in figure shown in 350.
Due to the fact that in microchannel, be provided with obstruction body (salient point), thus can hinder and reduce fluid in microchannel
Flow velocity, such that it is able to take away more heat.And, the obstruction body in the present invention can also also serve as conductive component, connects microchannel
Outside part to be connected.
The non-uniform Distribution obstructing body (salient point) can play more preferable inhibition, and when making described obstruction body phase
When fluid flow direction for described microchannel is vertically arranged or inversely arranges, it is also possible to play more preferable inhibition.Special
When not being to obstruct the obstruction face of body to be vertically arranged relative to the fluid flow direction of described microchannel or inversely arrange, inhibition
More preferably.Obstruction face refers to the face that first described obstruction body contacts with fluid.
The attachment structure that input port, microchannel and equipped at outlet port are arranged is capable of providing the good of device with external fluid
Docking, seals structure and then may insure that fluid does not leaks.
The present invention can be further used for processor and extension outside processor, and one-level nearest on multi core chip carrier is delayed
Deposit and carry out data transmission.External cache and processor chip carry out high-speed data by many bit wides dedicated bus in many core modules
Transmission.Outside caching can be placed near multi core chip.
The present invention can be further used in high performance system.Specifically, these high performance systems configuration three-dimensional comprehensive
Static RAM (SDRAM) or embedded type dynamic random access memory (EDRAM).The memorizer of both types
Typically all it is integrated among the processor chip of the confined space.Along with the increase of the quantity of processor, it can be placed
Near the cache being badly in need of, but outside processor.This strategy need multi-chip module enterprising row cache stacking and
Runner cools down.
Invention be also embodied in and improve the total of processor and other IC chips by the cooling of pipe interior fluid
Body rate of heat dispation, additionally, the approach of outside liquid cooling and heat conductivity can help to improve radiating efficiency.
Invention be also embodied in by having the metal of interior embedded hole and semiconductor layer conduction cooling to improve processor thermal conductance
Rate.
In the present invention, multi-chip module improves usefulness by shorter through hole.According to the structure of the present invention, multi-chip group
The integral thickness of part is expected to more much smaller than the ceramic multi-chip module of the metal level with equal number.This may cause to post
Raw inductance, electric capacity, resistance reduce, so that less buffer revises clock jitter and distorted signals.Relative to pottery
The less through hole that the multi-chip module present invention uses causes shorter propagation delay and less memory access latency.
In yet another aspect, due to material and the factor of structure, pottery multi-chip module reaches to meet WeiLai Technology requirement
Wiring density be infeasible.The wire laying mode that the design of the multi-chip module of the present invention and structure use is by pneumatic cooling
Pipeline, may be used for realizing integrated circuit height wiring density.
Above-described embodiment is the present invention preferably embodiment, but embodiments of the present invention are not by above-described embodiment
Limit, the change made under other any spirit without departing from the present invention and principle, modify, substitute, combine, simplify,
All should be the substitute mode of equivalence, within being included in protection scope of the present invention.
Claims (6)
1. an integrated circuit heat dissipation device, including being provided with the microchannel of input port and delivery outlet, arranges resistance in described microchannel
Scratching body, described obstruction body is the salient point being arranged in described microchannel；Described obstruction body is conductive material, its two ends electrical connection institute
State the part to be connected outside microchannel；In described microchannel, the flowing velocity of fluid is more than or equal to 0.1 Mach and to be less than or equal to
0.5 Mach；The pressure of the fluid of described heat abstractor input is more than or equal to 2bar and less than or equal to 11bar；
It is characterized in that,
The cooling system of described integrated circuit heat dissipation device includes three laminar substrate structures, respectively top substrate layer (150), interlayer base
Plate (170) and underlying substrate (180), described top substrate layer (150) and underlying substrate (180) use semiconductor substrate, institute
State interlayer substrate (170) and use metal basal board；At described top substrate layer (150), interlayer substrate (170) and underlying substrate
(180) upper surface is distributed with the insulating barrier (120) including built-in metal network of conductors.
Integrated circuit heat dissipation device the most according to claim 1, it is characterised in that described obstruction body is multiple and described
Multiple obstruction bodies non-uniform Distribution in described microchannel.
Integrated circuit heat dissipation device the most according to claim 1, it is characterised in that described obstruction body is micro-logical relative to described
The fluid flow direction in road is vertically arranged or inversely arranges.
Integrated circuit heat dissipation device the most according to claim 3, it is characterised in that the obstruction face of described obstruction body relative to
The fluid flow direction of described microchannel is vertically arranged or inversely arranges.
Integrated circuit heat dissipation device the most according to claim 1, it is characterised in that arrange at the input port of described microchannel
Attachment structure, the one end open of described attachment structure, the other end connects with the input port of described microchannel, and described connection ties
Structure arranges sealing structure with the joint of described microchannel.
Integrated circuit heat dissipation device the most according to claim 1, it is characterised in that the equipped at outlet port of described microchannel is arranged
Attachment structure, the one end open of described attachment structure, the other end connects with the delivery outlet of described microchannel, and described connection ties
Structure arranges sealing structure with the joint of described microchannel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010606435.2A CN102543917B (en) | 2010-12-24 | Integrated circuit heat dissipation device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010606435.2A CN102543917B (en) | 2010-12-24 | Integrated circuit heat dissipation device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102543917A CN102543917A (en) | 2012-07-04 |
| CN102543917B true CN102543917B (en) | 2016-12-14 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728365A (en) * | 2004-07-01 | 2006-02-01 | 国际商业机器公司 | Apparatus and methods for microchannel cooling of semiconductor integrated circuit packages |
| CN1819165A (en) * | 2004-11-24 | 2006-08-16 | 朗迅科技公司 | Techniques for microchannel cooling |
| CN101005753A (en) * | 2006-01-17 | 2007-07-25 | 德尔菲技术公司 | Microchannel heat sink |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1728365A (en) * | 2004-07-01 | 2006-02-01 | 国际商业机器公司 | Apparatus and methods for microchannel cooling of semiconductor integrated circuit packages |
| CN1819165A (en) * | 2004-11-24 | 2006-08-16 | 朗迅科技公司 | Techniques for microchannel cooling |
| CN101005753A (en) * | 2006-01-17 | 2007-07-25 | 德尔菲技术公司 | Microchannel heat sink |
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