CN104979305A - Semiconductor device - Google Patents
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- CN104979305A CN104979305A CN201410140258.1A CN201410140258A CN104979305A CN 104979305 A CN104979305 A CN 104979305A CN 201410140258 A CN201410140258 A CN 201410140258A CN 104979305 A CN104979305 A CN 104979305A
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Abstract
The invention provides a semiconductor device which comprises a semiconductor substrate, microelectronic members arranged on the semiconductor substrate, inter-metal dielectric layers arranged on the semiconductor substrate in sequence, metal interconnecting wires embedded in the inter-metal dielectric layers and connected with the microelectronic members, chain-type redundancy metal structures arranged in the inter-metal dielectric layers and insulated with the metal interconnecting wires; a dielectric layer arranged on the inter-metal dielectric layers; bond pads arranged in the dielectric layer and connected with the microelectronic members through the metal interconnecting wires respectively; and radiators arranged in the dielectric layer, insulated with the bond pads and connected with the chain-type redundancy metal structures. The radiators with the chain-type redundancy metal structures can provide more and deeper heat conduction paths, thereby effectively improving heat dissipation effect of a chip.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device.
Background technology
Along with very lagre scale integrated circuit (VLSIC) is along the development of Moore's Law, the integrated level of integrated circuit is up to several hundred million components and parts.Postpone for reducing RC, IC structure have employed three-dimensional and wiring multiple stratification.Layer stereo structure proposes high requirement to material surface planarization, if flattening effect is bad, then along with the increase of the number of plies, the uneven degree accumulative effect on surface is remarkable.Up to the present, the key process technology that uniquely can realize global planarizartion is cmp (Chemical Mechanical Polishing is called for short CMP) technology.And in CMP process, the uneven fluctuating causing metal thickness of density metal, produce dish, wearing and tearing, therefore need before CMP process, carry out redundancy metal (Dummy Metal) in the low density region of metal interconnecting wires and fill the density regulating metal, thus make the thickness after IC chip design CMP close to consistent.Therefore redundancy metal is mainly used in regulating density metal in prior art.
For adapting to the requirement of integrated circuit high density, compact, chip-stacked technology has become the trend of integrated circuit development.With the components and parts that 3D encapsulation technology manufactures, high packaging density is while making the power density of device improve, and the heat that encapsulation unit volume will inevitably be caused to hold increases.Generally, the inefficacy of device is often closely related with its working temperature.The working temperature of device raises, and failure rate also can increase.Irrational thermal design will bring out a series of integrity problem, as there is local overheating, and temperature distributing disproportionation etc.Therefore, adopt 3D encapsulation technology to manufacture components and parts, just must think better of the heat dissipation problem of packaging body.
Chip radiator plays a very crucial effect for the heat radiation improving packaging body, such as there is a kind of chip with radiator, as shown in Figure 1A, in figure, wafer 50 comprises the Semiconductor substrate 100 being positioned at bottom, be formed at the microelectronic component 101 on Semiconductor substrate 100, insulating barrier 102 is positioned in Semiconductor substrate 100, and the contact 105 that photoetching is formed runs through dielectric layer 102 and is connected with microelectronic component 101.Metal level M1 is positioned at the top of the first interconnection layer, radiator 150 is arranged in dielectric layer 120, and described radiator 150 comprises M3 with bond pad 145 with interior connection metal feature, contact 111 and distribution characteristics (RedistributionFeature) 112 is isolated again.Each radiator 150 has large surface area, and scope extends to the edge of wafer from the center of wafer 50, therefore in use heat from the high region of wafer surface temperature as crystal round fringes transmission.Further, the size of each radiator 150 can also expand along an arbitrary major axes orientation from the center of wafer 50 to the outward flange of wafer, as shown in Figure 1B.But this chip structure with radiator, when chip-stacked density is higher, the heat of chip internal still can not well pass.
Therefore, in order to solve deficiency of the prior art, be necessary to propose a kind of new chip radiator.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of semiconductor device, comprising: Semiconductor substrate and the microelectronic component be positioned in described Semiconductor substrate; Metal intermetallic dielectric layer, is positioned on described Semiconductor substrate successively; Metal interconnecting wires, is embedded in described metal intermetallic dielectric layer, and is connected with described microelectronic component; Chain type redundancy metal structure, is positioned at described metal intermetallic dielectric layer, insulate mutually with described metal interconnecting wires; Dielectric layer, is positioned on described metal intermetallic dielectric layer; Bond pad, is positioned at described dielectric layer, and is connected with described microelectronic component by described metal interconnecting wires; Radiator, is positioned at described dielectric layer, insulate mutually with described bond pad, and is connected with described chain type redundancy metal structure.
Preferably, described chain type redundancy metal structure comprises the first redundancy metal and the second redundancy metal, and described first redundancy metal is connected by through hole with described second redundancy metal.
Preferably, the material of described first redundancy metal and the second redundancy metal is selected from the one in copper, tungsten, aluminium, gold and silver.
Preferably, described radiator is not connected with the voltage node of the power supply in circuit or ground connection, to avoid producing unnecessary electric capacity in circuit.
Preferably, described radiator extends to edge from the center of described semiconductor device.
Preferably, described radiator expands to outward flange along an arbitrary major axes orientation from the center of described semiconductor device.
Preferably, on described metal intermetallic dielectric layer, also insulating barrier is comprised.
Preferably, in described insulating barrier, be formed with the first contact to contact with second.
Preferably, described first contact is in order to be connected described radiator with described chain type redundancy metal structure, and described second contact is in order to be connected described bond pad with described metal interconnecting wires.
To sum up, according to the radiator with chain type redundancy metal structure of the present invention, more and darker heat conduction path can be provided, effectively improve the radiating effect of chip.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A is the left view of a kind of chip with radiator of prior art;
Figure 1B is the vertical view of a kind of chip with radiator of prior art;
Fig. 2 is the left view of the chip structure of exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain the technical scheme of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
[exemplary embodiment]
Below in conjunction with schematic diagram, the present invention is described in more detail, wherein denotes the preferred embodiments of the present invention, should be appreciated that those skilled in the art can modify the present invention described here, and still realize advantageous effects of the present invention.
As shown in Figure 2, wafer 20 is provided, described wafer comprises Semiconductor substrate 200, silicon-based substrate can be selected, the illustrative examples containing Si semi-conducting material that can be used as substrate comprises: SiGe (SGOI) on Si, SiGe, SiC, SiGeC, silicon-on-insulator (SOI) or insulator, but is not limited to this.According to manufactured device, substrate can be unadulterated or doping.Microelectronic component 201 is positioned at described Semiconductor substrate 200, although merely illustrate a microelectronic component 201 in figure, the device that also may comprise multiple similar microelectronic component 201 is formed in Semiconductor substrate 200.Described microelectronic component is selected from transistor (such as mos field effect transistor, CMOS transistor, two-carrier engage transistor, high voltage transistor, high frequency transistor etc.), resistance, diode, electric capacity and other component be applicable to.
Comprise the interlayer dielectric layer (inter-layer Dielectric is called for short ILD) 202 be formed on described Semiconductor substrate 200 surface in addition.Interlayer dielectric layer 202 can use such as SiO
2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc.Or, also can be used in the film etc. fluorocarbon (CF) defining SiCN film.Fluorocarbon with fluorine (F) and carbon (C) for main component.Fluorocarbon also can use the material having noncrystal (amorphism) and construct.Interlayer dielectric layer 202 can also use the Porous structures such as such as carbon doped silicon oxide (SiOC).Comprise the contact 203 be formed in interlayer dielectric layer 202 in addition, described contact 203 is by carrying out patterning and the multiple irrigation canals and ditches of etching formation to interlayer dielectric layer.Described irrigation canals and ditches are filled by depositing the metal barrier layer of such as titanium nitride (TiN), deposit the contact plunger layer of such as tungsten afterwards on metal barrier layer.Contact 203 can provide the electrical connection of microelectronic component 201.
Also comprise metal interconnecting wires, be positioned at described first metal intermetallic dielectric layer IMD1 and the second metal intermetallic dielectric layer IMD2, and be connected with described microelectronic component 201.Described first metal dielectric layer IMD1 and the second metal intermetallic dielectric layer IMD2 can be low k dielectric (formation for low k dielectric), also can be ultra low k dielectric materials (formation be ultra-low-k dielectric layer).Generally speaking, low k dielectric refers to that the dielectric material that dielectric constant (k value) is less than 4, ultra low k dielectric materials refer to the dielectric material that dielectric constant (k value) is less than 2.Usual employing chemical gaseous phase spin coating proceeding (SOG), whirl coating technology or chemical vapour deposition technique preparation.
Metal interconnecting layer M1 and M2 is all positioned at the first metal intermetallic dielectric layer IMD1, by the first metal intermetallic dielectric layer IMD1, above-mentioned two metal interconnecting layers are insulated mutually, metal interconnecting layer M2 is connected with metal interconnecting layer M1 by the through hole VIA21 being embedded in the first metal intermetallic dielectric layer IMD1, metal interconnecting layer M3 is connected together by through hole VIA22 and M2, and such metal interconnecting layer M1, metal interconnecting layer M2 also just constitute metal interconnected line structure after being connected by through hole with metal interconnecting layer M3.The integrated circuit technologies such as available such as damascene process An or photoetching/plasma etching process form described metal interconnecting layer.The material of metal interconnecting layer M1, M2, M3 is selected from the one in copper, tungsten, aluminium, gold, silver.In the present embodiment, preferably copper metal is as the material forming metal interconnecting layer and through hole.
Also comprise chain type redundancy metal structure, be positioned at described first metal intermetallic dielectric layer IMD1 and the second metal intermetallic dielectric layer IMD2, insulate mutually with described metal interconnecting wires; In metal interconnecting layer M1 white space, form the first redundancy metal DM1, the second redundancy metal DM2 is formed in the white space of metal interconnecting layer M2, and redundancy metal DM1 is connected by the through hole VIA11 being positioned at the first interlayer dielectric layer IMD1 with redundancy metal DM2.Triple redundance metal DM3 is arranged in the white space of metal interconnecting layer M3, is embedded in the second metal intermetallic dielectric layer IMD2, is connected by through hole VIA12 with redundancy metal DM2.The integrated circuit technologies such as available such as damascene process An or photoetching/plasma etching process are formed.The material of redundancy metal DM1, DM2, DM3 is selected from the one in copper, tungsten, aluminium, gold, silver.Through above-mentioned steps, redundancy metal DM1, DM2, DM3 are connected by through hole, define chain type redundancy metal structure.The method that redundancy metal is filled adopts method well known to those skilled in the art, the metal filled method of such as traditional rule redundancies, as long as white space allows, the method will fill redundancy metal pattern as much as possible, can also be model redundancy metal completion method, the method be divided into very little pane one by one (such as 50 μm chip
2), then calculate the girth of density metal in each pane, finally determine to fill metal pattern according to the parameters of adjacent pane.The embodiment of the present invention does not do concrete restriction to the method that redundancy metal is filled, and all can use as long as can realize content of the present invention.
Although, in a specific embodiment of the present invention, the number of plies of described metal interconnecting layer and redundancy metal is 3 layers, but according to actual conditions, the number of plies of described metal level and redundancy metal can also be other value, and the concrete number of plies is determined according to the technique manufacturing integrated circuit.
Insulating barrier 204 is formed on metal interconnecting layer M3 and triple redundance metal DM3, other wafer circuits together bonded thereto to microelectronic component on wafer 20 and metal interconnecting layer can insulate by described insulating barrier mutually, can also prevent harmful substance from entering the active area of wafer circuit simultaneously.Insulating barrier is by using the inorganic insulation layer of such as silicon oxide layer, silicon nitride layer or silicon oxynitride layer, and the insulating barrier etc. such as comprising the layer of polyvinyl phenol, polyimides or siloxanes etc. is formed.In addition, polyvinyl phenol, polyimides or siloxanes can pass through the formation of droplet discharging method, the art of printing or spin-coating method effectively.Siloxanes according to its structure can be classified into silica glass, alkyl silsesquioxane (alkylsilsesquioxane) polymer, silsesquioxane hydride (silsesquioxane hydride) polymer, alkyl silsesquioxane hydride (alkylsilsesquioxane hydride) polymer, alkyl siloxane polymer, etc.In addition, insulating barrier can be formed with the material comprising the polymer (poly-silazane) with Si-N key.In addition, can these films stacked to form insulating barrier.Contact 206 is formed in described insulating barrier, for connecting wafer active area and bond pad forms electric pathway.Contact 207 for being connected with described redundancy metal structure by radiator, to form the heat conduction via of conducting.
On insulating barrier 204, form dielectric layer 205, the technology for the formation of insulating barrier 204 all can be used for forming dielectric layer 205, and therefore not to repeat here.Engage keyboard 209 and be arranged in dielectric layer 205, by the contact 206 be embedded in insulating barrier 205, bond pad is connected with uppermost metal interconnecting layer M3, aluminium, copper, tungsten, cobalt, gold, silver, signal bronze can be selected from for the formation of the metal engaging keyboard, gold-ashbury metal, indium-billon, Lead-tin alloy or other conductive metals.
Radiator 208 is positioned at dielectric layer 205, and radiator 208 insulate with bond pad, conductive interface and metal interconnecting layer M3 phase.Each radiator 208 has large surface area, and scope extends to the edge of wafer from the center of wafer 20, therefore in use heat from the high region of wafer surface temperature as crystal round fringes transmission.Further, each radiator 208 can also expand along an arbitrary major axes orientation from the center of wafer 20 to the outward flange of wafer.Radiator 208 is connected with chain type redundancy metal structure by contact 207, is namely connected with redundancy metal DM3, forms a kind of radiator with chain type redundancy metal structure.Described radiator is not connected with the voltage node of the power supply (Vcc) in circuit or ground connection, to avoid producing unnecessary electric capacity in circuit.In the present embodiment, redundancy metal can realize the effect that it regulates density metal, can be used as again the heat conduction path of chip cooling.Because redundancy metal is connected by through hole, define described chain type redundancy metal structure, chain type redundancy metal structure is connected with radiator again, metal has good thermal conductivity simultaneously, the heat that so device inside produces can pass to the radiator on upper strata by redundancy metal and through hole, and then heat is passed, therefore more and darker thermally conductive pathways can be provided, and then effectively improve the radiating effect of chip.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a semiconductor device, comprising:
Semiconductor substrate and the microelectronic component be positioned in described Semiconductor substrate;
Metal intermetallic dielectric layer, is positioned on described Semiconductor substrate successively;
Metal interconnecting wires, is embedded in described metal intermetallic dielectric layer, and is connected with described microelectronic component;
Chain type redundancy metal structure, is positioned at described metal intermetallic dielectric layer, insulate mutually with described metal interconnecting wires;
Dielectric layer, is positioned on described metal intermetallic dielectric layer;
Bond pad, is positioned at described dielectric layer, and is connected with described microelectronic component by described metal interconnecting wires;
Radiator, is positioned at described dielectric layer, insulate mutually with described bond pad, and is connected with described chain type redundancy metal structure.
2. semiconductor device as claimed in claim 1, it is characterized in that, described chain type redundancy metal structure comprises the first redundancy metal and the second redundancy metal, and described first redundancy metal is connected by through hole with described second redundancy metal.
3. semiconductor device as claimed in claim 2, it is characterized in that, the material of described first redundancy metal and the second redundancy metal is selected from the one in copper, tungsten, aluminium, gold and silver.
4. semiconductor device as claimed in claim 1, it is characterized in that, described radiator is not connected with the voltage node of the power supply in circuit or ground connection, to avoid producing unnecessary electric capacity in circuit.
5. semiconductor device as claimed in claim 1, it is characterized in that, described radiator extends to edge from the center of described semiconductor device.
6. semiconductor device as claimed in claim 1, it is characterized in that, described radiator expands to outward flange along an arbitrary major axes orientation from the center of described semiconductor device.
7. semiconductor device as claimed in claim 1, is characterized in that, on described metal intermetallic dielectric layer, also comprise insulating barrier.
8. semiconductor device as claimed in claim 7, is characterized in that, be formed with the first contact and contact with second in described insulating barrier.
9. semiconductor device as claimed in claim 8, is characterized in that, described first contact is in order to be connected described radiator with described chain type redundancy metal structure, and described second contact is in order to be connected described bond pad with described metal interconnecting wires.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410140258.1A CN104979305A (en) | 2014-04-09 | 2014-04-09 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410140258.1A CN104979305A (en) | 2014-04-09 | 2014-04-09 | Semiconductor device |
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| CN104979305A true CN104979305A (en) | 2015-10-14 |
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| CN201410140258.1A Pending CN104979305A (en) | 2014-04-09 | 2014-04-09 | Semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810664A (en) * | 2016-04-07 | 2016-07-27 | 上海华力微电子有限公司 | Electromigration structure of test metal line |
| CN106206506A (en) * | 2016-08-08 | 2016-12-07 | 武汉华星光电技术有限公司 | The preparation method of display device, terminal and terminal |
| CN107369670A (en) * | 2017-08-31 | 2017-11-21 | 长江存储科技有限责任公司 | A kind of three-dimensional storage electro-migration testing structure and preparation method thereof |
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| CN1240327A (en) * | 1998-06-23 | 2000-01-05 | 日东电工株式会社 | Installed circuit board structure and multi-layer circuit board for same |
| JP2006294905A (en) * | 2005-04-12 | 2006-10-26 | Sony Corp | Semiconductor device and semiconductor element |
| US20070093066A1 (en) * | 2005-10-24 | 2007-04-26 | Rajashree Baskaran | Stacked wafer or die packaging with enhanced thermal and device performance |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1240327A (en) * | 1998-06-23 | 2000-01-05 | 日东电工株式会社 | Installed circuit board structure and multi-layer circuit board for same |
| JP2006294905A (en) * | 2005-04-12 | 2006-10-26 | Sony Corp | Semiconductor device and semiconductor element |
| US20070093066A1 (en) * | 2005-10-24 | 2007-04-26 | Rajashree Baskaran | Stacked wafer or die packaging with enhanced thermal and device performance |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810664A (en) * | 2016-04-07 | 2016-07-27 | 上海华力微电子有限公司 | Electromigration structure of test metal line |
| CN105810664B (en) * | 2016-04-07 | 2018-06-01 | 上海华力微电子有限公司 | Test the electromigration structure of metal wire |
| CN106206506A (en) * | 2016-08-08 | 2016-12-07 | 武汉华星光电技术有限公司 | The preparation method of display device, terminal and terminal |
| CN107369670A (en) * | 2017-08-31 | 2017-11-21 | 长江存储科技有限责任公司 | A kind of three-dimensional storage electro-migration testing structure and preparation method thereof |
| CN107369670B (en) * | 2017-08-31 | 2019-11-26 | 长江存储科技有限责任公司 | A kind of three-dimensional storage electro-migration testing structure and preparation method thereof |
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Application publication date: 20151014 |