CN102243668A - Thermal-expandability three-dimensional parallel cooling integration method, namely, on-chip system key technology for massively parallel computation - Google Patents

Abstract

The invention belongs to the field of integrated circuit design, and in particular relates to a thermal-expandability three-dimensional parallel cooling integration method. The three-dimensional vertical integration technology proposed at present has disability in thermal expansion. The invention provides a thermal-expandability three-dimensional parallel cooling integration method. In the figure 1 described in the specification, all device layers are parallel with a cooling direction, each device layer is in a shape of a strip, short sides of the strip are parallel to the cooling device, and long sides of the strip are vertical to the cooling device, therefore each device layer is ensured to obtain an independent and shorter cooling channel by virtue of a high-thermal-conductivity silicon substrate (instead of thermal-conducting through holes) installed on the device layer and the fact that the highest temperature of a thermal-expandability three-dimensional parallel cooling integrated chip has no relation with the number of overlapped device layers is ensured. The invention also provides an analysis model for calculating the highest substrate temperature of the thermal-expandability three-dimensional parallel cooling integrated chip, and an analytic expression of the highest substrate temperature of a three-dimensional chip is derived, therefore the thermal expandability of the method disclosed by the invention can be proved theoretically. The method can be widely applied to a three-dimensional integration scheme-based massively parallel computation on-chip system needing good cooling performance urgently.

Description

The parallel heat radiation of three-dimensional integrated approach that can heat expansion: be used for the SOC (system on a chip) gordian technique that large-scale parallel calculates

Technical field:

The invention belongs to the integrated circuit (IC) design field, being specifically related to can the parallel heat radiation of the hot three-dimensional of expanding integrated approach.

Background technology:

The 3D chip technology has obtained extensive studies (with reference to documents 1-10) as a kind of candidate technologies that can continue Moore's Law.In order to improve performance and to reduce design complexities, integrated parallel computing is widely used in high-end calculating field on the sheet, and multinuclear SOC (system on a chip) (MPSoC) has become the important research direction (with reference to documents 2,10) of integrated circuit (IC) design.For pursue the maximization of performance, future must be in chip integrated thousands of computing unit (with reference to documents 10), need higher integrated level, just have only the 3D integrated technology that so high integrated level can be provided.

At present, the vertical integrated technology of 3D superposes common 2D planar chip or device layer perpendicular to heat dissipation channel, and all device layers are parallel to the heating radiator bottom surface, to obtain the improving (with reference to documents 1-5,7-10) of following performance and cost.But the high defective of the vertical integrated technology working temperature of existing 3D is (with reference to documents 7-10) also clearly, can't realize the heat expansion, is subject to too high temperature, can't realize the maximization of performance by stacking of numerous device layers.

The present invention proposes a kind of 3D integrated approach of parallel heat radiation, i.e. all device layers parallel with heat dissipation channel (promptly all device layers are vertical with the heat radiation plane of heat radiator), by the high heat conductance of silicon materials, with the substrate of device layer as heat-conducting layer, to reduce the temperature of transistor channel.Because the heat-conducting layer of each device layer is intrinsic, all can obtain an independence and stable heat dissipation channel, promptly the 3D chip has obtained parallel heat-sinking capability.Simultaneously along with the increase of device layer, the contact area between 3D parallel heat radiation integrated chip and the heat radiator also increases pro rata, can be effectively the heat of 3D chip be conducted, and makes 3D chip substrate temperature remain unchanged.And the analytical model that the highest underlayer temperature of the parallel heat radiation of a kind of 3D of being used for integrated chip calculates has been proposed, and derive the analytical expression of high underlayer temperature of 3D chip, understand the hot extendability of the inventive method in theory.

The present invention adopts 3D vertically to dispel the heat the parallel heat radiation of integrated approach and 3D integrated approach to adopting 10nm technology, area 10cm ², power consumption 200W the three-dimensional integrated heat dissipation design of having carried out of thousand nuclear SOC.When adopting the vertical integrated technology of existing 3D, lock into excessive power dissipation density and the interior temperature difference of layer, have only and adopt traditional bilayer vertically integrated, could satisfy the designing requirement of thermal behavior, but individual layer 5cm ²The kernel area can greatly reduce the yields of chip.Adopt the parallel heat radiation of 3D of the present invention integrated approach, then thousand nuclear SOC can be divided into 20 0.2 * 2.5cm ²Device layer obtains 2.5cm ²Radiating surface, this moment, the highest underlayer temperature of 3D chip was 66.22 ℃, 70 ℃ of maximum temperatures limits less than setting promptly satisfy the designing requirement of thermal behavior; Make 0.2 * 2.5cm simultaneously ²The flawless kernel (KGD) of device layer then can obtain higher yields, evades the San Re ﹠amp that the vertical integrated technology of 3D is faced; Contradiction between the yields under the prerequisite that guarantees yields, satisfies the designing requirement of thermal behavior.

Documents 1: WeerasekeraR, ZhengL R, PamunuwaD, et al, Extending systems-on-chip to the third dimension:performance, cost and technologicaltradeoffs. //Proceedings of Intl.Conf..on Computer Aided Design, San Jose, 2007.11:212-219

Documents 2:Bautista J, Tera-scale Computing and Interconnect Challenges, //Proceedings of 45th Design Automation Conf., San Diego, 2008:665-667

Documents 3:Mitsumasa K, Takafumi F, Tetsu T, Three-dimensional integration technology and integrated system.In Proceeding of ASP-DAC, Taibei.2009.1:409-415

Documents 4: ZhouP Q, Ma Y C, Zhuoyuan LiZ Y, et al, 3D-STAF:scalable temperature and leakage aware floorplanning for three-dimensionalintegrated circuits. //Proceedings of IEEE/ACM ICCAD, San Jose, 2007.11:590-597

Documents 5:Goplen B, and Sapatnekar S S, Placement of3D ICs with hermal and Interlayer Via Considerations, //Proceedings of 44th DesignAutomation Conf., San Diego, 2007:626-631

Documents 6:Jayaseelan R, Mitra T, Dynamic Thermal Management via Architectural Adaptation, //Proceeding of 46th Design Automation Conf., USA.2009.6:484-489

Documents 7:Haensch W, Why Should We Do 3D Integration? //Proceedings of45th Design Automation Conf., San Diego, 2008:674-675

Documents 8:Sapatnekar S S, Addressing Thermal and Power Delivery Bottlenecks in 3D Circuits. //Proceeding of ASP-DAC, Taibei.2009.1:423-428

Documents 9:Mizunuma H, Yang C L, Lu Y C.Thermal Modeling for 3D-ICs with Integrated Microchannel Cooling//Proceedings of Intl.Conf.onComputer Aided Design, San Jose, 2009:256-263

Documents 10:Borkar S.Thousand Core Chips-A Technology Perspective//Proceedings of44th Design Automation Conf., San Diego, 2007:746-749

Summary of the invention:

Can't realize the heat expansion at existing three-dimensional perpendicular integrated technology, be subject to too high temperature, can't realize the maximized defective of performance by stacking of numerous device layers, the present invention proposes a kind of have can heat expansion the parallel heat radiation of 3D integrated approach, be that each device layer is parallel to heat dissipation direction, device layer is a strip, its minor face is parallel to heat dissipation direction, its long limit is perpendicular to heat dissipation direction, so just guaranteed that each device layer all can rely on the high-termal conductivity silicon substrate (rather than heat conduction via hole) that self had, obtain independent and short heat dissipation channel, guarantee that the parallel heat radiation of 3D integrated chip maximum temperature is irrelevant with the device number of plies that is superposeed.And the analytical model that the highest underlayer temperature of the parallel heat radiation of a kind of 3D of being used for integrated chip calculates has been proposed, and derive the analytical expression of high underlayer temperature of 3D chip, understand the hot extendability of the inventive method in theory.

Wherein existing three-dimensional perpendicular integrated technology can't realize that the heat expansion is characterised in that: the highest underlayer temperature T of the vertical integrated chip of 3D _ChipIt is quadratic polynomial function about its device number of plies M that superposes.Therefore, there is a fatal technological deficiency in the vertical integrated chip of 3D, promptly can't realize the heat expansion, and under the prerequisite that limits maximum operating temperature, the vertical integrated technology of the 3D more device layer that is difficult to superpose can't be realized parallel computation on the large-scale sheet.

Wherein have and can be characterised in that by the parallel heat radiation of the hot 3D that expands integrated approach: as shown in Figure 1, the parallel integrated approach that dispels the heat of 3D has two important advantages and guarantees its hot extendability.(1) all device layers all have the silicon substrate of conventional thickness among the figure, because silicon materials are a kind of good Heat Conduction Materials, each device layer all can be transmitted to heat radiator with the heat that it produces by its silicon substrate, so each device layer all has oneself independently heat dissipation channel, so the 3D integrated approach that the present invention proposes has parallel heat-sinking capability.(2) for the parallel heat radiation of 3D integrated chip, because the contact area between it and the heat radiator is proportional to the device number of plies, so when its integrated more device layer, the contact area between it and the heat radiator also increases the ability of increasing thermal convection on year-on-year basis.In contrast, when the integrated device number of plies when increasing, the contact area of the vertical integrated chip of 3D and heat radiator is not increase but.

The analytical model that the highest underlayer temperature of the parallel heat radiation of wherein a kind of 3D of being used for integrated chip calculates is characterised in that: as shown in Figure 2,

1) establishes parallel all device layers that dispel the heat integrated chip of 3D and have identical power consumption P _D, also have area identical and dimensions, its area A _D=H * L, then the power dissipation density of device layer is P _d=P _D/ A _D=P _D/ (H * L).

2) with conventional substrate thickness h ₃For unit is K heat unit with device layer height H uniform subdivision, its computing formula is as follows: K=H ÷ h ₃Standard thermal resistance on the axis is r _d, can represent with following formula: r _d=h ₃÷ κ _Si=h ₃÷ 1.0=h ₃

3) the power dissipation density P of i heat unit _dPass on the heat dissipation channel (axis) of substrate by horizontal thermal resistance respectively, because the distance from the device layer to the axis is 0.5h ₃So horizontal thermal resistance is 0.5r _d

4) the power dissipation density P of i heat unit _dAfter passing to the axis, converge (the i-1) * P that transmits from above _dPower dissipation density, the power dissipation density that passes is i * P downwards _d

5) to fin conductive, the standard thermal resistance is r to the heat on the axis along the axis _d, owing to the distance from 1 temperature nodes of heat radiator surface of contact to the is 0.5h ₃So, with heat radiator thermal resistance r ₀The thermal resistance that links to each other is 0.5r _d

6) power dissipation density at heat-conducting layer and kernel surface of contact place is K * P _d

7) equivalent thermal resistance of fan, heat radiator, heat-conducting layer is r ₀

8) because each device layer has separately independently heat dissipation channel, so the thermal dissipating path of each device layer is separate.

Wherein the 3D chip the analytical expression of high underlayer temperature be characterised in that: (1) T _ChipIrrelevant with device number of plies M, i.e. the parallel heat radiation of 3D integrated approach has tangible hot extensibility.(2) T _ChipDirect ratio and device layer power dissipation density P _d(3) T _ChipDirect ratio and K square because K=H/h ₃So, along with the increase of device layer height H, T _ChipCan present the increase of square amount.Therefore, can be by turning down P _dWith the value of H, reach and reduce T _ChipPurpose.For the device layer of strip, its height is very little, therefore can guarantee lower T _Chip

Description of drawings:

Fig. 1 is the wiring layout of the parallel heat radiation of many device layers 3D integrated technology.

Fig. 2 is the distributed heat analytical model of the parallel heat radiation of 3D integrated chip.

Fig. 3 is the signal of 2D chip cooling structure.

Fig. 4 is the thermoanalytical chip core discretize signal of full chip 3D.

Fig. 5 is the static heat analytical model that the 2D chip is simplified.

Fig. 6 is the schematic cross-section of the vertical heat radiation chip of 3D.

Fig. 7 is the signal of device layer domain.

Fig. 8 is vertically the dispel the heat static heat analytical model of integrated chip of many device layers 3D.

Embodiment:

The present invention proposes a kind of have can heat expansion the parallel heat radiation of 3D integrated approach, and understand hot extendability of the present invention in theory.Concrete steps are as follows: carry out the full chip 3D static heat analysis of 2D chip, and the static heat analytical model of 2D chip is simplified.The static heat that the present invention is based on the 2D chip is analyzed simplified model, and at first the heat dissipation problem to the vertical integrated chip of 3D has carried out modelling, derives the highest underlayer temperature T of accurate Calculation 3D chip _ChipAnalytical expression, point out T _ChipBe about vertically the superpose quadratic polynomial function of number of plies M of 3D chip, proved that theoretically the vertical integrated technology of existing 3D has the inherent limitation that heat can not be expanded.And the analytical model that the highest underlayer temperature of the parallel heat radiation of a kind of 3D of being used for integrated chip calculates proposed, and derive the analytical expression of high underlayer temperature of 3D chip according to this model, understand the hot extendability of the inventive method in theory.

In the said method, described " carrying out the full chip 3D static heat analysis of 2D chip " is as follows:

Fig. 3 has provided complete 2D chip cooling structure (in fact the radiator structure of 3D chip also is the same), under heat radiator, be heat-conducting layer, heat-conducting layer can be further divided into heat-conducting layer 1 (TIM1) and heat-conducting layer 2 (TIM2), the heat-conducting layer below is exactly the kernel (die) of chip, the heat-conductive characteristic of heat-conducting layer is far above air, can improve the heat-conductive characteristic between kernel and the heat radiator effectively, so kernel+heat-conducting layer+heat radiator has constituted main heat dissipation channel.The kernel below is the encapsulation base of chip, and the encapsulation base below is a chip carrier socket, and the chip carrier socket below then is printed circuit board (PCB), and kernel+encapsulation base+chip carrier socket+PCB has constituted auxilliary heat dissipation channel.The heat-sinking capability of main heat dissipation channel is better than auxilliary heat dissipation channel several magnitude, so in full chip 3D heat is analyzed, main heat dissipation channel all only is discussed, and is ignored auxilliary heat dissipation channel, below main heat dissipation channel is called for short heat dissipation channel.

In the thermoanalytical discretize of chip core 3D, the present invention is divided into n by shown in Figure 4 with kernel ₁(x axle) * n ₂(y axle) * n ₃(z axle) individual square shape quality unit (be called for short matter unit) (with reference to documents 5,11), each matter unit with its central point temperature as its temperature.In static (steady-state) 3D heat is analyzed (with reference to documents 3), the kernel internal temperature distributes according to Poisson equation (Poisson ' s equation):

${\▿}^{2}T\left(r\right)=-\frac{E\left(r\right)}{\mathrm{\κ}\left(r\right)}---\left(1\right)$

(x, y z) are a particle to r=in the formula, and T (r) is r point temperature (℃), κ (r) is r point thermal conductivity coefficient (W/ (cm * ℃)), and E (r) is that r is ordered the energy density (W/cm that is produced ³).3D heat has 6 boundary conditions in analyzing, because chip core is embedded in the encapsulation base, emphasizes main heat dissipation channel, ignores the consequence that auxilliary heat dissipation channel brought to be: have only border upwards to have thermal convection among Fig. 3, there is not thermal convection in all the other 5 borders.

$\left\{\begin{array}{c}\frac{\∂T\left(r\right)}{\∂x}{|}_{x=0}=\frac{\∂T\left(r\right)}{\∂x}{|}_{x=n_1}=\frac{\∂T\left(r\right)}{\∂y}{|}_{y=0}=\frac{\∂T\left(r\right)}{\∂y}{|}_{y=n_2}=\frac{\∂T\left(r\right)}{\∂z}{|}_{z=0}=0\\ {\mathrm{\ρ}}_{n_3}\frac{\∂T\left(r\right)}{\∂z}{|}_{z=n_3}=h(T\left(r\right){|}_{z=n_3}-T_a)\end{array}\right.---\left(2\right)$

T in the formula _aBe the temperature of heat-conducting layer 2, ρ _N3Be n ₃The z axle thermal conductance of layer, h (W/ (cm ²* ℃)) be the coefficient of heat convection.For formula (1) and formula (2),, just can obtain the node temperature solving equation if the temperature deviation of consecutive point is replaced with temperature difference.

G·T＝P (3)

G is thermal conductance matrix (W/cm in the formula ²℃), T be temperature vector (℃), P is power dissipation density vector (W/cm ²).As shown in Figure 4, kernel being dispersed is N=n ₁(x axle) * n ₂(y axle) * n ₃(z axle) individual square shape matter unit, then T and P are the N dimensional vectors, G is that (dimension of N * N) matrix, because matter unit can carry out heat conduction by 6 faces and adjacent matter unit, according to kirchhoff electric current theorem, G is 7 diagonal matrix.

In the said method, described " the static heat analytical model to the 2D chip is simplified " is as follows:

Because full chip 3D static heat analysis is comparatively complicated, so in some application scenarios, can analyze simplification to it.In Fig. 4, suppose that the power dissipation density of chip core is evenly distributed, silicon substrate, heat-conducting layer, heat radiator, and fan uniform heat conduction, we just can obtain a simple serial conduction model, as shown in Figure 5.In the direct simplified model shown in Fig. 5 (a), silicon substrate, heat-conducting layer, heat radiator, and the capacity of heat transmission of fan be separately thermal resistance by equivalence, be respectively r _Bulk, r _Cond, r _Sink, r _Fan, the power dissipation density P of device layer is the heat that device layer produced.In the degree of depth simplified model shown in Fig. 5 (b), heat-conducting layer, heat radiator, and the thermal resistance of fan be merged into a total equivalent resistance r ₀, i.e. r ₀=r _Cond+ r _Sink+ r _FanMore than two figure can form turn to following formula:

T _chip-T _a＝(r _bulk+r _cond+r _sink+r _fan)P＝(r _bulk+r ₀)P＝r _systemP (4)

R in the formula _System=r _Bulk+ r ₀Be system's equivalent thermal resistance of chip cooling system, T _aBe environment temperature.The Xeon 7400 series processors handbooks (with reference to documents 13) of Intel Company have provided following temperature funtion (a best temperature curve):

T _chip＝0.146TDP+45 (5)

TDP in the formula (Thermal Design Power) is the TDP of chip, and mxm. is 130W, T _aIt is 45 ℃.Can obtain as drawing a conclusion from formula (5): the maximum operating temperature of (1) chip is 64 ℃.(2) because its kernel area is A _Chip=1.43cm ², the thermal resistance r of the pairing system of its unit area then _System=0.146 * 1.43=0.209cm ²K/W.

In the said method, described " the vertical integrated chip of 3D " is as follows:

Fig. 6 has provided the structural drawing of the vertical integrated chip of 3D and the principle of work of vertical heat radiation thereof.In the vertical heat radiation chip of 3D, the 1st device layer has the silicon substrate of conventional thickness, and other device layer has cuts thin substrate, to shorten the 3D interconnect length.3D interconnection comprises two class TSV, i.e. signal TSV and heat conduction TSV, and signal TSV passes device layer and silicon substrate, carry out the signal transmission layer by layer at two devices, in order to prevent the leakage of marking current, between signal TSV and the silicon substrate insulation course is arranged, so the thermal conductivity of signal TSV is poor; And heat conduction TSV only passes device layer, carries out heat conduction between two adjacent silicon substrates, requires to adopt the extraordinary material of thermal conductivity, as copper.

The vertical heat radiation principle of work of the vertical integrated chip of 3D is as follows: the heat that each device layer produced conducts to the 1st device layer from the 5th device layer, successively through heat-conducting layer, heat radiator, fan, spills in the environment at last, and this path has constituted heat dissipation channel.Therefore, in the vertical heat radiation chip of 3D, because the direction of contrary heat dissipation channel, from the 1st device layer to the 5 device layers, its underlayer temperature raises successively, and the underlayer temperature of the 5th device layer is the highest, is called as the highest underlayer temperature T of 3D chip _ChipIn like manner, for the vertical heat radiation chip of 3D of M device layer of a stack, its M device layer has the highest underlayer temperature.

Fig. 7 has provided the domain signal of device layer.For a foursquare device layer, its length of side is D _Die, its area A _Die=D _Die* D _DieSeveral 3D vertical routing channels are arranged in the device layer, and all TSV cloth are placed in the 3D vertical routing channel, and wherein signal TSV preferentially lays, and all remaining TSV are all as heat conduction TSV.Device layer is divided into several device blocks equably by the 3D vertical routing channel, and the heat that device blocks produced is derived by heat conduction TSV, and the width of each module is L _BlockBecause the module centers line from the 3D vertical routing channel farthest, so the module centers line generally is to have temperature the highest in the module.

In the said method, described " heat dissipation problem to the vertical integrated chip of 3D has carried out modelling, derives the highest underlayer temperature T of accurate Calculation 3D chip _ChipAnalytical expression " as follows:

In view of the vertical integrated technology of present 3D is that common 2D planar chip or device layer are superposeed perpendicular to heat dissipation channel, the static heat that the present invention is based on the 2D chip is analyzed simplified model, modelling is carried out in analysis to the vertical heat radiation chip static heat of 3D, points out that existing three-dimensional perpendicular integrated technology can't realize heat expansion.And adopt traditional continuous lax excessively (SOR) algorithm (with reference to documents 11) that above analytical analysis model is verified.

Above, analysis is carried out modelling and can be finished in order to following flow process to the vertical heat radiation chip static heat of 3D:

1) at first, for to the vertical heat radiation chip static heat of 3D analysis carry out modelling, the present invention carries out following hypothesis: the device blocks shown in (1) Fig. 4 has uniform power dissipation density; (2), have only heat conduction TSV the heat of a silicon substrate to be transmitted to its adjacent silicon substrate of low temperature at device layer; (3) heat conduction TSV evenly distributes in the 3D vertical routing channel.Can draw as drawing a conclusion according to above hypothesis: (1) in same device layer, heat conduction TSV has identical temperature, conducts identical heat; (2) in each device blocks, because the module centers line from the 3D vertical routing channel farthest, so the module centers line has temperature the highest in the module.

2) ask T _{I, block}: for i device layer (as Fig. 7), it to cut thin substrate thickness be h ₂, its device blocks center line is taken as T to the temperature difference between the heat conduction TSV _{I, block}After the thermoanalytical discretize of 3D, from the device blocks center line to total 0.5L the heat conduction TSV _Block/ h ₂The individual length of side is h ₂Square block matter unit.The thermal resistance of each matter unit is r _Thin=h ₂/ k _Si, k wherein _SiBe the thermal conductivity of silicon materials, k _SiUnit is W/ (cm a ℃).If the power dissipation density of all device blocks is P on this device layer _i, then can be with T _{I, block}Form turns to:

$T_{i,\mathrm{block}}=\underset{j=1}{\overset{0.5L/h_2}{\mathrm{\Σ}}}(j\×r_{\mathrm{thin}}\×P_i)-0.5\×(\frac{0.5L_{\mathrm{block}}}{h_2}{r}_{\mathrm{thin}}\×P_i)$

$=\frac{{(0.5L_{\mathrm{block}}/h_2)}^2}{2}{r}_{\mathrm{thin}}{P}_i=\frac{{(0.5L_{\mathrm{block}}/h_2)}^2}{2}\×\frac{h_2}{k_{\mathrm{Si}}}{P}_i=\frac{L_{\mathrm{block}}^2{P}_i}{8h_2{k}_{\mathrm{Si}}}---\left(6\right)$

Can draw as drawing a conclusion according to formula (6): (1) reduction of device module width L _BlockOr the thickness h of rich substrate is cut in thickening ₂Can reduce T _{I, block}, but, reduce L for the vertical integrated design of 3D _BlockWith thickening h ₂All there is technical difficulty.(2) reducing power dissipation density is P _iAlso can reduce T _{I, block}, can suitably reduce P by the design that lays L2 or L3 high-speed cache at device layer _i, but acutely reduce P _iAlso unrealistic.

3) ask T _{I, TSV}: as shown in Figure 8, with formalization T _{I, block}Required plane is discrete to be compared, and the temperature of each device layer heat conduction TSV is carried out formalization then needs to carry out the 3D discrete processes, and wherein adopting the length of side is h ₃Square block matter unit be h to thickness ₃Conventional substrate carry out discretize, the thermal resistance r of each matter unit ₁=h ₃/ k _Si, and establish heat-conducting layer, heat radiator, and the equivalent thermal resistance of fan be r ₀For the device layer of i＞1, get r _iFor thickness is h ₁I device layer and the+1 device layer cut the equivalent thermal resistance of thin substrate, if do not consider to cut the sideways expansion effect of thermal conducting path in the thin substrate, can directly adopt following formula to calculate r _i:

$r_i=\frac{A_{\mathrm{die}}}{A_{\mathrm{TSV}}}\×(\frac{h_1}{k_{\mathrm{Cu}}}+\frac{h_2}{k_{\mathrm{Si}}})---\left(7\right)$

A in the formula _DieAnd A _TSVBe respectively the area of device layer and 3D vertical routing channel.In the present invention's research, we suppose all TSV all as heat conduction TSV, adopt copper product to make heat conduction TSV, k in the formula _CuIt is the temperature conductivity of copper product.Handle based on 3D discretize shown in Figure 8, can be with the heat conduction TSV temperature T of i device layer _{I, TSV}Form turns to:

$T_{i,\mathrm{TSV}}=T_a+(r_0+r_1)\underset{j=1}{\overset{M}{\mathrm{\Σ}}}{P}_j+\underset{j=2}{\overset{i}{\mathrm{\Σ}}}\left[r_j\underset{k=j}{\overset{M}{\mathrm{\Σ}}}{P}_k\right]---\left(8\right)$

M is the device number of plies that the vertical heat radiation chip of 3D is superposeed in the formula, T _aBe environment temperature.

4) determine the highest underlayer temperature T of the vertical heat radiation chip of 3D _Chip: with T _{I, block}And T _{I, TSV}Carrying out that addition can obtain can be with the highest underlayer temperature T of i device layer _i:

$T_i=T_{i,\mathrm{TSV}}+T_{i,\mathrm{block}}=T_a+(r_0+r_1)\underset{j=1}{\overset{M}{\mathrm{\Σ}}}{P}_j+\underset{j=2}{\overset{i}{\mathrm{\Σ}}}\left[r_j\underset{k=j}{\overset{M}{\mathrm{\Σ}}}{P}_k\right]+\frac{L^2{P}_i}{8h_2{k}_{\mathrm{Si}}}---\left(9\right)$

With T _MThe highest underlayer temperature T as the vertical heat radiation chip of 3D _Chip, then can obtain following formula:

$T_{\mathrm{chip}}=T_M=T_a+(r_0+r_1)\underset{j=1}{\overset{M}{\mathrm{\Σ}}}{P}_j+\underset{j=2}{\overset{M}{\mathrm{\Σ}}}\left[r_j\underset{k=j}{\overset{M}{\mathrm{\Σ}}}{P}_k\right]+\frac{L^2{P}_i}{8h_2{k}_{\mathrm{Si}}}=T_{\mathrm{chip}}^{2D}+T_{\mathrm{chip}}^{3D}---\left(10\right)$

Wherein

$T_{\mathrm{chip}}^{2D}=T_a+(r_0+r_1)\underset{j=1}{\overset{M}{\mathrm{\Σ}}}{P}_j---\left(11\right)$

$T_{\mathrm{chip}}^{3D}=\underset{j=2}{\overset{M}{\mathrm{\Σ}}}\left[r_j\underset{k=j}{\overset{M}{\mathrm{\Σ}}}{P}_k\right]+\frac{L^2{P}_i}{8h_2{k}_{\mathrm{Si}}}---\left(12\right)$

T in the formula _Chip ^2DBe 2D equivalence underlayer temperature, after promptly all device layer power dissipation density being added up, its summation be added to the highest underlayer temperature that first device layer is produced; T _Chip ^3DIt is the temperature increment that the vertical stack of device layer 3D is brought.According to formula (11) and (12), when device number of plies M that 3D superposeed increases, T _Chip ^2DPresent linear increase, T _Chip ^3DThen presenting quadratic power increases, i.e. the highest underlayer temperature T of the vertical integrated chip of 3D _ChipIt is the multi-form function of secondary about its device number of plies M that superposes.Therefore, there is a fatal technological deficiency in the vertical integrated chip of 3D, promptly can't realize the heat expansion, and under the prerequisite that limits maximum operating temperature, the vertical integrated technology of the 3D more device layer that is difficult to superpose can't be realized parallel computation on the large-scale sheet.

Above, adopt traditional continuous lax excessively (SOR) algorithm (with reference to documents 11) that above analytical analysis model is verified and can be finished in order to following flow process:

1) asks T _{I, block}: based on vertical integrated technique of the given 3D of table 2 and design parameter, at first, calculate

And calculate

2) ask T _{I, TSV}: then can calculate r ₁=h ₃/ k _Si=0.05cm ℃/W, and employing formula (7) calculates r _i=0.205cm ℃/W, employing formula (8) calculates the heat conduction TSV temperature T of i device layer _{I, TSV}:

$T_{i,\mathrm{TSV}}=45+0.209\×(10+5\×M)+\underset{j=2}{\overset{i}{\mathrm{\Σ}}}[0.205\×(M-j+1)\×5]$

$=45+1.045\×(2+M)+1.025\×\underset{j=2}{\overset{i}{\mathrm{\Σ}}}(M-j+1)---\left(14\right)$

3) determine the highest underlayer temperature T of the vertical heat radiation chip of 3D _Chip: based on formula (10), (13) (14) can calculate the highest underlayer temperature T of the vertical integrated chip of 3D _Chip:

$T_{\mathrm{chip}}=T_{M,\mathrm{TSV}}+T_{M,\mathrm{block}}=45+1.045\×(2+M)+1.025\×\underset{j=2}{\overset{M}{\mathrm{\Σ}}}(M-j+1)+4.75$

$=49.75+1.045\×(2+M)+0.5125\×M\×(M-1)=51.84+0.5325M+0.5125M^2---\left(15\right)$

4) parameter setting: for the vertical heat radiation chip of 3D of integrated different components number of plies M, employing formula (15) can directly calculate the highest underlayer temperature T _ChipFor the vertical integrated chip of 3D to stack 2-10 layer designs, the present invention sets correlation parameter according to document (with reference to documents 12-14), lists in the table 1.The first device layer power dissipation density P that wherein contacts with heat radiator ₁Be 15W/cm ², the power dissipation density of other device layer is 5W/cm ², the device layer thickness h ₁Be taken as 5um, cut the thin silicon substrates thickness h ₂Be taken as 50um, conventional silicon substrate thickness h ₃Be taken as 500um, device layer square kernel area A _DieBe 1.0cm ², length of side D _DieBe 1.0cm, device layer 3D interconnecting channel area A _TSVBe 0.025cm ², device layer has N _Block=5 functional modules, environment temperature T _aIt is 45 ℃.

5) checking result data analysis: the T that will adopt the present invention to calculate _ChipThe data rows that data and SOR modeling algorithm are found the solution is in table 2.From the table data as can be seen, along with the increase of the vertical heat radiation chip of the 3D integrated device number of plies M of institute, T _ChipIncrease fast, present quafric curve character, this shows that the vertical integrated technology of 3D can't carry out the heat expansion, exists fatal thermal behavior defective; Simultaneously, compare T that analytic model of the present invention calculates with the exact value that adopts the SOR algorithm simulation to go out _ChipMaximum error less than 1.7%, this shows that model of the present invention is enough accurate.Therefore, model of the present invention can directly be used for calculating the highest underlayer temperature T of the vertical integrated chip of 3D of an integrated M device layer _Chip, the thermal behavior of the vertical integrated design of analysis 3D.

Table 1 is used for the whole technologies and the design parameter (with reference to documents 12-14) of the vertical integrated chip thermal design of 3D

Table 2 is about the vertical integrated chip T of 3D _ChipAlgorithm relatively

In the said method, described " a kind of have can heat expansion the parallel heat radiation of 3D integrated approach " be as follows:

As shown in Figure 1, each device layer is parallel to heat dissipation direction, device layer is a strip, its minor face is parallel to heat dissipation direction, its long limit is perpendicular to heat dissipation direction, so just guaranteed that each device layer all can rely on high-termal conductivity silicon substrate (rather than heat conduction via hole) that self had, obtain independent and short heat dissipation channel, guarantees that the parallel heat radiation of 3D integrated chip maximum temperature is irrelevant with the device number of plies that is superposeed.

In the said method, described " a kind of analytical model that is used for the highest underlayer temperature calculating of the parallel heat radiation of 3D integrated chip " is as follows:

In the distributed heat analytical modelization of the parallel radiating element layer of 3D chip, the present invention carries out discretize by following flow process:

1) establishes parallel all device layers that dispel the heat integrated chip of 3D and have identical power consumption P _D, also have area identical and dimensions, its area A _D=H * L, then the power dissipation density of device layer is P _d=P _D/ A _D=P _D/ (H * L).

2) with conventional substrate thickness h ₃For unit is K heat unit with device layer height H uniform subdivision, its computing formula is as follows:

K＝H÷h ₃ (16)

Standard thermal resistance on the axis is r _d, can represent with following formula:

r _d＝h ₃÷κ _si＝h ₃÷1.0＝h ₃ (17)

3) the power dissipation density P of i heat unit _dPass on the heat dissipation channel (axis) of substrate by horizontal thermal resistance respectively, because the distance from the device layer to the axis is 0.5h ₃So horizontal thermal resistance is 0.5r _d

4) the power dissipation density P of i heat unit _dAfter passing to the axis, converge (the i-1) * P that transmits from above _dPower dissipation density, the power dissipation density that passes is i * P downwards _d

5) to fin conductive, the standard thermal resistance is r to the heat on the axis along the axis _d, owing to the distance from 1 temperature nodes of heat radiator surface of contact to the is 0.5h ₃So, with heat radiator thermal resistance r ₀The thermal resistance that links to each other is 0.5r _d

6) power dissipation density at heat-conducting layer and kernel surface of contact place is K * P _d

7) equivalent thermal resistance of fan, heat radiator, heat-conducting layer is r ₀

8) because each device layer has separately independently heat dissipation channel, so the thermal dissipating path of each device layer is separate.

In the said method, described " the 3D chip is the analytical expression of high underlayer temperature " is as follows:

1) the highest underlayer temperature T of the parallel heat radiation of derivation 3D integrated chip _Chip: as shown in Figure 2, the highest underlayer temperature T of the parallel heat radiation of 3D integrated chip _ChipIrrelevant with device number of plies M, only relevant with power dissipation density, the dimensions of device layer, so the parallel heat radiation of 3D integrated technology has hot extensibility.According to modelling result shown in Figure 2, can calculate T _Chip:

$T_{\mathrm{chip}}=T_a+0.5r_d\×P_d+\underset{i=1}{\overset{K-1}{\mathrm{\Σ}}}\{i\×r_d\×P_d\}+(0.5r_d+r_0)\×K\×P_d$

$=T_a+0.5(K^2+1)\×r_d\×P_d+r_0\×K\×P_d---\left(18\right)$

According to the parameter in the table 1, can obtain r _d=0.05cm ℃/W and r ₀=0.159cm ℃/W, and then formula (18) is rewritten as T _Chip=T _a+ 0.5 (K ²+ 1) 0.05P _d+ K * 0.159P _d=T _a+ (0.025+0.159K+0.025K ²) P _d(19)

From formula (19) can obtain about the parallel heat radiation of 3D integrated approach as drawing a conclusion.(1) T _ChipIrrelevant with device number of plies M, i.e. the parallel heat radiation of 3D integrated approach has tangible hot extensibility.(2) T _ChipDirect ratio and device layer power dissipation density P _d(3) T _ChipDirect ratio and K square because K=H/h ₃So, along with the increase of device layer height H, T _ChipCan present the increase of square amount.Therefore, can be by turning down P _dWith the value of H, reach and reduce T _ChipPurpose.For the device layer of strip, its height is very little, therefore can guarantee lower T _Chip

2) accuracy of check analysis analytic model of the present invention: in order to verify the thermoanalytical analytic model of the above 3D that derives parallel heat radiation integrated chip, the present invention adopts traditional SOR method for solving and analytic model of the present invention to find the solution T respectively respectively _Chip, device layer power dissipation density P wherein _dBe taken as 10W/cm ²In the SOR method for solving, for the accuracy that guarantees that SOR finds the solution, the employing length of side is 50um (rather than the h of 500um ₃) square block the parallel heat radiation of 3D integrated chip is carried out discretize.Corresponding to different K values, all T _ChipThe value of finding the solution (unit for ℃) listed in the table 3.As shown in table 3, along with the continuous increase of K value, T _ChipAlso increase fast, and present the Changing Pattern of quafric curve, show T _ChipAnd the relation that has the quadratic polynomial function between the K (and H).Simultaneously, compare with the SOR algorithm, analytic model of the present invention is very accurate, and its maximum error is less than 0.17%, and therefore analytic model of the present invention can be used for the thermal behavior of the integrated design of the parallel heat radiation of express-analysis 3D.

Concrete steps of the present invention are as follows:

1) carries out the full chip 3D static heat analysis of 2D chip, and the static heat analytical model of 2D chip is simplified.

2) modelling is carried out in analysis to the vertical heat radiation chip static heat of 3D, points out that existing three-dimensional perpendicular integrated technology can't realize heat expansion.

3) propose a kind of analytical model that the highest underlayer temperature of the parallel heat radiation of 3D integrated chip calculates that is used for, derive the analytical expression of high underlayer temperature of 3D chip according to this model.

Table 3 is about the highest underlayer temperature T of 3D parallel heat radiation integrated chip _ChipMethod relatively

Documents 11:

Processor 7400Series Manual, Http:// www.intel.com/product/processor.

Documents 12:Goplen B, and Sapatnekar S S, Placement of3D ICs with hermal and Interlayer Via Considerations, //Proceedings ot 44th DesignAutomation Conf., San Diego, 2007:626-631

Documents 13:Iverson R B, LeCoz Y L, Kleveland B, et al.A Multi-Scale Random-Walk Thermal-Analysis Methodology for Complex IC-InterconnectSystems. //Proceeding of Simulation of Semiconductor Processes and Devices, Seattle, 2000:84-86

Documents 14:Zhong Y, Wong M D F.Fast Algorithms for IR Drop Analysis in Large Power Grid. //Proceedings of Intl.Conf.on Computer AidedDesign, San Jose, 2005:351-357

Simulation result:

The three-dimensional integrated thermal design of thousand nuclear SOC

For Xeon 7400 system processors that present employing 45nm produces, its kernel area is 1.43cm ², maximum power dissipation is 130W, comprises 6 processor units.According to Moore's Law, IC technology will improve for 4 generations in 10 years, i.e. 45nm → 32nm → 22nm → 15nm → 10nm, and integrated level improves 16 times, can be at 1.43cm ²Integrated 96 nuclears on the area, the monokaryon power consumption can be controlled near the 1W.Lock into the quantum effect of metal-oxide-semiconductor technology, the later technology of 10nm promotes and will face physics limit, is difficult to technology be promoted again.In order to continue Moore's Law, the number of plies of 3D integrated chip will constantly increase, and keeping the continuous lifting of chip integration, how thousand nuclear SOC be carried out that 3D is integrated just to become significant studying a question (with reference to documents 7-10).

In the 3D of thousand nuclear SOC was integrated, we can suppose that chip adopts 10nm technology, and the monokaryon area is 0.01cm ²(be 1mm ²), the monokaryon power consumption is 0.2W (adopting the super low-power consumption design).According to above hypothesis, the kernel area of thousand nuclear SOC is 10cm ², power consumption is 200W.If also adopt traditional 2D chip to design, the highest underlayer temperature that can calculate it according to formula (4) and formula (5) is 49.38 ℃, much smaller than 70 ℃ of temperature limits of thermal design, but its 10cm ²The kernel area but can cause the strange low consequence of yields, so traditional 2D chip design scheme is inadvisable.Below we will adopt the parallel heat radiation of the vertical integrated technology of 3D and 3D integrated technology respectively, the three-dimensional integrated thermal design problem of thousand nuclear SOC will be studied, research focus concentrates on the highest underlayer temperature T of chip _Chip

1) the existing vertical Integrated Solution of 3D

In the vertical integrated design of 3D, establishing the first device layer power dissipation density that contacts with heat radiator is P ₁, the power dissipation density of other device layer is P _i, P ₁=3P _iThe present invention uses the heat dissipation problem to the vertical integrated chip of 3D to carry out the highest underlayer temperature T that modeled formula calculates the vertical integrated design proposal of all 3D _ChipThermal design parameter corresponding to the vertical integrated design proposal of 3D of 2-5 device layer all is listed in the table 4.Along with the increase of the integrated device number of plies M of 3D chip institute, each device layer area A as can be seen _DieConstantly reduce, the contact area that means 3D chip and heat radiator is also in continuous minimizing, while P ₁And P _iA small amount of increase is also arranged, but the ratio between the two remains unchanged, but the T of the vertical integrated chip of 3D _ChipBut significantly increasing.Have only and adopt two device layer Integrated Solutions commonly used at present, could guarantee T _Chip=64.91 ℃, satisfy T _Chip＜70 ℃ designing requirement, but for two device layer Integrated Solutions, because the kernel area of its device layer is 5.0cm ², large-area kernel like this will significantly reduce the yields of manufacturing.Therefore, the heat that locks into the vertical integrated technology of 3D is extensibility not, and there is the contradiction that is difficult to be in harmonious proportion in the vertical Integrated Solutions of 3D of thousand nuclear SOC between thermal behavior and yields.

The thermal design parameter of the vertical integrated chip of table 43D

2) the parallel heat radiation of 3D Integrated Solution

Table 5 is corresponding to different P _dT with the parallel integrated chip that dispels the heat of the 3D of K _ChipValue (unit ℃)

The thermal design parameter of the parallel heat radiation integrated chip of table 6 3D design proposal

For the integrated design of the parallel heat radiation of 3D, the present invention adopts formula (14) to calculate: corresponding to different P _dT with the parallel integrated chip that dispels the heat of the 3D of K _ChipValue, all parameters are listed in the table 5.Along with K=H/h ₃Increase, T _ChipConstantly increase, must reduce the value of K and H, could reduce T _ChipIn table 5, the pairing design proposal of green area all can guarantee T _Chip＜70 ℃ designing requirement.For the kernel area is 10cm ², power consumption be 200W thousand nuclear SOC, suppose that its power dissipation density is even, then P _d=20W/cm ², when getting K=4, T _Chip=66.22 ℃, satisfy T _Chip＜70 ℃ designing requirement.When K=4, H=K * h ₃=4 * 500um=0.2cm.Reasonable for the length/height ratio that guarantees device layer, the present invention gets L=2.5cm, and this moment, the length/height ratio of kernel was 12.5, the kernel area A _Die=0.5cm ², promptly need integrated 20 flawless kernels could obtain the 10cm of thousand nuclear SOC ²The kernel area.The contact area A of this 3D parallel heat radiation integrated chip and heat radiator _Interface=M * h ₃* L=20 * 0.05 * 2.5=2.5cm ², show that the parallel heat radiation of 3D integrated chip has enough big thermal convection area.Table 6 has been listed employing P _d=20W/cm ²With the parallel heat radiation of the 3D of K=4 integrated corresponding to all thermal design parameters.

Compare with the vertical integrated technology of existing 3D, the parallel heat radiation of the 3D that the present invention proposes integrated approach demonstrates following advantage: (1) hot extendability, each device layer all has oneself heat dissipation channel alone, and the contact area between parallel heat radiation chip of 3D and the heat radiator is proportional to the number M of device layer, has all guaranteed T _ChipThe increase with M does not increase.(2) need not heat conduction TSV, can not bring the overhead of kernel area and TSV.(3) rate of good quality rate, the parallel heat radiation chip of 3D needs the flawless kernel of a lot of layers of parallel stack, and flawless kernel smaller core area guarantees that it has very high yields, and then guarantees that the parallel heat radiation chip of 3D has higher yields.

Claims (4)

1. One kind have can heat expansion the parallel heat radiation of 3D integrated approach, it is characterized in that each device layer is parallel to heat dissipation direction, device layer is a strip, its minor face is parallel to heat dissipation direction, its long limit is perpendicular to heat dissipation direction, so just guaranteed that each device layer all can rely on high-termal conductivity silicon substrate (rather than heat conduction via hole) that self had, obtain independent and short heat dissipation channel, guarantees that the parallel heat radiation of 3D integrated chip maximum temperature is irrelevant with the device number of plies that is superposeed.And the analytical model that the highest underlayer temperature of the parallel heat radiation of a kind of 3D of being used for integrated chip calculates has been proposed, and derive the analytical expression of high underlayer temperature of 3D chip, understand the hot extendability of the inventive method in theory.
2. 2. as claimed in claim 1 a kind of have can heat expansion the parallel heat radiation of 3D integrated approach, wherein have can the heat expansion the parallel heat radiation of 3D integrated approach be characterised in that: the parallel heat radiation of 3D integrated approach has two important advantages and guarantees its hot extendability.(1) all device layers all have the silicon substrate of conventional thickness, because silicon materials are a kind of good Heat Conduction Materials, each device layer all can be transmitted to heat radiator with the heat that it produces by its silicon substrate, so each device layer all has oneself independently heat dissipation channel, so the 3D integrated approach that the present invention proposes has parallel heat-sinking capability.(2) for the parallel heat radiation of 3D integrated chip, because the contact area between it and the heat radiator is proportional to the device number of plies, so when its integrated more device layer, the contact area between it and the heat radiator also increases the ability of increasing thermal convection on year-on-year basis.In contrast, when the integrated device number of plies when increasing, the contact area of the vertical integrated chip of 3D and heat radiator is not increase but.
3. 3. as claimed in claim 1 a kind of have can heat expansion the parallel heat radiation of 3D integrated approach, the analytical model that the highest underlayer temperature of the parallel heat radiation of wherein a kind of 3D of being used for integrated chip calculates is characterised in that: all device layers of 1) establishing the parallel heat radiation of 3D integrated chip have identical power consumption P _D, also have area identical and dimensions, its area A _D=H * L, then the power dissipation density of device layer is P _d=P _D/ A _D=P _D/ (H * L).

   2) with conventional substrate thickness h ₃For unit is K heat unit with device layer height H uniform subdivision, its computing formula is as follows: K=H ÷ h ₃Standard thermal resistance on the axis is r _d, can represent with following formula: r _d=h ₃÷ κ _Si=h ₃÷ 1.0=h ₃

   3) the power dissipation density P of i heat unit _dPass on the heat dissipation channel (axis) of substrate by horizontal thermal resistance respectively, because the distance from the device layer to the axis is 0.5h ₃So horizontal thermal resistance is 0.5r _d

   4) the power dissipation density P of i heat unit _dAfter passing to the axis, converge (the i-1) * P that transmits from above _dPower dissipation density, the power dissipation density that passes is i * P downwards _d

   5) to fin conductive, the standard thermal resistance is r to the heat on the axis along the axis _d, owing to the distance from 1 temperature nodes of heat radiator surface of contact to the is 0.5h ₃So, with heat radiator thermal resistance r ₀The thermal resistance that links to each other is 0.5r _d

   6) power dissipation density at heat-conducting layer and kernel surface of contact place is K * P _d

   7) equivalent thermal resistance of fan, heat radiator, heat-conducting layer is r ₀

   8) because each device layer has separately independently heat dissipation channel, so the thermal dissipating path of each device layer is separate.
4. 4. as claimed in claim 1 a kind of have can heat expansion the parallel heat radiation of 3D integrated approach, wherein the 3D chip the analytical expression of high underlayer temperature be characterised in that: 1) T _ChipIrrelevant with device number of plies M, i.e. the parallel heat radiation of 3D integrated approach has tangible hot extensibility.2) T _ChipDirect ratio and device layer power dissipation density P _d3) with conventional substrate thickness h ₃For unit is K heat unit with device layer height H uniform subdivision, T _ChipDirect ratio and K square because K=H/h ₃So, along with the increase of device layer height H, T _ChipCan present the increase of square amount.Therefore, can be by turning down P _dWith the value of H, reach and reduce T _ChipPurpose.For the device layer of strip, its height is very little, therefore can guarantee lower T _Chip

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