CN104951600A - Photoetch-friendly dummy metal fill method - Google Patents
Photoetch-friendly dummy metal fill method Download PDFInfo
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- CN104951600A CN104951600A CN201510304216.1A CN201510304216A CN104951600A CN 104951600 A CN104951600 A CN 104951600A CN 201510304216 A CN201510304216 A CN 201510304216A CN 104951600 A CN104951600 A CN 104951600A
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Abstract
The invention provides a photoetch-friendly dummy metal fill method and belongs to the field of integrated circuit manufacturability design and electronic design automation. Dummy metal serves as printable auxiliary patterns, a pre-filling model is provided regarding T-shaped and L-shaped via holes and the ordinary line end photoetch distortion problem, and a corresponding dummy metal pre-fill scheme is given. On the basis, the invention further provides the photoetch-friendly metal dummy fill process, the steps of carrying out pre-fill, conventional fill and pre-fill removal are carried out on an original layout, and the pre-fill scheme is revised by comparing the photoetch distortion situations before and after pre-fill removal. By means of the dummy metal fill method, local photoetch distortion correction can be achieved, the local metal intensity can be improved, and the influence of the dummy metal on photoetch and flatness is balanced.
Description
Technical field
The present invention relates to ic manufacturability design and field of electron design automation, be specifically related to a kind of integrated circuit (IC) etching friendly redundancy metal fill method.
Background technology
Current IC manufacturing generally adopts the Damascus technics based on copper-connection.Along with the continuous progress of semiconductor technology node, the improvement speed of material and facility can not meet the performance, the power consumption requirements that continue to increase far away.Photoetching (Lithography) and chemically mechanical polishing (Chemical Mechanical Polishing, CMP) process deviation caused has become the significant bottleneck that restriction semicon industry develops by Moore's Law, also makes it become the main goal in research of manufacturability design.
CMP technology is the process means simultaneously realizing chip surface planarization by chemical corrosion and ultramicron physical grinding.The nonhomogeneous hardness that metal level and dielectric layer exist have impact on polishing velocity, causes metal dish effect (dishing) and dielectric abrasion (erosion) defect, is degrading CMP effect, and by lamination effects upper strata metal.In order to address this problem, deviser generally adopts the method inserting redundancy metal, by controlling size, the spacing of filling metal, realizes the consistance of metallic pattern density, thus flatness after optimizing CMP.The sign-off that chip production side also inserts for redundancy metal proposes the requirement of density metal aspect.
The insertion of redundancy metal brings new problem.First, the introducing extreme influence sequential of parasitic parameter and coupling capacitance.Researcher constantly proposes new parasitic parameter extraction means and the insertion method based on sequential, wishes while accurate simulation result, realizes minimizing of metal insertion and coupling capacitance by the shape of appropriate design redundancy metal and position.Secondly, because exposure wavelength is close to the theoretical limit of etching system, redundancy metal is filled the photoetching impact caused and also more and more cannot be ignored.On the one hand, redundancy metal changes original layout graphics environment and pattern density, can worsen optical distortion by optical approach effect, causes the problems such as broken string, bridging, turning are round and smooth, line segment indentation.For the via pattern comparatively easily producing distortion, these distortion may cause fatal logic error, and for common signal wire, distortion can change resistance capacitance and affect sequential equally.On the other hand, redundancy metal optimizes flatness after CMP, and this avoids optics problem out of focus to a certain extent.Chip is more smooth, and the distance between chip surface and best focal point is more stable, and the figure carved distortion compared with simulation result is also less.How to balance the impact of redundancy metal on these two kinds of optical effects, realize the filling of photoetching friendly redundancy metal and there is realistic meaning.Applicant finds, the filling research of current redundancy metal too concentrates on the optimal anchor direction of density and sequential, and considers that the filling that photoetching affects does not cause enough attention.
Sub-resolution assist features (Sub-resolution Assist Feature, SRAF) scattering strip is also referred to as, resolution enhance technology (Resolution Enhancement Technology conventional in photoetching process, RET), the photoetching of the much higher crystal silicon grid of Line-width precision requirement is usually used in.Scattering strip in lithography mask version is enough wide with the depth of focus increasing original litho pattern, weaken its distortion degree, simultaneously enough narrowly again introduce unplanned device to avoid being carved into chip, which increase design difficulty and the mask cost of scattering strip, be not suitable for the photoetching reparation of metal level.The reparation scale of metal wire is large and accuracy requirement is lower slightly, there is not the printability constraint of auxiliary pattern simultaneously, applicant thinks redundancy metal can be adopted as the auxiliary pattern of printability, improves local metal density, realize the balance of photoetching and CMP while optimization photoetching distortion.
Summary of the invention
Filling to solve integrated circuit redundancy metal the photoetching aberration problems caused, the present invention proposes a kind of redundancy metal fill method of photoetching friendly, specifically comprising:
A pre-filled model is repaired in photoetching for T font layout patterns, it is characterized in that: the T font layout patterns structure 100 and the redundancy metal 101 that comprise an any direction, the position relationship of redundancy metal and T font domain as shown in Figure 1.
A pre-filled model is repaired in photoetching for L font layout patterns, it is characterized in that: the L font layout patterns structure 200 and the redundancy metal 201 that comprise an any direction, the position relationship of redundancy metal and L font domain as shown in Figure 2.
A pre-filled model is repaired in photoetching for line end layout patterns, it is characterized in that: the line end layout patterns structure 300 and the redundancy metal 301 that comprise an any direction, the position relationship of redundancy metal and line end domain as shown in Figure 3.
For a pre-filled method for T font, L font via hole and common line end, said method comprising the steps of:
(1) provide integrated circuit diagram to be filled, described integrated circuit diagram comprises at least one structured metal layer, at least one in T font, L font and line end structure, has the region of enough inserting pre-filled figure simultaneously;
(2) according to the original layout figure in the pre-filled model of summary of the invention 1 ~ 3, Graphic Pattern Matching is carried out to existing domain;
(3) the original layout figure coordinate in three kinds of matching results is extracted respectively;
(4) respectively according to the redundancy metal graph position in the pre-filled model of summary of the invention 1 ~ 3, amendment coupling figure coordinate, obtains pre-filled figure coordinate;
(5) carry out pre-filled according to pre-filled figure coordinate to existing domain.
The present invention comprises further: the region of enough inserting pre-filled figure in step (1) refers to, after inserting pre-filled figure, still enough meets DRC rule request according to model in summary of the invention (1).
The present invention comprises further: in step (2), Graphic Pattern Matching is realized by Graphic Pattern Matching eda tool, and matching content not only comprises figure itself, also comprises for meeting the necessary packing space of DRC rule.
A kind of photoetching friendly redundancy metal fill method, is characterized in that, said method comprising the steps of:
(1) provide integrated circuit diagram to be filled, described integrated circuit diagram comprises at least one structured metal layer, and comprises the region can filling redundancy metal;
(2) according to step described in summary of the invention 4, redundancy metal carries out to domain to be filled pre-filled;
(3) carry out conventional redundancy metal to fill, and carry out lithography simulation;
(4) remove all pre-filled redundancy metal figures, and carry out lithography simulation;
(5) pre-filled redundancy metal and common filling redundancy metal coordinate is extracted;
(6) utilize the redundancy metal coordinate in step (5), in the lithographic results of step (3), remove the lithographic hotspots information of redundancy metal;
(7) utilize the redundancy metal coordinate in step (5), in the lithographic results of step (4), remove the lithographic hotspots information of redundancy metal;
(8) result of comparison step (6) and (7), determines whether to retain pre-filled figure;
(9) will determine that the pre-filled figure retained refills in domain.
The present invention comprises further: the lithography simulation in step (3), (4) is realized by photoetching close friend design eda tool.
The present invention comprises further: the metal filled filling comprising any density based, sequential or other functions of the conventional redundancy in step (3), demand fulfillment corresponding DRC density rule request.
The present invention comprises further: wherein the photoetching distortion information of corresponding with (7) for step (6) hotspot location compares by step (8), comprise the PVI information etc. of the pitch information of minimum spacing focus, the width information of minimum widith focus, the indentation information of line end focus and all focuses, if the result of correspondence position step (6) is better than step (7), the then pre-filled reservation of this point, otherwise point is pre-filled does not retain for this.
Compared with prior art, the present invention has following features:
The present invention utilizes pre-filled redundancy metal as printability auxiliary pattern, while the original special lithographic hotspots of reparation, improves local density metal, flatness after optimization CMP.
The photoetching friendly fill method that the present invention proposes only needs Twi-lithography emulate, a feedback adjusting, simply efficiently, is applicable to the not high but interconnecting metal layer that loading is large of reparation accuracy requirement.
In addition, Conventional filler part of the present invention has higher dirigibility, can carry out density based, sequential according to demand, improve the multiple filling of power consumption, and affects the effect of optimization of common filling to flatness and sequential hardly.
Accompanying drawing explanation
Fig. 1 is the pre-filled model of T font domain redundancy metal of the present invention, and wherein, 100 is original T font domain, and 101 is pre-filled metal;
Fig. 2 is the pre-filled model of L font domain redundancy metal of the present invention, and wherein, 200 is original L font domain, and 201 is pre-filled metal;
Fig. 3 is the pre-filled model of line end domain redundancy metal of the present invention, and wherein, 300 is original line end domain, and 301 is pre-filled metal;
Fig. 4 is the pre-filled schematic flow sheet of redundancy metal of the present invention;
Fig. 5 is that photoetching friendly redundancy metal of the present invention fills schematic flow sheet;
Fig. 6 is the invention process case T font layout extraction and the pre-filled concrete dimensional parameters of redundancy metal, and unit is nm, and dotted portion is the white space considering DRC rule request coupling, and figure dashed boundaries is non-matching border;
Fig. 7 is the invention process case L font layout extraction and the pre-filled dimensional parameters of redundancy metal, and unit is nm, and dotted portion is the white space considering DRC rule request coupling, and figure dashed boundaries is non-matching border;
Fig. 8 is the invention process case line end layout extraction and the pre-filled concrete dimensional parameters of redundancy metal, and unit is nm, and dotted portion is the white space considering DRC rule request coupling, and figure dashed boundaries is non-matching border.
Concrete case study on implementation
Below in conjunction with concrete case study on implementation to technical scheme of the present invention carry out complete, clearly describe.Obviously, described example is only a part of the present invention and not all.Based on the case study on implementation in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, all belongs to protection scope of the present invention.
First, provide 45nm technique integrated circuit diagram to be filled with GDSII form, this integrated circuit diagram comprises a M3 structured metal layer.
Secondly, utilize Graphic Pattern Matching eda software to set up T font, L font, line end domain model bank respectively, design parameter is arranged as can be seen from figures 6 to 8.For meeting sign-off requirement, model considers M3 metal level minimum spacing problem, coupling corresponding domain structure while have matched enough white spaces (as shown in phantom in FIG.), with ensure pre-filled after meet DRC rule request.Adopt boundary scheme to mate, namely special pattern border allow coupling particular range size (as in Fig. 6 60 ~ 150 border), special pattern border can be used as virtual boundary and does not participate in mating (as dashed boundaries in Fig. 6).Utilize Perl language scripts to extract the coordinate of final matching results, and generate redundancy metal position coordinates according to Fig. 6 ~ the 8 Suo Shi.
After obtaining redundancy metal position coordinates, the eda software utilizing redundancy metal to insert carry out respectively based on the pre-filled of model and width be 1 times of minimum widith, spacing is that the conventional s2w1 of 2 times of minimum spacings fills, and carry out LFD lithography simulation, obtain LEC focus result.After removing all pre-filled metals, then carry out LFD lithography simulation, obtain LEC focus result.Perl script is utilized to compare the line end indentation parameter max of same position LEC focus.If this lithographic hotspots to remove pre-filled front max index little, then retain the pre-filled coordinate in this place, otherwise then removes the pre-filled coordinate in this place.The pre-filled coordinate file processed is utilized heavily to enter to fill back in domain by pre-filled metal.
Below for the result of study of the invention process case: s2w1 represents, common filling (Selecting parameter: be 2 times of minimum spacings between redundancy metal and signal wire is directly performed to M3 layer, redundancy metal width is 1 times of minimum widith, spacing is 1 times of minimum spacing) after domain, LFD_s2w1 represents that performing to M3 layer the photoetching friendly redundancy metal that the present invention proposes fills the domain after flow process (the same s2w1 of Selecting parameter).
Table 1 illustrates original layout hotspot's classification statistics, and T font, L font focus number account for 69.25% of LEC focus sum, account for 72.29% of MWC focus sum.Although might not meet the requirement of filling around these figures, fill flow process for LFD, such domain has very large reparative potential.Contrast table 2, T font and the pre-filled number of L font, all much larger than the figure number producing focus, may being protected because filling the domain producing distortion for potential, being filled risk in the hope of reducing.Filled by LFD, final loading reduces 1.62% compared with common filling.
Table 1 original layout hotspot's classification is added up
Table 2 loading contrasts
Table 3 compared for common filling flow process and LFD flow process each stage lithographic hotspots number.After pre-filled end (T, L-type domain are pre-filled rear), repair specific original figure focus 329 altogether, repair rate reaches 57.52%.But after carrying out LFD Conventional filler; the number repaired declines, and the new focus of generation increases, and Conventional filler disturbs to pre-filled effect; but with directly carry out filling compared with (common s2w1 fill after), repairing effect and protected effect are all fairly obvious.Through feedback adjusting, net result (LFD_s2w1 fills rear) display, original LEC focus number have dropped 20.70%, and more common filling have dropped 8.90%, LEC focus sum and adds 1.25%, and more common filling have dropped 45.08%.Original MWC focus number have dropped 62.65%, and more common filling have dropped 27.06%, MWC focus sum and have dropped 10.84%, and more common filling have dropped 19.13%.Original MSC focus number have dropped 85.71%, MSC focus sum and increase only 2, illustrates and fills on MSC impact not quite.It can thus be appreciated that LFD fills flow process can repair original layout focus to a certain extent, effectively reduce because filling the new focus brought simultaneously.
Table 3 LEC, MWC, MSC focus number contrasts
Table 4 is flatness maximum difference contrast after CMP.Emulation adopts CMP to analyze emulation eda tool, and min_max represents the highest minimum 2 distance difference in simulating area.Result shows, flatness difference comparatively original layout improves 84.19%, with common s2w1 fill maintain an equal level, its distribution trend and common filling basically identical and more concentrated.
Flatness maximum difference situation contrast table after table 4 CMP
Claims (7)
1. a photoetching friendly redundancy metal fill method, is characterized in that comprising the following steps:
(1) provide integrated circuit diagram to be filled, described integrated circuit diagram comprises at least one structured metal layer, and comprises the region can filling redundancy metal;
(2) redundancy metal carries out to domain to be filled pre-filled;
(3) carry out conventional redundancy metal to fill, and carry out lithography simulation;
(4) remove all pre-filled redundancy metal figures, and carry out lithography simulation;
(5) pre-filled redundancy metal and common filling redundancy metal coordinate is extracted;
(6) utilize the redundancy metal coordinate in step (5), in the lithographic results of step (3), remove the lithographic hotspots information of redundancy metal;
(7) utilize the redundancy metal coordinate in step (5), in the lithographic results of step (4), remove the lithographic hotspots information of redundancy metal;
(8) result of comparison step (6) and (7), determines whether to retain pre-filled figure;
(9) will determine that the pre-filled figure retained refills in domain.
2. a kind of photoetching friendly redundancy metal fill method as claimed in claim 1, is characterized in that, step (2) is described, and to carry out redundancy metal to domain to be filled pre-filled, comprises the following steps:
(1) provide integrated circuit diagram to be filled, described integrated circuit diagram comprises at least one structured metal layer, at least one in T font, L font and line end structure, has the region of enough inserting pre-filled figure simultaneously;
(2) carry out Graphic Pattern Matching according to the original layout figure in following three kinds of pre-filled models to existing domain, three kinds of pre-filled models refer to:
1) pre-filled model is repaired in the photoetching for T font layout patterns, comprises T font layout patterns structure and a redundancy metal of an any direction;
2) pre-filled model is repaired in the photoetching for L font layout patterns, comprises L font layout patterns structure and a redundancy metal of an any direction;
3) pre-filled model is repaired in the photoetching for line end layout patterns, comprises line end layout patterns structure and a redundancy metal of an any direction;
(3) the original layout figure coordinate in three kinds of matching results is extracted respectively;
(4) respectively according to the redundancy metal graph position in three kinds of pre-filled models, amendment coupling figure coordinate, obtains pre-filled figure coordinate;
(5) carry out pre-filled according to pre-filled figure coordinate to existing domain.
3. a kind of photoetching friendly redundancy metal fill method as claimed in claim 1 or 2, is characterized in that, the lithography simulation in step (3), (4) is realized by photoetching close friend design eda tool.
4. a kind of photoetching friendly redundancy metal fill method as claimed in claim 1 or 2, it is characterized in that, the metal filled filling comprising any density based, sequential or other functions of conventional redundancy in step (3), demand fulfillment corresponding DRC density rule request.
5. a kind of photoetching friendly redundancy metal fill method as claimed in claim 1 or 2, it is characterized in that, wherein the photoetching distortion information of corresponding with (7) for step (6) hotspot location compares by step (8), comprise the PVI information etc. of the pitch information of minimum spacing focus, the width information of minimum widith focus, the indentation information of line end focus and all focuses, if the result of correspondence position step (6) is better than step (7), the then pre-filled reservation of this point, otherwise point is pre-filled does not retain for this.
6. a kind of photoetching friendly redundancy metal fill method as claimed in claim 2, it is characterized in that, the region of enough inserting pre-filled figure in step (1) refers to, after inserting pre-filled figure, still enough meets DRC rule request according to pre-filled model.
7. a kind of photoetching friendly redundancy metal fill method as described in claim 2 or 6, it is characterized in that, in step (2), Graphic Pattern Matching is realized by Graphic Pattern Matching eda tool, matching content not only comprises figure itself, also comprises for meeting the necessary packing space of DRC rule.
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| CN113312873A (en) * | 2021-05-24 | 2021-08-27 | 海光信息技术股份有限公司 | Circuit layout design method and device, mask plate and electronic equipment |
| CN115688669A (en) * | 2022-12-27 | 2023-02-03 | 华芯程(杭州)科技有限公司 | Layout design method, device and equipment for metal layer connecting through hole |
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| CN107153720B (en) * | 2016-03-02 | 2020-10-16 | 中国科学院微电子研究所 | Method and system for filling redundant metal |
| CN107153720A (en) * | 2016-03-02 | 2017-09-12 | 中国科学院微电子研究所 | A kind of method and system of redundancy metal filling |
| CN108122267B (en) * | 2016-11-30 | 2021-05-11 | 中国科学院微电子研究所 | Filling method and device for redundant metal |
| CN108122267A (en) * | 2016-11-30 | 2018-06-05 | 中国科学院微电子研究所 | The fill method and device of a kind of redundancy metal |
| CN108009352A (en) * | 2017-11-30 | 2018-05-08 | 上海华力微电子有限公司 | A kind of filling flow of lithography layout and the design method of photo etched mask |
| CN108536944A (en) * | 2018-04-02 | 2018-09-14 | 郑州云海信息技术有限公司 | The method and system of overlapping via is checked in a kind of placement-and-routing |
| CN109345509A (en) * | 2018-08-31 | 2019-02-15 | 上海华力微电子有限公司 | A kind of polycrystal layer photoetching process hotspot lookup method |
| CN109345509B (en) * | 2018-08-31 | 2022-02-08 | 上海华力微电子有限公司 | Method for searching hot spots in multi-crystal layer photoetching process |
| CN110658696A (en) * | 2019-09-30 | 2020-01-07 | 上海华力集成电路制造有限公司 | Photoetching friendliness design checking method for disconnection hot spot |
| CN110658696B (en) * | 2019-09-30 | 2021-04-13 | 上海华力集成电路制造有限公司 | Photoetching friendliness design checking method for disconnection hot spot |
| CN112434484A (en) * | 2020-12-02 | 2021-03-02 | 长江存储科技有限责任公司 | Redundancy filling method |
| CN113312873A (en) * | 2021-05-24 | 2021-08-27 | 海光信息技术股份有限公司 | Circuit layout design method and device, mask plate and electronic equipment |
| CN115688669A (en) * | 2022-12-27 | 2023-02-03 | 华芯程(杭州)科技有限公司 | Layout design method, device and equipment for metal layer connecting through hole |
| CN115688669B (en) * | 2022-12-27 | 2023-04-07 | 华芯程(杭州)科技有限公司 | Layout design method, device and equipment for metal layer connecting through hole |
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