CN104951600B - A kind of photoetching friendly redundancy metal fill method - Google Patents
A kind of photoetching friendly redundancy metal fill method Download PDFInfo
- Publication number
- CN104951600B CN104951600B CN201510304216.1A CN201510304216A CN104951600B CN 104951600 B CN104951600 B CN 104951600B CN 201510304216 A CN201510304216 A CN 201510304216A CN 104951600 B CN104951600 B CN 104951600B
- Authority
- CN
- China
- Prior art keywords
- filled
- photoetching
- redundancy metal
- metal
- redundancy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000002184 metal Substances 0.000 title claims abstract description 100
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 100
- 238000001259 photo etching Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000011049 filling Methods 0.000 claims abstract description 29
- 238000013461 design Methods 0.000 claims abstract description 10
- 238000001459 lithography Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 claims description 10
- 238000004088 simulation Methods 0.000 claims description 10
- 230000006870 function Effects 0.000 claims description 2
- 238000012986 modification Methods 0.000 claims description 2
- 230000004048 modification Effects 0.000 claims description 2
- 238000012856 packing Methods 0.000 claims description 2
- 239000000945 filler Substances 0.000 abstract description 3
- 230000004075 alteration Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 7
- 238000000605 extraction Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000011068 loading method Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 238000013515 script Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012966 insertion method Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002633 protecting effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a kind of photoetching friendly redundancy metal fill method, belongs to ic manufacturability design and field of electron design automation.The present invention is used as printability secondary graphics by the use of redundancy metal, there is provided for the pre-filled model of T fonts, L fonts via and common line end photoetching aberration problems, and gives corresponding redundancy metal pre-filled scheme.On this basis, present invention also offers a kind of photoetching friendly redundancy metal to fill flow, carries out pre-filled, Conventional filler respectively to original layout and removes pre-filling step, removes pre-filled front and rear photoetching distortion situation by contrast, corrects pre-filled scheme.Using redundancy metal fill method of the present invention, it is possible to achieve local photoetching distortion correction, improve local metal density, balance redundancy metal is to photoetching and the influence of flatness.
Description
Technical field
The present invention relates to ic manufacturability design and field of electron design automation, and in particular to the integrated electricity of one kind
Road photoetching friendly redundancy metal fill method.
Background technology
Current IC manufacturing generally uses the Damascus technics based on copper-connection.With semiconductor technology section
The continuous progress of point, the improvement speed of material and facility far can not meet the performance, the power consumption requirements that continue to increase.Photoetching
(Lithography) and chemically mechanical polishing (Chemical Mechanical Polishing, CMP) caused by process deviation
Turn into the significant bottleneck that limitation semicon industry presses Moore's Law development, it is turned into the main of manufacturability design and is ground
Study carefully target.
CMP technique be and meanwhile by chemical attack and ultramicron physical grinding realize chip surface planarization technique hand
Section.Metal level have impact on polishing velocity with nonhomogeneous hardness existing for dielectric layer, cause metal dish effect (dishing) and electricity to be situated between
Matter denudes (erosion) defect, is degrading CMP effects, and pass through lamination effects upper strata metal.Asked to solve this
Topic, designer generally using the methods of insertion redundancy metal, size, the spacing of metal are filled by controlling, realizes metallic pattern
The uniformity of density, so as to optimize flatness after CMP.It is close that the sign-off that chip production side also inserts for redundancy metal proposes metal
Requirement in terms of degree.
The insertion of redundancy metal brings the problem of new.First, the introducing of parasitic parameter and coupled capacitor significantly impacts
Sequential.Researcher constantly proposes new parasitic parameter extraction means and the insertion method based on sequential, it is desirable in accurate simulation knot
While fruit, the minimum of metal insertion and coupled capacitor is realized by the shape and position that rationally design redundancy metal.Its
Secondary, because exposure wavelength is close to the theoretical limit of etching system, the photoetching caused by redundancy metal filling influences also increasingly
It can not ignore.On the one hand, redundancy metal changes original layout graphics environment and pattern density, may pass through optical approach effect
Deteriorate optical distortion, cause the problems such as broken string, bridging, turning are round and smooth, line segment is retracted.Via for being relatively easy to produce distortion
Figure, these distortion may cause fatal logic error, and for common signal wire, distortion can vary in resistance electricity
Hold and influence sequential.On the other hand, redundancy metal optimizes flatness after CMP, and it is out of focus that this avoids optics to a certain extent
Problem.Chip is more flat, and chip surface and the distance between best focal point are more stable, and the figure carved is compared with simulation result
Distortion is also smaller.Influence of the redundancy metal to both optical effects how is balanced, realizes that photoetching friendly redundancy metal is filled
With realistic meaning.It has been found that the filling research of redundancy metal excessively concentrates on the optimization direction of density and sequential at present,
And consider the filling of photoetching influence and do not cause enough attention.
Sub-resolution assist features (Sub-resolution Assist Feature, SRAF) are also referred to as scattering strip, are
The RET (Resolution Enhancement Technology, RET) commonly used in photoetching process, is usually used in
Line-width precision requires the photoetching of high polysilicon gate.Scattering strip in lithography mask version wants sufficiently wide to increase original lithography figure
Depth of focus, weaken its distortion degree, at the same it is sufficiently narrow again introduce unplanned device to avoid being carved into chip, which increase
The design difficulty and mask cost of scattering strip, the photoetching reparation of uncomfortable metal layer.The reparation scale of metal wire is big and precision will
Ask lower slightly, while constrained in the absence of the printability of secondary graphics, applicant thinks to use redundancy metal as printability
Secondary graphics, improve local metal density while photoetching distortion is optimized, realize photoetching and CMP balance.
The content of the invention
In order to solve photoetching aberration problems caused by the filling of integrated circuit redundancy metal, the present invention proposes a kind of photoetching friend
The redundancy metal fill method of good type, is specifically included：
Pre-filled model is repaired in a kind of photoetching for T font layout patterns, it is characterised in that：Include an any direction
T font layout patterns structure 100 and a redundancy metal 101, position relationship such as Fig. 1 institutes of redundancy metal and T font domains
Show.
Pre-filled model is repaired in a kind of photoetching for L font layout patterns, it is characterised in that：Include an any direction
L font layout patterns structure 200 and a redundancy metal 201, position relationship such as Fig. 2 institutes of redundancy metal and L font domains
Show.
Pre-filled model is repaired in a kind of photoetching for line end layout patterns, it is characterised in that：Include an any direction
Line end layout patterns structure 300 and a redundancy metal 301, the position relationship of redundancy metal and line end domain it is as shown in Figure 3.
A kind of pre-filled method for T fonts, L fonts via and common line end, it the described method comprises the following steps：
(1) integrated circuit diagram to be filled is provided, the integrated circuit diagram includes at least one structured metal layer, T words
At least one of type, L fonts and line end structure, while there is the region for inserting pre-filled figure enough；
(2) Graphic Pattern Matching is carried out to existing domain according to the original layout figure in 1~3 pre-filled model of the content of the invention；
(3) the original layout figure coordinate in three kinds of matching results is extracted respectively；
(4) sat respectively according to the redundancy metal graph position in 1~3 pre-filled model of the content of the invention, modification matching figure
Mark, obtains pre-filled figure coordinate；
(5) existing domain is carried out according to pre-filled figure coordinate pre-filled.
The present invention further comprises：The region for inserting pre-filled figure in step (1) enough refers to, according to the content of the invention
(1) after model inserts pre-filled figure in, still meet that DRC rules require enough.
The present invention further comprises：Graphic Pattern Matching is realized by Graphic Pattern Matching eda tool in step (2), in matching
Holding not only includes figure in itself, also includes to meet packing space necessary to DRC rules.
A kind of photoetching friendly redundancy metal fill method, it is characterised in that the described method comprises the following steps：
(1) integrated circuit diagram to be filled is provided, the integrated circuit diagram includes at least one structured metal layer, and wraps
Containing the region that can fill redundancy metal；
(2) according to step described in the content of the invention 4, it is pre-filled that redundancy metal is carried out to domain to be filled；
(3) conventional redundancy metal filling is carried out, and carries out lithography simulation；
(4) remove all pre-filled redundancy metal figures, and carry out lithography simulation；
(5) pre-filled redundancy metal and common filling redundancy metal coordinate are extracted；
(6) the redundancy metal coordinate in step (5) is utilized, removes the light of redundancy metal in the lithographic results of step (3)
Carve hot information；
(7) the redundancy metal coordinate in step (5) is utilized, removes the light of redundancy metal in the lithographic results of step (4)
Carve hot information；
(8) comparison step (6) and the result of (7), it is determined whether retain pre-filled figure；
(9) the pre-filled figure for determining to retain is refilled in domain.
The present invention further comprises：Lithography simulation in step (3), (4) is realized by the friendly design eda tool of photoetching
's.
The present invention further comprises：Conventional redundancy in step (3) it is metal filled including arbitrarily based on density, sequential or its
The filling of his function is, it is necessary to meet that corresponding DRC density rule requires.
The present invention further comprises：Wherein step (8) is by the photoetching distortion information of the corresponding hotspot location in step (6) and (7)
It is compared, includes the retraction information of the pitch information of minimum spacing focus, the width information of minimum widith focus, line end focus
With the PVI information of all focuses etc., if the result of correspondence position step (6) is better than step (7), the pre-filled reservation of point is no
Then, this point is pre-filled does not retain.
Compared with prior art, the present invention has following features：
For the present invention by the use of pre-filled redundancy metal as printability secondary graphics, repairing, which is restored, the same of special lithographic hotspots
When, improve local density metal, optimize flatness after CMP.
Photoetching friendly fill method proposed by the present invention only needs Twi-lithography to emulate, a feedback adjustment, simple efficient,
Suitable for repairing the interconnecting metal layer that required precision is not high but loading is big.
In addition, the present invention Conventional filler part there is higher flexibility, can carry out according to demand be based on density, when
Sequence, a variety of fillings for improving power consumption, and have little influence on effect of optimization of the common filling to flatness and sequential.
Brief description of the drawings
Fig. 1 is the pre-filled model of T fonts domain redundancy metal of the present invention, wherein, 100 be original T fonts domain, and 101 are
Pre-filled metal；
Fig. 2 is the pre-filled model of L fonts domain redundancy metal of the present invention, wherein, 200 be original L fonts domain, and 201 are
Pre-filled metal；
Fig. 3 is the pre-filled model of line end domain redundancy metal of the present invention, wherein, 300 be original line end domain, and 301 be pre-
Fill metal；
Fig. 4 is the pre-filled schematic flow sheet of redundancy metal of the present invention；
Fig. 5 is that photoetching friendly redundancy metal of the present invention fills schematic flow sheet；
Fig. 6 is case study on implementation T fonts layout extraction of the present invention and the pre-filled specific dimensional parameters of redundancy metal, unit are
Nm, for dotted portion to consider that DRC rules require the white space of matching, figure dotted line border is non-matching border；
Fig. 7 is case study on implementation L fonts layout extraction of the present invention and the pre-filled dimensional parameters of redundancy metal, and unit nm is empty
To consider that DRC rules require the white space of matching, figure dotted line border is non-matching border for line part；
Fig. 8 is case study on implementation line end layout extraction of the present invention and the pre-filled specific dimensional parameters of redundancy metal, unit nm,
For dotted portion to consider that DRC rules require the white space of matching, figure dotted line border is non-matching border.
Case is embodied
Technical scheme is carried out below in conjunction with specific implementation case completely, clearly to describe.Obviously, retouched
The example stated only be the present invention a part and it is not all.Based on the case study on implementation in the present invention, the ordinary skill people of this area
The every other embodiment that member is obtained under the premise of creative work is not made, belongs to protection scope of the present invention.
First, 45nm techniques integrated circuit diagram to be filled is provided with GDS II format, the integrated circuit diagram includes one
Individual M3 structured metal layers.
Secondly, T fonts, L fonts, line end domain model library are established respectively using Graphic Pattern Matching eda software, design parameter is set
Put as can be seen from figures 6 to 8.To meet sign-off requirement, model considers M3 metal level minimum spacing problems, is matching corresponding domain knot
Enough white spaces (as shown in phantom in FIG.) are have matched while structure, with ensure it is pre-filled after meet DRC rule require.Adopt
Being matched with boundary scheme, i.e., special pattern border allows to match particular range size (60~150 borders in such as Fig. 6),
Special pattern border can be not involved in matching (dashed boundaries in such as Fig. 6) as virtual boundary.Using the extraction of Perl language scripts most
The coordinate of whole matching result, and according to generation redundancy metal position coordinates Fig. 6~8 Suo Shi.
After obtaining redundancy metal position coordinates, the eda software inserted using redundancy metal is carried out based on the pre- of model respectively
Filling and width are 1 times of minimum widith, spacing is the conventional s2w1 fillings of 2 times of minimum spacings, and carry out LFD lithography simulations, are obtained
To LEC focus results.After removing all pre-filled metals, then LFD lithography simulations are carried out, obtain LEC focus results.Utilize Perl
Script compares the line end retraction parameter max of same position LEC focuses.If the lithographic hotspots to remove pre-filled preceding max indexes small,
Then retain pre-filled coordinate at this, it is on the contrary then remove pre-filled coordinate at this.Will be pre- using treated pre-filled coordinate file
Filling metal enters to fill back in domain again.
It is the result of study of case study on implementation of the present invention below：S2w1 represents directly to perform M3 layers common filling (parameter choosing
Select：It is 2 times of minimum spacings between redundancy metal and signal wire, redundancy metal width is 1 times of minimum widith, and spacing is between 1 times of minimum
Away from) after domain, LFD_s2w1 represents that performing photoetching friendly redundancy metal proposed by the present invention to M3 layers fills flow (parameter
Select same s2w1) after domain.
Table 1 illustrates original layout hotspot's classification statistical result, and T fonts, L font focus numbers account for LEC focuses sum
69.25%, account for the 72.29% of MWC focuses sum.Although the requirement of filling might not be met around these figures, for
For LFD filling flows, such domain has very big reparative potential.Contrast table 2, T fonts and the pre-filled number of L fonts are equal
Much larger than the figure number for producing focus, it is protected by for the domain that distortion may be potentially produced because of filling, in the hope of reducing
Fill risk.Filled by LFD, final loading reduces 1.62% compared with common filling.
The original layout hotspot's classification of table 1 counts
The loading of table 2 contrasts
Table 3 compared for commonly filling flow and each stage lithographic hotspots number of LFD flows.(T, L-type after pre-filled end
After domain is pre-filled), specific original figure focus 329 is repaired altogether, and repair rate reaches 57.52%.It is but conventional carrying out LFD
After filling, the number of reparation declines, and caused new focus increases, and Conventional filler disturbs to pre-filled effect, but
Compared with being directly filled (after common s2w1 fillings), repairing effect and protecting effect are fairly obvious.By feedback adjustment,
Final result (after LFD_s2w1 fillings) display, original LEC focuses number have dropped 20.70%, and relatively common filling have dropped
8.90%, LEC focus sum add 1.25%, and relatively common filling have dropped 45.08%.Original MWC focuses number have dropped
62.65%, relatively common filling have dropped 27.06%, MWC focus sums and have dropped 10.84%, and relatively common filling have dropped
19.13%.Original MSC focuses number have dropped 85.71%, MSC focus sums and increase only 2, illustrate that filling influences not on MSC
Greatly.It follows that LFD fillings flow can repair original layout focus to a certain extent, while effectively reduce because of filling tape
The new focus come.
Table 3 LEC, MWC, MSC focus number contrasts
Flatness maximum difference contrasts after table 4 is CMP.Emulation represents imitative using CMP analysis emulation eda tools, min_max
Minimum 2 distance differences of highest in true region.As a result show, flatness difference improves 84.19% compared with original layout, and general
Logical s2w1 fillings maintain an equal level, and its distribution trend is with commonly filling basically identical and more concentrating.
Flatness maximum difference situation contrast table after the CMP of table 4
Claims (6)
1. a kind of photoetching friendly redundancy metal fill method, it is characterised in that comprise the following steps：
(1) integrated circuit diagram to be filled is provided, the integrated circuit diagram includes at least one structured metal layer, and includes energy
Enough fill the region of redundancy metal；
(2) it is pre-filled to domain to be filled progress redundancy metal；
(3) conventional redundancy metal filling is carried out, and carries out lithography simulation；
(4) remove all pre-filled redundancy metal figures, and carry out lithography simulation；
(5) pre-filled redundancy metal and common filling redundancy metal coordinate are extracted；
(6) the redundancy metal coordinate in step (5) is utilized, removes the photoetching heat of redundancy metal in the lithographic results of step (3)
Point information；
(7) the redundancy metal coordinate in step (5) is utilized, removes the photoetching heat of redundancy metal in the lithographic results of step (4)
Point information；
(8) comparison step (6) and the result of (7), it is determined whether retain pre-filled figure；
(9) the pre-filled figure for determining to retain is refilled in domain；
Described step (2) comprises the following steps：
(A) integrated circuit diagram to be filled is provided, the integrated circuit diagram includes at least one structured metal layer, T fonts, L
At least one of font and line end structure, while there is the region for inserting pre-filled figure enough；
(B) Graphic Pattern Matching, three kinds of pre-fill are carried out to existing domain according to the original layout figure in following three kinds of pre-filled models
Mold filling type refers to：
1) pre-filled model is repaired in the photoetching for T font layout patterns, includes the T font layout patterns knots of an any direction
Structure and a redundancy metal；
2) pre-filled model is repaired in the photoetching for L font layout patterns, includes the L font layout patterns knots of an any direction
Structure and a redundancy metal；
3) pre-filled model is repaired in the photoetching for line end layout patterns, includes the line end layout patterns structure of an any direction
With a redundancy metal；
(C) the original layout figure coordinate in three kinds of matching results is extracted respectively；
(D) modification matching figure coordinate, obtained pre-filled according to the redundancy metal graph position in three kinds of pre-filled models respectively
Figure coordinate；
(E) existing domain is carried out according to pre-filled figure coordinate pre-filled.
2. a kind of photoetching friendly redundancy metal fill method as claimed in claim 1, it is characterised in that step (3), (4)
In lithography simulation be to be realized by the friendly design eda tool of photoetching.
3. a kind of photoetching friendly redundancy metal fill method as claimed in claim 1, it is characterised in that in step (3)
The metal filled filling including arbitrarily based on density, sequential or other functions of conventional redundancy is, it is necessary to meet corresponding DRC density rule
Then require.
A kind of 4. photoetching friendly redundancy metal fill method as claimed in claim 1, it is characterised in that wherein step (8)
The photoetching distortion information of step (6) and (7) corresponding hotspot location is compared, including the pitch information of minimum spacing focus,
The PVI information of the width information of minimum widith focus, the retraction information of line end focus and all focuses, if correspondence position step
(6) result is better than step (7), then the pre-filled reservation of point, and otherwise, point is pre-filled does not retain for this.
A kind of 5. photoetching friendly redundancy metal fill method as claimed in claim 1, it is characterised in that step (A) mesopodium
The region for enough inserting pre-filled figure refers to, after inserting pre-filled figure according to pre-filled model, still meets that DRC rules will enough
Ask.
6. a kind of photoetching friendly redundancy metal fill method as described in claim 1 or 5, it is characterised in that in step (B)
Graphic Pattern Matching realizes that matching content not only includes figure in itself by Graphic Pattern Matching eda tool, also includes to meet DRC
Packing space necessary to rule.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510304216.1A CN104951600B (en) | 2015-06-04 | 2015-06-04 | A kind of photoetching friendly redundancy metal fill method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510304216.1A CN104951600B (en) | 2015-06-04 | 2015-06-04 | A kind of photoetching friendly redundancy metal fill method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104951600A CN104951600A (en) | 2015-09-30 |
| CN104951600B true CN104951600B (en) | 2017-12-26 |
Family
ID=54166257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510304216.1A Expired - Fee Related CN104951600B (en) | 2015-06-04 | 2015-06-04 | A kind of photoetching friendly redundancy metal fill method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104951600B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107153720B (en) * | 2016-03-02 | 2020-10-16 | 中国科学院微电子研究所 | Method and system for filling redundant metal |
| CN108122267B (en) * | 2016-11-30 | 2021-05-11 | 中国科学院微电子研究所 | Filling method and device for redundant metal |
| CN108009352A (en) * | 2017-11-30 | 2018-05-08 | 上海华力微电子有限公司 | A kind of filling flow of lithography layout and the design method of photo etched mask |
| CN108536944A (en) * | 2018-04-02 | 2018-09-14 | 郑州云海信息技术有限公司 | The method and system of overlapping via is checked in a kind of placement-and-routing |
| CN109345509B (en) * | 2018-08-31 | 2022-02-08 | 上海华力微电子有限公司 | Method for searching hot spots in multi-crystal layer photoetching process |
| CN110658696B (en) * | 2019-09-30 | 2021-04-13 | 上海华力集成电路制造有限公司 | Photoetching friendliness design checking method for disconnection hot spot |
| CN112434484A (en) * | 2020-12-02 | 2021-03-02 | 长江存储科技有限责任公司 | Redundancy filling method |
| CN113312873B (en) * | 2021-05-24 | 2023-03-14 | 海光信息技术股份有限公司 | Circuit layout design method and device, mask plate and electronic equipment |
| CN115688669B (en) * | 2022-12-27 | 2023-04-07 | 华芯程(杭州)科技有限公司 | Layout design method, device and equipment for metal layer connecting through hole |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446826A (en) * | 2011-09-23 | 2012-05-09 | 上海华力微电子有限公司 | Design and application of redundant metal filler testing photo mask on metal layer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8455180B2 (en) * | 2010-10-29 | 2013-06-04 | Texas Instruments Incorporated | Gate CD control using local design on both sides of neighboring dummy gate level features |
-
2015
- 2015-06-04 CN CN201510304216.1A patent/CN104951600B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446826A (en) * | 2011-09-23 | 2012-05-09 | 上海华力微电子有限公司 | Design and application of redundant metal filler testing photo mask on metal layer |
Non-Patent Citations (4)
| Title |
|---|
| Optimized pattern fill process for improved CMP uniformity and interconnect capacitance;Mark M. Nelson;《University/Government/Industry Microelectronics Symposium》;20030904;374-375 * |
| Random Yield Model in Integrated Circuit Design;XM Chen 等;《Applied Mechanics & Materials》;20130831;1837-1843 * |
| 冗余金属的光刻影响分析及优化;辛玲;《中国优秀硕士学位论文全文数据库 信息科技辑》;20130815;I135-165 * |
| 化学机械研磨（CMP）对电特性影响的分析与优化;姜霖;《中国优秀硕士学位论文全文数据库 信息科技辑》;20120815;I135-131 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104951600A (en) | 2015-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104951600B (en) | A kind of photoetching friendly redundancy metal fill method | |
| US8745554B2 (en) | Practical approach to layout migration | |
| US7458045B2 (en) | Silicon tolerance specification using shapes as design intent markers | |
| US8812999B2 (en) | Method and system of mask data preparation for curvilinear mask patterns for a device | |
| US8683392B2 (en) | Double patterning methodology | |
| US20130239071A1 (en) | Method and apparatus for enhanced optical proximity correction | |
| US8839158B2 (en) | Pattern designing method, pattern designing program and pattern designing apparatus | |
| CN105488244B (en) | Method and system for designing semiconductor device | |
| US20200081352A1 (en) | Dissection method for layout patterns in semiconductor device, optical proximity correction method including the same and method of manufacturing semiconductor device including the same | |
| KR20170073513A (en) | A computer implemented system and method for modifying a layout of standard cells defining a circuit component | |
| US8103984B1 (en) | System and method for compressed design phase contour data | |
| US11061321B1 (en) | Obtaining a mask using a cost function gradient from a Jacobian matrix generated from a perturbation look-up table | |
| US20150161321A1 (en) | Polygon-based optical proximity correction | |
| KR102356163B1 (en) | A system and method for perforating redundant metal in self-aligned multiple patterning | |
| CN103365071A (en) | Optical proximity correction method for mask plate | |
| CN103544332B (en) | A kind of dummy argument integrated approach based on density gradient focus cluster and local solution | |
| CN103048873A (en) | Optical proximity correction method for hole | |
| CN106094422A (en) | A kind of simplify the method for mask graph after OPC | |
| CN100592494C (en) | Method for correcting layout design for correcting metallic coating of contact hole | |
| TWI465839B (en) | Method of generating assistant feature | |
| US10001698B2 (en) | Layout hierachical structure defined in polar coordinate | |
| US8527927B2 (en) | Zone-based area recovery in electronic design automation | |
| US8112724B2 (en) | Method of designing semiconductor integrated circuit, apparatus for designing semiconductor integrated circuit, recording medium, and mask manufacturing method | |
| Wang et al. | Exploiting hierarchical structure to enhance cell-based RET with localized OPC reconfiguration | |
| US8910092B1 (en) | Model based simulation method with fast bias contour for lithography process check |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220112 Address after: 116085 room 211, No. 97, Guangxian Road, high tech Industrial Park, Dalian, Liaoning Province Patentee after: Dalian Mingxin Technology Co.,Ltd. Address before: 116024 No. 2 Ling Road, Ganjingzi District, Liaoning, Dalian Patentee before: DALIAN University OF TECHNOLOGY |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171226 |