CN109345509B

CN109345509B - Method for searching hot spots in multi-crystal layer photoetching process

Info

Publication number: CN109345509B
Application number: CN201811012246.5A
Authority: CN
Inventors: 朱忠华; 魏芳
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2018-08-31
Filing date: 2018-08-31
Publication date: 2022-02-08
Anticipated expiration: 2038-08-31
Also published as: CN109345509A

Abstract

A hot spot search method of polycrystalline layer photoetching technology is characterized by comprising a hot spot search method of polycrystalline layer photoetching technology, which is applicable to the field of integrated circuit manufacturing, provides a layout of an integrated circuit design and defines an isolated gate pattern; further comprising the steps of: step S1, carrying out the pattern matching of the isolated gate in the layout; step S2, finding out all hotspots in the layout according to the matching result; step S3, determining a risk level of the hot spot according to the line width size of the hot spot, determining that the hot spot is a first risk level if the line width size is smaller than a first threshold, and determining that the hot spot is a second risk level if the line width size is larger than the first threshold. The technical scheme of the invention has the beneficial effects that: before the tape-out, find out the hot spot of the glue pouring caused by the isolated grid structure in the original product and take the corresponding measure, save the time of the new product tape-out, increase the yield of the new product at the same time.

Description

Method for searching hot spots in multi-crystal layer photoetching process

Technical Field

The invention relates to the field of Design For Manufacturability (DFM) design, in particular to a hot spot searching method For a polycrystalline layer photoetching process.

Background

As the technology nodes of integrated circuit manufacturing technology continue to advance, the design of integrated circuits becomes very complex. The wavelength of light in the mainstream lithographic process currently used in integrated circuit production has been maintained at 193 nm. Under the condition that the wavelength of the exposure machine is not updated, the size of the exposure pattern is continuously reduced, and a plurality of photoetching patterns which accord with the design rule and have poorer actual process windows are generated, and are generally called photoetching defect patterns. The processing method for the photoetching defect graph comprises the steps of optimizing the original layout design before tape-out and carrying out special process treatment on the detected hot spots of the photoetching process.

Polycrystalline layer is one of the most important layers in the manufacturing layer of the integrated circuit, and isolated polycrystalline layer patterns are often found to be easy to have glue fall after the development is finished in the existing production process. The occurrence of the glue fall affects the final yield of the product. As shown in fig. 1, SEM (Scanning Electron Microscope) photographs of the isolated gate defects found in the integrated circuit production process. The area 101 should have gate lines present but the pattern is lost due to the smaller process window. As shown in fig. 2, the original layout design pattern corresponding to the isolated gate defect pattern is glued down, and it can be obviously found that a large empty process exists at the periphery of the region 201 corresponding to the region 101, and in the developing process after exposure is completed, a large impact is generated on the isolated gate lines, so that glue pouring is caused.

If the isolated gate lines can be searched and corresponding measures can be taken before the tape-out, the time for new products to tape-out can be saved, and the yield of the new products can be increased.

Disclosure of Invention

Aiming at the problems, the hot spot searching method for the polycrystalline layer photoetching process is provided for searching defects caused by isolated gate structures in the original product before the flow sheet is realized.

The invention adopts the following technical scheme:

a hot spot searching method for multi-layer photoetching process is suitable for the field of integrated circuit manufacture, provides a layout of an integrated circuit design, and defines an isolated gate pattern;

further comprising the steps of:

step S1, carrying out the pattern matching of the isolated gate in the layout;

step S2, finding out all hotspots in the layout according to the matching result;

step S3, determining a risk level of the hot spot according to the line width size of the hot spot, determining that the hot spot is a first risk level if the line width size is smaller than a first threshold, and determining that the hot spot is a second risk level if the line width size is larger than the first threshold.

Preferably, the method for defining the isolated gate pattern includes:

step A1, making the line width of the isolated gate pattern smaller than a second threshold;

step A2, making the area of the corresponding open region of the isolated gate pattern larger than a third threshold;

and A3, making the distance from the empty region corresponding to the isolated gate pattern smaller than a fourth threshold value.

Preferably, the method further includes adding a redundant graph to the hot spot determined as the first risk level at a corresponding position in the layout.

Preferably, the method further includes, for the hot spot determined as the first risk level, increasing the size of the isolated gate pattern corresponding to the hot spot in the layout.

Preferably, the method further includes, for the hot spot determined as the second risk level, adjusting a focus depth of the isolated gate pattern in the photolithography process.

Preferably, the method further includes, for the hot spot judged as the second risk level, adjusting the rotation rate of the developing program in the lithography process.

Preferably, when the isolated gate pattern is defined, the empty region corresponding to the isolated gate pattern may surround two sides of the isolated gate pattern, or may surround three sides of the isolated gate pattern, or may surround four sides of the isolated gate pattern.

Preferably, the method for defining the isolated gate pattern further includes making the density of the empty region smaller than a fifth threshold.

The technical scheme of the invention has the beneficial effects that: before tape-out, find out the hot spot of the defect caused by relatively isolated gate structure in the original product and take corresponding measures, save the time of tape-out of new products, increase the yield of new products at the same time.

Drawings

Embodiments of the present invention will be described more fully with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.

FIG. 1 is an SEM photograph of an inverted isolated gate defect found during integrated circuit fabrication;

FIG. 2 is an original layout design pattern corresponding to a defective pattern of an isolated gate by glue pouring;

FIG. 3 is a schematic flow chart of a hot spot search method for a multi-layer lithography process according to a preferred embodiment of the present invention;

FIG. 4 is a schematic diagram of the type of the open area around the gate structure in the integrated circuit design layout;

FIG. 5 is a schematic diagram of layout hotspot types of an integrated circuit design;

FIG. 6 is a diagram illustrating a specific method for defining an orphan gate structure in an integrated circuit design layout;

FIG. 7 is a flow chart illustrating a method for defining isolated gate patterns for a hot spot search method of a poly-layer lithography process in a preferred embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

Based on the problems in the prior art, the invention provides a hot spot searching method for a polycrystalline layer photoetching process, which is suitable for the field of integrated circuit manufacturing, provides a layout of an integrated circuit design, and defines an isolated gate pattern;

as shown in fig. 3, the method further comprises the following steps:

step S1, carrying out isolated gate pattern matching in the layout;

step S2, finding out hotspots in all layouts according to matching results;

step S3, determining a risk level of the hot spot according to the line width size of the hot spot, determining the hot spot as a first risk level if the line width size is smaller than a first threshold, and determining the hot spot as a second risk level if the line width size is larger than the first threshold.

Specifically, the layout hot spots of the integrated circuit design in the example shown in fig. 5 can be summarized into 3 parts, including 501, 502, 503;

501 is the important open area size definition, belonging to the open enclosure of the L-shape on both sides. C and d are the key definition quantities of the first type risk grade and the second type risk grade according to the sizes of c and d;

502 is a specific isolated gate pattern, wherein a and b are the key definition quantities thereof, and can be used as important parameters for classifying risk levels.

503 is a don't care area, no matter how the shape of the graph is, no influence is on the search itself.

In a preferred embodiment of the present invention, as shown in fig. 7, the method for defining the isolated gate pattern includes:

step A2, making the area of the corresponding empty region of the isolated gate pattern larger than a third threshold;

and step A3, making the distance from the empty region corresponding to the isolated gate pattern smaller than a fourth threshold value.

Specifically, as shown in fig. 4(a), the isolated gate pattern is defined. The size of the isolated gate pattern 401 is defined, and the definition includes: length, width, or area.

Further, as shown in fig. 6, the specific definition method of the isolated gate pattern includes:

(1) defining the size of an isolated gate pattern, a and b;

(2) taking the left half area of the isolated gate pattern as an example, the line segment AB is derived from a position c away from the left side of the isolated gate pattern. And (5) delaying the line segments BA to A 'according to the requirement of the size of the open area, and extending the line segments AB to B' to construct a new line segment A 'B'. Translating a 'B' to a segment CD in the left direction, forming a rectangle such as a 'B' CD, an open area shown as 601 in fig. 6;

(3) the same operation flow, a 602 empty region is constructed above the isolated gate;

(4) the two sides of 601 and 602 surround the open area and limit the density to be within e%.

The patterns meeting the critical dimensions a, b, c, d and e are isolated gate patterns to be searched.

In an embodiment of the invention, the second threshold is set to 0.5 μm, or other suitable values, that is, the range of the line width of the isolated gate pattern is 0-0.5 μm; third threshold valueIs set to be 200 μm²Or other suitable value, i.e. the area of the peripheral open region of the isolated gate pattern is larger than 200 μm²(ii) a The fourth threshold is set to 0.2 μm, or other suitable values, i.e. the distance between the empty region and the isolated gate pattern is in the range of 0-0.2 μm.

In a specific embodiment, if a hotspot with a first risk level exists on the layout, the layout is revised again.

In a preferred embodiment of the present invention, the method further includes adding a redundant pattern to a corresponding position in the layout for the hot spot determined as the first risk level.

In a preferred embodiment of the present invention, for the hot spot determined as the first risk level, the size of the isolated gate pattern corresponding to the hot spot is increased in the layout.

In a specific embodiment, if a hotspot with a second risk level exists on the layout, the production process is adjusted.

In a preferred embodiment of the present invention, the method further comprises adjusting a focus depth of the isolated gate pattern in the photolithography process for the hot spot determined as the second risk level.

In a preferred embodiment of the present invention, the method further comprises adjusting the rotation rate of the developing program in the photolithography process for the hot spot determined as the second risk level.

In a preferred embodiment of the present invention, when the isolated gate pattern is defined, the empty region corresponding to the isolated gate pattern may surround two sides of the isolated gate pattern, or may surround three sides of the isolated gate pattern, or may surround four sides of the isolated gate pattern.

Specifically, the definition of the open region 403 may be divided into a form in which two sides are open as shown in fig. 4(a), three sides are open as shown in fig. 4(b), and four sides are open as shown in fig. 4 (c). 402 represents the distance of the open area from the gate lines, and each bounding surface may be defined by a different dimension value.

The open region 403 may not be completely without a pattern, and the pattern density of the region may be set, and the region may be represented as an open region as long as the pattern density matches. Meanwhile, any matching result according with fig. 4 is determined as an isolated gate pattern.

In a preferred embodiment of the present invention, the method for defining the isolated gate pattern further comprises making the density of the empty region less than a fifth threshold.

Specifically, the fifth threshold may be set to 50%, or other suitable value, i.e., the density of the open region is less than 50%.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A hot spot searching method for multi-layer photoetching process is suitable for the field of integrated circuit manufacture, and provides a layout of an integrated circuit design, which is characterized in that an isolated gate pattern is defined;

further comprising the steps of:

step S1, carrying out the pattern matching of the isolated gate in the layout;

step S3, judging the risk level of the hot spot according to the line width size of the hot spot, if the line width size is smaller than a first threshold, judging the hot spot to be a first risk level, and if the line width size is larger than the first threshold, judging the hot spot to be a second risk level; the definition method of the isolated gate pattern comprises the following steps:

2. The method according to claim 1, further comprising adding redundant patterns to corresponding locations in the layout for the hot spots determined to be at the first risk level.

3. The method according to claim 1, further comprising increasing the size of the isolated gate pattern corresponding to the hotspot in the layout for the hotspot determined to be the first risk level.

4. The method according to claim 1, further comprising adjusting a focus depth of the isolated gate pattern during the photolithography process for the hot spot determined as the second risk level.

5. The method of claim 1, further comprising adjusting a rotation rate of a development program during the lithography process for the hot spot determined as the second risk level.

6. The method according to claim 1, wherein the open region corresponding to an isolated gate pattern surrounds two sides of the isolated gate pattern, three sides of the isolated gate pattern, or four sides of the isolated gate pattern when the isolated gate pattern is defined.

7. The method of claim 1, wherein the method of defining the isolated gate pattern further comprises reducing the density of the open region to less than a fifth threshold.