CN113312873A - Circuit layout design method and device, mask plate and electronic equipment - Google Patents
Circuit layout design method and device, mask plate and electronic equipment Download PDFInfo
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- CN113312873A CN113312873A CN202110566049.3A CN202110566049A CN113312873A CN 113312873 A CN113312873 A CN 113312873A CN 202110566049 A CN202110566049 A CN 202110566049A CN 113312873 A CN113312873 A CN 113312873A
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Abstract
The embodiment of the application discloses a circuit layout design method and device, a mask plate and electronic equipment, relates to the technical field of circuit manufacturing, and aims to improve the flatness of the surface of a wafer after chemical mechanical polishing. The method comprises the following steps: determining a first to-be-filled layout area in an original circuit layout; inserting a first redundant graph into the first layout area to be filled to obtain a first intermediate circuit layout; determining a second layout area to be filled in the first intermediate circuit layout; the second to-be-filled layout region and the first to-be-filled layout region are not completely overlapped; determining at least one layout area adjacent to the second to-be-filled layout area; and inserting a second redundant graph into the second layout area to be filled according to the layout density of the second layout area to be filled and the layout density of at least one adjacent layout area. The application is applicable to circuit design.
Description
Technical Field
The application relates to the technical field of circuit manufacturing, in particular to a circuit layout design method and device, a mask plate and electronic equipment.
Background
In the field of circuit fabrication, particularly integrated circuit fabrication, the degree of flatness of the wafer (wafer) surface after Chemical Mechanical Polishing (CMP) of a silicon wafer bar is of significant relevance to the density distribution of the initially designed circuit layout. The circuit layout density distribution is not uniform, which easily causes dishing and Erosion (Erosion) formation on the wafer surface after CMP.
Redundant graphics (dummy) are inserted into the circuit layout, so that the density distribution of the layout is relatively uniform, and the CMP process window is improved. However, the insertion process of the redundant pattern is performed according to the area size of a certain step, specifically, in the form of a window (window), since the layout pattern design varies greatly, some original patterns in the window may accumulate in the corners dividing the window, and after the redundant pattern is inserted once, although the layout density in a single window satisfies the design rule, there may be a density shortage condition at the junction of the window, so that a density step difference is formed between the adjacent relatively high-density areas, and thus, the density of the circuit layout is not uniform, thereby resulting in a low wafer surface flatness after CMP.
Disclosure of Invention
In view of this, embodiments of the present application provide a circuit layout design method, an apparatus, a mask, an electronic device, and a readable storage medium, which can make the density of a circuit layout more uniform, thereby facilitating to improve the surface flatness of a wafer after chemical mechanical polishing.
In a first aspect, an embodiment of the present application provides a circuit layout design method, including: determining a first to-be-filled layout area in an original circuit layout; inserting a first redundant graph into the first layout area to be filled to obtain a first intermediate circuit layout; determining a second layout area to be filled in the first intermediate circuit layout; the second to-be-filled layout region and the first to-be-filled layout region are not completely overlapped; determining at least one layout area adjacent to the second to-be-filled layout area; and inserting a second redundant graph into the second layout area to be filled according to the layout density of the second layout area to be filled and the layout density of at least one adjacent layout area.
According to a specific implementation manner of the embodiment of the application, determining a first layout area to be filled in an original circuit layout includes: dividing an original circuit layout according to a first preset rule to obtain at least two first layout areas; performing density check on each first layout area; and determining a first layout area with the layout density lower than a preset threshold value as a first layout area to be filled.
According to a specific implementation manner of the embodiment of the application, determining a second layout area to be filled in the first intermediate circuit layout includes: dividing the first intermediate circuit layout according to a second preset rule to obtain at least two second layout areas; the second layout area and the first to-be-filled layout area are not completely overlapped; performing density inspection on each second layout area; and determining a second layout area with the layout density lower than a preset threshold value as a second layout area to be filled.
According to a specific implementation manner of the embodiment of the application, after determining a second layout area to be filled in the first intermediate circuit layout, the method further includes: extracting the second layout area to be filled from the first intermediate circuit layout so as to form an independent second intermediate circuit layout in the second layout area to be filled; extracting the first intermediate circuit layout after the second layout area to be filled to form a third intermediate circuit layout; inserting a second redundant graph into the second layout region to be filled according to the layout density of the second layout region to be filled and the layout density of at least one adjacent layout region, wherein the inserting step comprises the following steps: inserting a second redundant graph into the second intermediate circuit layout according to the layout density of the second layout area to be filled and the layout density of the at least one adjacent layout area to form a fourth intermediate circuit layout; and merging the fourth intermediate circuit layout into the third intermediate circuit layout according to the position of the second layout area to be filled in the first intermediate circuit layout.
According to a specific implementation manner of the embodiment of the application, inserting a second redundant graph into the second intermediate circuit layout according to the layout density of the second to-be-filled layout region and the layout density of the adjacent at least one layout region includes: determining a density difference value between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region; and inserting a second redundant graph into the second intermediate circuit layout according to the density difference.
According to a specific implementation manner of the embodiment of the application, in the third intermediate circuit layout, the first and second intermediate circuit layouts are different
The position corresponding to the second layout area to be filled comprises a main pattern; before merging the fourth intermediate circuit layout into the third intermediate circuit layout, the method further comprises: and deleting the main pattern in the fourth intermediate circuit layout to form a new fourth intermediate circuit layout.
According to a specific implementation manner of the embodiment of the application, according to the layout density of the second to-be-filled layout region and the layout density of the adjacent at least one layout region, inserting a second redundant graph into the second to-be-filled layout region includes: determining a density difference value between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region; and inserting a second redundant graph into the second layout area to be filled according to the density difference.
According to a specific implementation manner of the embodiment of the application, after the second redundant graph is inserted into the second to-be-filled layout region, the method further includes: and modifying the second redundant graph to enable the modified second redundant graph to have the characteristics which are unified with the characteristics of the first redundant graph.
In a second aspect, an embodiment of the present application provides a circuit layout design apparatus, including: the first to-be-filled layout region determining module is used for determining a first to-be-filled layout region in the original circuit layout; the first redundant graph inserting module is used for inserting a first redundant graph into the first to-be-filled layout area to obtain a first intermediate circuit layout; the second to-be-filled layout region determining module is used for determining a second to-be-filled layout region in the first intermediate circuit layout; the second to-be-filled layout region and the first to-be-filled layout region are not completely overlapped; an adjacent layout area determining module, configured to determine at least one layout area adjacent to the second to-be-filled layout area; and the second redundant graph inserting module is used for inserting a second redundant graph into the second to-be-filled layout region according to the layout density of the second to-be-filled layout region and the layout density of at least one adjacent layout region.
According to a specific implementation manner of the embodiment of the application, the first to-be-filled layout region determining module is specifically configured to: dividing an original circuit layout according to a first preset rule to obtain at least two first layout areas; performing density check on each first layout area; and determining a first layout area with the layout density lower than a preset threshold value as a first layout area to be filled.
According to a specific implementation manner of the embodiment of the application, the second to-be-filled layout region determining module is specifically configured to: dividing the first intermediate circuit layout according to a second preset rule to obtain at least two second layout areas; the second layout area and the first to-be-filled layout area are not completely overlapped; performing density inspection on each second layout area; and determining a second layout area with the layout density lower than a preset threshold value as a second layout area to be filled.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: the extraction module is used for extracting the second layout area to be filled from the first intermediate circuit layout so as to enable the second layout area to be filled to form an independent second intermediate circuit layout; extracting the first intermediate circuit layout after the second layout area to be filled to form a third intermediate circuit layout; the second redundant graphics insertion module comprising: the second redundant graph inserting sub-module is used for inserting a second redundant graph into the second intermediate circuit layout according to the layout density of the second to-be-filled layout region and the layout density of the adjacent at least one layout region to form a fourth intermediate circuit layout; and the merging submodule is used for merging the fourth intermediate circuit layout into the third intermediate circuit layout according to the position of the second layout area to be filled in the first intermediate circuit layout.
According to a specific implementation manner of the embodiment of the present application, the second redundant pattern insertion sub-module includes: a density difference determining unit, configured to determine a density difference between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region; and the second redundant graph inserting unit is used for inserting a second redundant graph into the second intermediate circuit layout according to the density difference.
According to a specific implementation manner of the embodiment of the application, a position in the third intermediate circuit layout, which corresponds to the second layout area to be filled, comprises a main pattern; the second redundant graphics insertion module further comprises: and the deleting submodule is used for deleting the main pattern in the fourth intermediate circuit layout to form a new fourth intermediate circuit layout.
According to a specific implementation manner of the embodiment of the present application, the second redundant graphics insertion module includes: the density difference sub-module is used for determining the density difference between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region; and the second redundant graph inserting sub-module inserts a second redundant graph into the second to-be-filled layout area according to the density difference.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: and the modification module is used for modifying the second redundant graph so as to unify the characteristics of the modified second redundant graph and the characteristics of the first redundant graph.
In a third aspect, an embodiment of the present application provides a mask, including: the display device comprises a substrate, a main pattern, a first redundant pattern and a second redundant pattern; the main pattern, the first redundant pattern and the second redundant pattern are arranged on the substrate; the first redundant graph and the second redundant graph are manufactured according to a circuit layout obtained by the circuit layout design method in any one of the implementation manners.
In a fourth aspect, an embodiment of the present application provides an electronic device, including: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used for executing the circuit layout design method according to any one of the foregoing implementation modes.
In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement the circuit layout design method according to any one of the foregoing implementation manners.
In the circuit layout design method, the device, the mask plate, the electronic device and the readable storage medium provided by the embodiment, the first redundant graph is inserted into the first layout region to be filled in the original circuit layout to obtain the first intermediate circuit layout, the second layout region to be filled and at least one layout region adjacent to the second layout region to be filled are determined in the first intermediate circuit layout, so that the second redundant graph is inserted into the second layout region to be filled according to the layout density of the second layout region to be filled and the layout density of the adjacent at least one layout region, and after the first intermediate circuit layout is obtained by filling the redundant graph into the first layout region to be filled in the original circuit layout, the second layout region to be filled which is not completely overlapped with the first layout region to be filled is determined from the first intermediate circuit layout, and inserting a second redundant graph into the region, so that the density step difference between the region and the adjacent region is reduced, the density distribution of the circuit layout can be more uniform, and the flatness of the surface of the wafer after chemical mechanical polishing is improved conveniently.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flow chart of a circuit layout design method according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a circuit layout design method according to another embodiment of the present application;
fig. 3 is a schematic flow chart of a circuit layout design method according to an embodiment of the present application;
fig. 4a is a schematic diagram of extracting a second to-be-filled layout region from a first intermediate circuit layout as an independent layout in a specific embodiment of the present application;
FIG. 4b is a schematic diagram of a layout region adjacent to the second to-be-filled layout region in FIG. 4 a;
FIG. 4c is a schematic diagram of the independent layout in FIG. 4a after a second redundant pattern is inserted;
FIG. 4d is a layout diagram after the layout in FIG. 4c is merged into the first intermediate circuit layout;
fig. 5 is a schematic structural diagram of a circuit layout design apparatus according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In a first aspect, a circuit layout design method provided in an embodiment of the present application includes: determining a first to-be-filled layout area in an original circuit layout; inserting a first redundant graph into the first layout area to be filled to obtain a first intermediate circuit layout; determining a second layout area to be filled in the first intermediate circuit layout; the first layout area to be filled and the second layout area to be filled are not completely overlapped; determining at least one layout area adjacent to the second to-be-filled layout area; and inserting a second redundant graph into the second layout region to be filled according to the layout density of the second layout region to be filled and the layout density of at least one adjacent layout region, so that the surface flatness of the wafer after chemical mechanical polishing is improved.
Fig. 1 is a schematic flow chart of a circuit layout design method provided in an embodiment of the present application, and as shown in fig. 1, the circuit layout design method of the present embodiment may include:
s101, determining a first layout area to be filled in the original circuit layout.
The circuit layout can be a plane geometric description of the physical condition of a real circuit. Specifically, the circuit layout, especially the integrated circuit layout, may be a set of multi-level geometric figures designed under certain process conditions according to related design rules and according to the functional and performance requirements of the integrated circuit, the set of multi-level geometric figures including physical information such as the figure structure and size of each device in the circuit, and the mutual positions and connections of the devices.
The original circuit layout in this embodiment includes a main pattern corresponding to a functional device that is necessary to implement a circuit function.
At least one layout region may be included in the original circuit layout. The specific shape of the layout area is not limited, and may be a regular shape such as a rectangle, a square and/or a triangle, etc., or may be an irregular shape.
In the original circuit layout, there is a condition that the local layout density does not meet the requirement of the predetermined threshold, and therefore, in this embodiment, the layout region in the original circuit layout, in which the layout density does not meet the predetermined threshold, is determined as the layout region to be filled, i.e., the first layout region to be filled.
S102, inserting a first redundant graph into the first to-be-filled layout area to obtain a first intermediate circuit layout.
The first redundancy pattern may be a pattern structure unrelated to a circuit function.
After inserting a first redundant graph into a first to-be-filled layout area in the graph of the original circuit, a new circuit layout, namely a first intermediate circuit layout, is formed.
S103, determining a second layout area to be filled in the first intermediate circuit layout.
The second layout region to be filled in this embodiment does not completely coincide with the first layout region to be filled in S101, where the incomplete coincidence includes the cases of partial coincidence and complete non-coincidence.
After the first redundant graph is inserted into the first region of the layout to be filled, the obtained first intermediate circuit layout still has the condition that the layout density does not meet the requirement of the preset threshold value, and the adjacent regions have step differences, namely, the density is not uniform.
It will be appreciated that the layout area in the first intermediate circuit layout may be an area that does not completely coincide, which is obtained by a different method of dividing the layout area in the original circuit layout.
And S104, determining at least one layout area adjacent to the second to-be-filled layout area.
In the first intermediate circuit layout, including at least two layout areas, the number of the areas adjacent to the second to-be-filled layout area may be one, two, four, and so on, and the shape and size of the adjacent layout areas may be the same as or different from the shape and size of the second to-be-filled layout area, for example, the shape of the second to-be-filled layout area is a square, and the size is 10um × 10um, in some examples, the shape of the layout area adjacent to the second to-be-filled layout area may also be a square, and the size is 10um × 10um, in other examples, the shape of the layout area adjacent to the second to-be-filled layout area may also be a rectangle, and the size is 10um × 20 um.
And S105, inserting a second redundant graph into the second layout area to be filled according to the layout density of the second layout area to be filled and the layout density of at least one adjacent layout area.
When the second to-be-filled layout region only comprises the main pattern, the ratio of the area of the main pattern in the second to-be-filled layout region to the area of the second to-be-filled layout region is the layout density of the second to-be-filled layout region.
When the second to-be-filled layout region comprises the main pattern and the first redundant pattern, firstly obtaining the area of the main pattern and the area and the value of the first redundant pattern in the second to-be-filled layout region, wherein the ratio of the area and the value to the area of the second to-be-filled layout region is the layout density of the second to-be-filled layout region.
It can be understood that the calculation method of the layout density of each layout region in the at least one adjacent layout region may be the same as the calculation method of the layout density of the second to-be-filled layout region.
In this embodiment, a first redundant pattern is inserted into a first region to be filled in an original circuit layout to obtain a first intermediate circuit layout, a second region to be filled and at least one layout region adjacent to the second region to be filled are determined in the first intermediate circuit layout, so that a second redundant pattern is inserted into the second region to be filled according to the layout density of the second region to be filled and the layout density of the adjacent at least one layout region, and since the second region to be filled which is not completely overlapped with the first region to be filled in the original circuit layout is determined from the first intermediate circuit layout after the first intermediate circuit layout is obtained by filling the redundant pattern into the first region to be filled in the original circuit layout, and the second redundant pattern is inserted into the first region, thereby reducing the density step difference between the first region and an adjacent region, the density distribution of the circuit layout can be more uniform, so that the flatness of the surface of the wafer after chemical mechanical polishing is improved conveniently, and in addition, when the second redundant graph is inserted, the layout density of the layout area adjacent to the second to-be-filled layout area is combined, so that the step difference of a local area and the step difference of the whole layout are eliminated quickly, the layout design time is shortened, and the layout design accuracy is improved.
The layout design method of the embodiment is not only suitable for the device level (cell level) layout design in an integrated circuit, but also suitable for the chip level (chip level) layout design, and accordingly, the problem of density step difference of the layout device level (small range) and the problem of density step difference of the chip level (layout global) can be solved.
In order to more conveniently determine the first layout region to be filled, in some examples, the determining the first layout region to be filled in the original circuit layout (S101) includes:
s101a, dividing the original circuit layout according to a first preset rule to obtain at least two first layout areas.
The preset rule for dividing the circuit layout can specify the position of a starting point for dividing the original circuit layout and the size of a layout region, and the first preset rule of the embodiment can include that the lower left corner of the original circuit layout is taken as the starting point and the size of each layout region is the same, so that the original circuit layout is divided, and specifically, the original circuit layout can be divided into at least two windows, namely at least two first layout regions, in the form of a window with a certain size and with the lower left corner of the original circuit layout as the starting point.
And S101, 101b, performing density check on each first layout area.
The density of each first layout area may be calculated separately and a density threshold may be set to perform a density check on each first layout area to determine which layout areas satisfy the density rule, where the predetermined threshold may be 60%.
S101c, determining a first layout area with layout density lower than a preset threshold value as a first layout area to be filled.
In order to more conveniently determine the second to-be-filled layout region, in other examples, the determining the second to-be-filled layout region in the first intermediate circuit layout (S103) includes:
s103a, dividing the first intermediate circuit layout according to a second preset rule to obtain at least two second layout areas.
The second layout area in this embodiment does not completely coincide with the first layout area to be filled.
In order to make the second layout area and the first layout area to be filled not completely coincide, the second preset rule of this embodiment may be different from the first preset rule, for example, the second preset rule may include that a position having a certain offset with a lower left corner of the first intermediate circuit layout is taken as a starting point, and the size of each second layout area may be the same as that of the first layout area, so as to divide the original circuit layout, specifically, the first intermediate circuit layout may be divided into at least two windows, that is, at least two second layout areas, in a form of a window of a certain size, with a certain offset with a lower left corner of the first intermediate circuit layout as a starting point, where the offset may be half of the window; the second preset rule may further include that the lower left corner of the first intermediate circuit layout is used as a starting point, the size of each second layout region may be different from the size of the first layout region, and the original circuit layout is divided accordingly.
And S103, 103b, performing density check on each second layout area.
The specific implementation process of this embodiment may be similar to S101b, and is not described herein again.
S103c, determining a second layout area with the layout density lower than a preset threshold value as a second layout area to be filled.
In order to facilitate the processing, the efficiency of inserting the second redundant pattern into the second to-be-filled layout region is improved, and an embodiment of the present application is basically the same as the above embodiment, except that the method for designing the circuit layout of the present embodiment, after determining the second to-be-filled layout region in the first intermediate circuit layout (S103), further includes:
and S106, extracting a second layout area to be filled from the first intermediate circuit layout so as to form an independent second intermediate circuit layout in the second layout area to be filled.
In this embodiment, the first intermediate circuit layout after the second layout area to be filled is extracted to form a third intermediate circuit layout.
Extracting the second to-be-filled layout region may be copying the second to-be-filled layout region, and the corresponding second intermediate circuit layout is the same as the first intermediate circuit layout; extracting the second to-be-filled layout region may also be removing the second to-be-filled layout region from the first intermediate circuit layout, and the corresponding second intermediate circuit layout lacks the second to-be-filled layout region and the rest regions are the same as the first intermediate circuit layout; the extraction of the second to-be-filled layout region may also be a duplication of the second to-be-filled layout region, and the deletion of the first redundant pattern from the first intermediate circuit layout only retains the main pattern, and compared with the first intermediate circuit layout, the corresponding second intermediate circuit layout lacks the first redundant pattern in the second to-be-filled layout region, and the remaining regions are the same.
And extracting the second layout area to be filled, and recording the position of the second layout area to be filled in the first intermediate circuit layout so as to carry out corresponding operation according to the position.
In some examples, the extracted second to-be-filled layout region may be stored, so that reference may be provided for determining which layout regions are to-be-filled layout regions later, and a layout region having the same or similar distribution of the main patterns and the redundant patterns in the second to-be-filled layout region may be determined as the to-be-filled layout region.
After the first intermediate circuit layout after the second to-be-filled layout region is extracted to form a third intermediate circuit layout, in some examples, according to the layout density of the second to-be-filled layout region and the layout density of at least one adjacent layout region, a second redundant pattern is inserted into the second to-be-filled layout region (S105), including:
s105a, inserting a second redundant graph into the second intermediate circuit layout according to the layout density of the second to-be-filled layout area and the layout density of at least one adjacent layout area to form a fourth intermediate circuit layout.
The density control value of the redundant graph inserted into the rule file can be determined according to the layout density of the second to-be-filled layout area and the layout density of at least one adjacent layout area, the second redundant graph is inserted into the second intermediate circuit layout according to the insertion rule file, and compared with the second intermediate circuit layout, the fourth intermediate circuit layout formed comprises a plurality of second redundant graphs, namely the fourth intermediate circuit layout comprises a main graph, a first redundant graph and a second redundant graph, or comprises the main graph and the second redundant graph.
S105b, according to the position of the second layout area to be filled in the first intermediate circuit layout, combining the fourth intermediate circuit layout into the third intermediate circuit layout.
And combining the fourth intermediate circuit layout inserted with the second redundant graph into the third intermediate circuit layout according to the position of the second to-be-filled layout region in the first intermediate circuit layout.
In this embodiment, the second to-be-filled layout region is extracted from the first intermediate circuit layout, so that the second to-be-filled layout region forms an independent second intermediate circuit layout, and thus, the insertion of the redundant graph performed independently for the second intermediate circuit layout can be performed.
In order to simplify the process of inserting the second redundant pattern into the second intermediate circuit layout and improve the processing efficiency, in an embodiment of the present application, according to the layout density of the second to-be-filled layout region and the layout density of at least one adjacent layout region, inserting the second redundant pattern into the second intermediate circuit layout (S105a), includes:
a1, determining the density difference value between the layout density of the second to-be-filled layout region and the layout density of the at least one adjacent layout region according to the layout density of the second to-be-filled layout region and the layout density of the at least one adjacent layout region.
The calculation method of the layout density of the second layout region to be filled and the layout density of each layout region in the at least one adjacent layout region is the same as that in the above embodiment, and is not repeated here.
In this embodiment, determining a density difference between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region may specifically be:
when at least one adjacent layout area comprises one layout area, directly calculating a difference value according to the layout density of the layout area and the layout density of a second layout area to be filled to obtain a density difference value; when at least one adjacent layout area comprises two or more layout areas, calculating the layout density of each layout area, calculating the average value of each layout density, and calculating the density difference value of the two areas according to the obtained average value of each layout density and the layout density of the second to-be-filled layout area.
And A2, inserting a second redundant graph into the second intermediate circuit layout according to the density difference.
The density difference obtained in step a1 may be set as a density control value in a redundant pattern insertion rule file according to which a second redundant pattern is inserted in the second intermediate circuit layout.
In some examples, the method further comprises, prior to merging the fourth intermediate circuit layout into the third intermediate circuit layout, including a main feature at a location in the third intermediate circuit layout corresponding to the second to-be-filled layout region, in order to avoid the main feature from overlapping with a main feature in the fourth intermediate circuit layout:
and S105c, deleting the main pattern in the fourth intermediate circuit layout to form a new fourth intermediate circuit layout.
In order to simplify the process of inserting the second redundant pattern into the second layout region to be filled and improve the processing efficiency, in some examples, inserting the second redundant pattern into the second layout region to be filled according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region (S105), includes:
b1, determining the density difference value between the layout density of the second to-be-filled layout region and the layout density of the at least one adjacent layout region according to the layout density of the second to-be-filled layout region and the layout density of the at least one adjacent layout region.
The process for determining the difference between the layout density of the second to-be-filled layout region and the layout density of the at least one adjacent layout region in this embodiment is similar to the process of a1 in the foregoing embodiment, and is not described herein again.
And B2, inserting a second redundant graph in the second layout area to be filled according to the density difference.
The density difference obtained in step B1 may be set as a density control value in a redundant pattern insertion rule file according to which a second redundant pattern is inserted in the second to-be-filled layout area.
Fig. 2 is a schematic flow chart of a circuit layout design method according to another embodiment of the present application, and as shown in fig. 2, in order to improve a process window of chemical mechanical polishing, in this embodiment, after a second redundant pattern is inserted into a second layout region to be filled, the method further includes:
s107, modifying the second redundant graph to enable the modified characteristics of the second redundant graph to be uniform with the characteristics of the first redundant graph.
The features of the redundant pattern may include: area, perimeter, angle, and/or side length.
The decorating the second redundant pattern may include: and performing contraction edge, extension edge and perimeter optimization processing on the second redundant graph to ensure that the modified second redundant graph and the first redundant graph keep the uniformity on the characteristics and the specified distance.
The regions or windows of the layout density error reporting do not exist in isolation, and when the error reporting windows exist adjacently, or exist at intervals, or are regularly arranged, the technical scheme of the application is also applicable.
When the error reporting windows exist adjacently, the adjacent windows can be used as an integral area to be inserted with a redundant graph, in an embodiment of the present application, the second layout area to be filled includes a first sub-area and a second sub-area, and the first sub-area is adjacent to the second sub-area;
the determining of at least one layout area adjacent to the second to-be-filled layout area includes: at least one layout region adjacent to the first sub-region and/or the second sub-region is determined.
Inserting a second redundant graph into the second layout region to be filled according to the layout density of the second layout region to be filled and the layout density of at least one adjacent layout region, wherein the inserting step comprises the following steps:
and inserting a second redundant graph into the first sub-region and the second sub-region according to the layout density of the second to-be-filled layout region and the layout density of the at least one adjacent layout region.
The following describes the embodiments of the present application in detail with reference to a specific example.
Referring to fig. 3, 4a to 4d, the circuit layout design method of the present embodiment may include:
s201, performing first redundant graph inserting operation on the original layout, and performing density rule checking.
S202, extracting the layout in the window (window) range with the error report after the density check into an independent layout, and recording the position P (x, y) of the window center coordinate on the original layout.
And extracting the independent layout to obtain an original layout as a first intermediate layout.
S203, calculating the layout density in the error reporting window range and the layout average density in four window ranges adjacent to the error reporting window range, and calculating the layout density difference sigma in the two window ranges according to the layout density difference.
S204, setting the density control value in the dummy insertion rule file as a density difference value sigma, and performing second redundant graph insertion operation on the extracted independent layout.
And S205, deleting the main pattern in the independent layout into which the second redundant pattern is inserted, only keeping the redundant pattern, and merging the main pattern with the first intermediate layout according to the window central coordinate P (x, y).
S206, performing contraction edge, extension edge and perimeter optimization processing on the second redundant graph in the secondary filling window in the merged layout to ensure that the second redundant graph and the first redundant graph filled for the first time keep a specified space and the uniformity of graph characteristics (area, perimeter, angle and edge length).
And S207, performing density rule check on the layout again.
The circuit layout design method of the embodiment can be used for processing the layout data by means of a computer, and in the process of inserting the redundant graph, the density of the adjacent region of the region to be filled is considered, so that the density step difference in the layout can be quickly and accurately eliminated, the density distribution of the whole layout is more uniform, the flatness of the wafer surface after CMP is improved, the problems of complexity, time consumption and error easiness in manual insertion of the redundant graph are avoided, and the problem of low flatness of the wafer surface after CMP caused by the fact that the layout adopting the redundant graph in the prior art is adopted is avoided.
In a second aspect, an embodiment of the present application provides a circuit layout design apparatus, including: the first to-be-filled layout region determining module is used for determining a first to-be-filled layout region in the original circuit layout; the first redundant graph inserting module is used for inserting a first redundant graph into the first to-be-filled layout area to obtain a first intermediate circuit layout; the second to-be-filled layout region determining module is used for determining a second to-be-filled layout region in the first intermediate circuit layout; the second to-be-filled layout region and the first to-be-filled layout region are not completely overlapped; an adjacent layout area determining module, configured to determine at least one layout area adjacent to the second to-be-filled layout area; and the second redundant graph inserting module is used for inserting a second redundant graph into the second to-be-filled layout region according to the layout density of the second to-be-filled layout region and the layout density of at least one adjacent layout region, so that the flatness of the surface of the wafer after chemical mechanical polishing is improved conveniently.
Fig. 5 is a schematic structural diagram of a circuit layout design apparatus according to an embodiment of the present application, and as shown in fig. 5, the circuit layout design apparatus according to the embodiment may include:
a first to-be-filled layout region determining module 11, configured to determine a first to-be-filled layout region in an original circuit layout;
a first redundant graph inserting module 12, configured to insert a first redundant graph in the first to-be-filled layout area to obtain a first intermediate circuit layout;
a second to-be-filled layout region determining module 13, configured to determine a second to-be-filled layout region in the first intermediate circuit layout; the second to-be-filled layout region and the first to-be-filled layout region are not completely overlapped;
an adjacent layout region determining module 14, configured to determine at least one layout region adjacent to the second to-be-filled layout region;
and the second redundant graph inserting module 15 is configured to insert a second redundant graph into the second to-be-filled layout region according to the layout density of the second to-be-filled layout region and the layout density of the at least one adjacent layout region.
The apparatus of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 1, and the implementation principle and the technical effect are similar, which are not described herein again.
The device of the embodiment obtains a first intermediate circuit layout by inserting a first redundant graph into a first to-be-filled layout region in an original circuit layout, and then determines a second to-be-filled layout region and at least one layout region adjacent to the second to-be-filled layout region in the first intermediate circuit layout, so that a second redundant graph can be inserted into the second to-be-filled layout region according to the layout density of the second to-be-filled layout region and the layout density of the adjacent at least one layout region, and because the second to-be-filled layout region which is not completely overlapped with the first to-be-filled layout region is determined from the first intermediate circuit layout after the first to-be-filled layout region in the original circuit layout is filled with the redundant graph to obtain the first intermediate circuit layout, and the second redundant graph is inserted into the first to-be-filled layout region, thereby reducing the density step difference between the region and an adjacent region, the density distribution of the circuit layout can be more uniform, and therefore the flatness of the surface of the wafer after chemical mechanical polishing is convenient to improve.
As an optional implementation manner, the first to-be-filled layout region determining module is specifically configured to:
dividing an original circuit layout according to a first preset rule to obtain at least two first layout areas; performing density check on each first layout area; and determining a first layout area with the layout density lower than a preset threshold value as a first layout area to be filled.
As an optional implementation manner, the second to-be-filled layout region determining module is specifically configured to: dividing the first intermediate circuit layout according to a second preset rule to obtain at least two second layout areas; the second layout area and the first to-be-filled layout area are not completely overlapped; performing density inspection on each second layout area; and determining a second layout area with the layout density lower than a preset threshold value as a second layout area to be filled.
As an optional implementation, the apparatus further includes: the extraction module is used for extracting the second layout area to be filled from the first intermediate circuit layout so as to enable the second layout area to be filled to form an independent second intermediate circuit layout; extracting the first intermediate circuit layout after the second layout area to be filled to form a third intermediate circuit layout; the second redundant graphics insertion module comprising: the second redundant graph inserting sub-module is used for inserting a second redundant graph into the second intermediate circuit layout according to the layout density of the second to-be-filled layout region and the layout density of the adjacent at least one layout region to form a fourth intermediate circuit layout; and the merging submodule is used for merging the fourth intermediate circuit layout into the third intermediate circuit layout according to the position of the second layout area to be filled in the first intermediate circuit layout.
As an optional implementation, the second redundant graphic insertion sub-module includes: a density difference determining unit, configured to determine a density difference between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region; and the second redundant graph inserting unit is used for inserting a second redundant graph into the second intermediate circuit layout according to the density difference.
As an optional implementation manner, a position in the third intermediate circuit layout corresponding to the second layout area to be filled includes a main pattern; the second redundant graphics insertion module further comprises: and the deleting submodule is used for deleting the main pattern in the fourth intermediate circuit layout to form a new fourth intermediate circuit layout.
As an optional implementation, the second redundant graphics insertion module includes: the density difference sub-module is used for determining the density difference between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region; and the second redundant graph inserting sub-module inserts a second redundant graph into the second to-be-filled layout area according to the density difference.
As an optional implementation, the apparatus further includes: and the modification module is used for modifying the second redundant graph so as to unify the characteristics of the modified second redundant graph and the characteristics of the first redundant graph.
The apparatus of the foregoing embodiment may be configured to implement the technical solution of the foregoing method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.
In a third aspect, the present application provides a mask, including: the display device comprises a substrate, a main pattern, a first redundant pattern and a second redundant pattern; the main pattern, the first redundant pattern and the second redundant pattern are arranged on the substrate; wherein the first redundant pattern and the second redundant pattern are manufactured according to a circuit layout obtained by the circuit layout design method according to any one of the above embodiments.
The mask plate is also called as a photomask, and is required to be used in the field of designing a photoetching process, and a mask pattern structure is formed on a transparent substrate by an opaque shading film. The mask pattern structure comprises a main pattern, a first redundant pattern and a second redundant pattern. The first redundant pattern and the second redundant pattern in this embodiment are manufactured in accordance with the circuit layout obtained by the circuit layout design method in the above-described embodiment.
In this embodiment, the first redundant pattern and the second redundant pattern on the mask are manufactured according to the circuit layout obtained by the circuit layout design method according to any one of the embodiments, and due to the circuit layout design method according to any one of the embodiments, the density distribution of the circuit layout can be more uniform, so that the pattern structure of the mask obtained according to the circuit layout is more uniform, and thus, the surface flatness of the wafer after chemical mechanical polishing can be improved conveniently.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the electronic device may include: the electronic device comprises a shell 61, a processor 62, a memory 63, a circuit board 64 and a power circuit 65, wherein the circuit board 64 is arranged inside a space enclosed by the shell 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; a power supply circuit 65 for supplying power to each circuit or device of the electronic apparatus; the memory 63 is used to store executable program code; the processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, and is configured to execute the circuit layout design method according to any of the foregoing embodiments, so that corresponding beneficial technical effects can also be achieved.
The above electronic devices exist in a variety of forms, including but not limited to:
(1) ultra mobile personal computer device: the equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads.
(2) A server: the device for providing the computing service comprises a processor, a hard disk, a memory, a system bus and the like, and the server is similar to a general computer architecture, but has higher requirements on processing capacity, stability, reliability, safety, expandability, manageability and the like because of the need of providing high-reliability service.
(3) And other electronic equipment with data interaction function.
Accordingly, an embodiment of the present application further provides a computer-readable storage medium, where one or more programs are stored in the computer-readable storage medium, and the one or more programs may be executed by one or more processors to implement any one of the circuit layout design methods provided in the foregoing embodiments, so that corresponding technical effects may also be achieved, which has been described in detail above and will not be described herein again.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations when the present application is implemented.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (19)
1. A circuit layout design method is characterized by comprising the following steps:
determining a first to-be-filled layout area in an original circuit layout;
inserting a first redundant graph into the first layout area to be filled to obtain a first intermediate circuit layout;
determining a second layout area to be filled in the first intermediate circuit layout; the second to-be-filled layout region and the first to-be-filled layout region are not completely overlapped;
determining at least one layout area adjacent to the second to-be-filled layout area;
and inserting a second redundant graph into the second layout area to be filled according to the layout density of the second layout area to be filled and the layout density of at least one adjacent layout area.
2. The method according to claim 1, wherein said determining a first layout area to be filled in the original circuit layout comprises:
dividing an original circuit layout according to a first preset rule to obtain at least two first layout areas;
performing density check on each first layout area;
and determining a first layout area with the layout density lower than a preset threshold value as a first layout area to be filled.
3. The method according to claim 1, wherein said determining a second layout area to be filled in said first intermediate circuit layout comprises:
dividing the first intermediate circuit layout according to a second preset rule to obtain at least two second layout areas; the second layout area and the first to-be-filled layout area are not completely overlapped;
performing density inspection on each second layout area;
and determining a second layout area with the layout density lower than a preset threshold value as a second layout area to be filled.
4. The method according to claim 1, wherein after determining a second layout area to be filled in the first intermediate circuit layout, the method further comprises:
extracting the second layout area to be filled from the first intermediate circuit layout so as to form an independent second intermediate circuit layout in the second layout area to be filled; extracting the first intermediate circuit layout after the second layout area to be filled to form a third intermediate circuit layout;
inserting a second redundant graph into the second layout region to be filled according to the layout density of the second layout region to be filled and the layout density of at least one adjacent layout region, wherein the inserting step comprises the following steps:
inserting a second redundant graph into the second intermediate circuit layout according to the layout density of the second layout area to be filled and the layout density of the at least one adjacent layout area to form a fourth intermediate circuit layout;
and merging the fourth intermediate circuit layout into the third intermediate circuit layout according to the position of the second layout area to be filled in the first intermediate circuit layout.
5. The method according to claim 4, wherein said inserting a second redundant pattern into said second intermediate circuit layout according to said layout density of said second to-be-filled layout region and said layout density of said at least one adjacent layout region comprises:
determining a density difference value between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region;
and inserting a second redundant graph into the second intermediate circuit layout according to the density difference.
6. The method according to claim 4, wherein the location in the third intermediate circuit layout corresponding to the second to-be-filled layout region comprises a main pattern;
before merging the fourth intermediate circuit layout into the third intermediate circuit layout, the method further comprises:
and deleting the main pattern in the fourth intermediate circuit layout to form a new fourth intermediate circuit layout.
7. The method according to claim 1, wherein inserting a second redundant pattern in the second layout region to be filled according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region comprises:
determining a density difference value between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region;
and inserting a second redundant graph into the second layout area to be filled according to the density difference.
8. The method according to claim 1, wherein after inserting a second dummy pattern into the second to-be-filled layout region, the method further comprises:
and modifying the second redundant graph to enable the modified second redundant graph to have the characteristics which are unified with the characteristics of the first redundant graph.
9. A circuit layout designing apparatus, comprising:
the first to-be-filled layout region determining module is used for determining a first to-be-filled layout region in the original circuit layout;
the first redundant graph inserting module is used for inserting a first redundant graph into the first to-be-filled layout area to obtain a first intermediate circuit layout;
the second to-be-filled layout region determining module is used for determining a second to-be-filled layout region in the first intermediate circuit layout; the second to-be-filled layout region and the first to-be-filled layout region are not completely overlapped;
an adjacent layout area determining module, configured to determine at least one layout area adjacent to the second to-be-filled layout area;
and the second redundant graph inserting module is used for inserting a second redundant graph into the second to-be-filled layout region according to the layout density of the second to-be-filled layout region and the layout density of at least one adjacent layout region.
10. The apparatus according to claim 9, wherein the first to-be-filled layout region determining module is specifically configured to:
dividing an original circuit layout according to a first preset rule to obtain at least two first layout areas;
performing density check on each first layout area;
and determining a first layout area with the layout density lower than a preset threshold value as a first layout area to be filled.
11. The apparatus according to claim 9, wherein the second to-be-filled layout region determining module is specifically configured to:
dividing the first intermediate circuit layout according to a second preset rule to obtain at least two second layout areas; the second layout area and the first to-be-filled layout area are not completely overlapped;
performing density inspection on each second layout area;
and determining a second layout area with the layout density lower than a preset threshold value as a second layout area to be filled.
12. The apparatus of claim 9, further comprising:
the extraction module is used for extracting the second layout area to be filled from the first intermediate circuit layout so as to enable the second layout area to be filled to form an independent second intermediate circuit layout; extracting the first intermediate circuit layout after the second layout area to be filled to form a third intermediate circuit layout;
the second redundant graphics insertion module comprising:
the second redundant graph inserting sub-module is used for inserting a second redundant graph into the second intermediate circuit layout according to the layout density of the second to-be-filled layout region and the layout density of the adjacent at least one layout region to form a fourth intermediate circuit layout;
and the merging submodule is used for merging the fourth intermediate circuit layout into the third intermediate circuit layout according to the position of the second layout area to be filled in the first intermediate circuit layout.
13. The apparatus of claim 12, wherein the second redundant graphic insert sub-module comprises:
a density difference determining unit, configured to determine a density difference between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region;
and the second redundant graph inserting unit is used for inserting a second redundant graph into the second intermediate circuit layout according to the density difference.
14. The apparatus according to claim 12, wherein a location in the third intermediate circuit layout corresponding to the second to-be-filled layout region comprises a main pattern;
the second redundant graphics insertion module further comprises:
and the deleting submodule is used for deleting the main pattern in the fourth intermediate circuit layout to form a new fourth intermediate circuit layout.
15. The apparatus of claim 9, wherein the second redundant graphics insertion module comprises:
the density difference sub-module is used for determining the density difference between the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region according to the layout density of the second layout region to be filled and the layout density of the at least one adjacent layout region;
and the second redundant graph inserting sub-module inserts a second redundant graph into the second to-be-filled layout area according to the density difference.
16. The apparatus of claim 9, further comprising:
and the modification module is used for modifying the second redundant graph so as to unify the characteristics of the modified second redundant graph and the characteristics of the first redundant graph.
17. A mask, comprising: the display device comprises a substrate, a main pattern, a first redundant pattern and a second redundant pattern; the main pattern, the first redundant pattern and the second redundant pattern are arranged on the substrate; wherein the first redundant pattern and the second redundant pattern are manufactured according to a circuit layout obtained by the circuit layout design method according to any one of claims 1 to 8.
18. An electronic device, characterized in that the electronic device comprises: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the circuit layout design method according to any one of the preceding claims 1 to 8.
19. A computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, which are executable by one or more processors to implement the circuit layout design method of any one of the preceding claims 1 to 8.
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