CN111458974A - Method and system for accelerating layout processing - Google Patents
Method and system for accelerating layout processing Download PDFInfo
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- CN111458974A CN111458974A CN202010444483.XA CN202010444483A CN111458974A CN 111458974 A CN111458974 A CN 111458974A CN 202010444483 A CN202010444483 A CN 202010444483A CN 111458974 A CN111458974 A CN 111458974A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a method and a system for accelerating layout processing, wherein the method comprises a layout dividing and correcting step and a layout merging step, the system comprises a management node, a plurality of computing nodes and a plurality of storage nodes, hierarchical arrangement, block division, parallel correction, correction result merging and the like are required to be completed in a computer processing system, the blocks are mutually independent, and the blocks can independently complete correction in the plurality of computing nodes; the invention utilizes the mode of layering the multiplexing units and flattening and dividing the layout by the rest units to accelerate the parallel correction process of the OPC whole chip, improve the efficiency of parallel correction, reuse the correction result, improve the manufacturing consistency of internal units and ensure the performance of the chip.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method and a system for accelerating layout processing.
Background
In semiconductor device manufacturing, a mask pattern is printed or realized on a semiconductor substrate by photolithography. As the minimum feature size and pitch of integrated circuits decrease, patterns in the layout that are close to each other are subject to significant distortion between the actual printed pattern and the desired pattern due to dry diffraction of light and development and etching of the photoresist. To eliminate these distortions, one approach is to perform Optical Proximity Correction (OPC) on the pattern on the mask when the line width on the wafer is smaller than the exposure wavelength. The optical proximity correction technique compensates for transfer distortion of a pattern during photolithography by correcting a design layout in advance.
Because the number of the layout patterns is huge, the optical correction is a task which consumes time and resources. As the feature size of integrated circuits further decreases, the difference between the photolithography wavelength and the line width becomes larger, especially for the process below 22nm, and the full-chip optical correction has become an essential step in the chip mask manufacturing process.
Because the optical correction adopts a complex and accurate calculation model, the number of each layer of mask layout can reach the order of billions, each graph needs to be corrected, and a single machine is difficult to finish. The full-chip optical correction needs to divide a physical layout into a plurality of small blocks according to positions, and each small block is calculated in a distributed parallel mode. Each patch modifies the pattern within the region according to the model. Because each block is independent of the other, the linearly increasing computational complexity can be maintained with distributed computing. Because the mask manufacturing rule is violated probably caused by splicing after the layout is divided and corrected, and meanwhile, the polygon correction error is overlarge due to the influence of an environment area, and the like, the OPC is a process of repeated iteration and repeated correction. Usually, there is a post-OPC verification step to detect the verification and correction result, and when the post-OPC verification detects that there is a problem in the corrected image, the area needs to be corrected again, so that each area mostly adopts an iterative manner of correction-verification-correction again.
Each cutting block comprises two regions, influenced by the optical scattering radius between the patterns: a target area and a surrounding area. As shown in fig. 1, the target area 102 is a reserved area after modification, and the calculation result of the environment area 101 is discarded. The environmental region 101 is a modified pattern that assists in calculating the target region, and its size depends on the lithographic scattering radius, typically the conventional 193nm lithographic wavelength, which is on the order of microns. In parallel division, the larger the number of divided blocks, the greater the proportion of the total environment region increases, and the correction efficiency is lowered simultaneously. If a lithography calculation efficiency factor F (total area of cumulative calculation and/target area of cumulative calculation) is defined, the higher the F factor value is, the higher the calculation efficiency is. For the way of flattening the divided layout, assuming that the area of each block calculated by lithography is (N + m) × (N + m), the area of the target area is N × N, and the total number of divided blocks is N, then
Usually, N × N is the area of the maximum outer frame of all patterns of the layer, and m represents the optical action distance. Depending on the circuit feature size and the lithography wavelength.
Due to the fact that unit multiplexing exists in the integrated circuit layout, if the unit multiplexing is effectively utilized, the operation time can be reduced or the number of calculation nodes can be reduced. However, the original hierarchical unit structure is influenced by other unit graphic elements and cannot be directly reused. The traditional method for correcting the flattened layout divided layout in parallel or in series not only repeatedly corrects redundant parts, but also influences the consistency of correction.
In the prior art, some layout hierarchical OPC correction technologies, for example, according to the existing hierarchy of a layout, an 'external influence free region' in a unit is extracted from bottom to top unit by unit, other regions in the unit and a father unit are corrected together, and the correction efficiency of an integral distributed parallel system is not considered. The reason is that the correction is performed in a step-by-step unit, although the N value is reduced by multiplexing the correction result, the proportion of a part of the environment area of the divided blocks is increased and the efficiency factor is reduced because the area is divided in the unit.
If the corrected block combination is a flattened layout, the hierarchy of the layout cannot be reused during subsequent OPC verification and secondary correction. The amount of mask information stored in a flattened mode after correction is increased violently, and a single layer can reach TB level.
Disclosure of Invention
The invention aims to provide a method and a system for accelerating layout processing, which aim to solve the problems in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme: a method for accelerating layout processing comprises the following steps:
layout division and correction:
Step 2: traversal set V1If the cell has a unique parent cell, the cell is selected from V1Deleted in (1), the remaining unit set is marked as V2；
And step 3: analyzing the multiplexing unit set V one by one according to the optical action distance2Obtaining the influence area of the unit, other units and the unit on the unit graph to obtain the boundary B of the unit in the domain layering reusable area to be optically corrected1To optically modify the zone boundary B1As an auxiliary graphic L2Inserting into the top unit;
step 4, dividing the top unit block, subtracting the auxiliary graph L by the top unit2Obtaining a to-be-corrected area of the top unit in the covered area, and performing distributed parallel correction on the to-be-corrected area of the top unit;
and 5: to V2The unit auxiliary graphics L2Subtracting the area covered by the auxiliary graphs of all the subunits from the covered area to obtain the area to be corrected of the unit, and dividing the area to be corrected of the unit into blocks for distributed parallel correction;
layout merging step:
step 6: storing the correction result of each block to each unit node to which the original cutting block belongs, and combining the correction results of the blocks;
and 7: extracting a layout unit tree structure and reserving the unit set V1And deleting the residual unit nodes to obtain a new unit hierarchical structure.
Preferably, the boundary of the modified area dividing block is not limited to any polygon.
Preferably, the average partition block size W1Greater than the inter-pattern optical working distance.
Preferably, the parallel correction in steps 4 and 5 is a parallel correction on a plurality of processors or a plurality of processor cores.
Preferably, in step 7, the deletion of the unit tree node needs to update the call relationship of the reserved unit node and the corresponding information of the conversion unit.
Preferably, the block size W2At least the block size W14 times of the total weight of the product.
The utility model provides a system for accelerating territory processing, includes a management node, a plurality of calculation node and a plurality of storage node, wherein, the management node is used for accomplishing the optical proximity correction of each block including the reading module that is used for loading original territory, the analysis module that is used for hierarchical analysis and cuts apart the territory, the processing module that is used for merging the correction result at least, the calculation node, the storage node is used for storing territory mask data and instruction program.
Preferably, the management node, the plurality of computing nodes and the storage node are interconnected through a network controller.
Compared with the prior art, the invention has the beneficial effects that:
the invention utilizes the mode of layering the multiplexing units and flattening and dividing the layout by the rest units to accelerate the parallel correction process of the OPC whole chip, improve the efficiency of parallel correction, reuse the correction result, improve the manufacturing consistency of internal units and ensure the performance of the chip.
Drawings
FIG. 1 is a cut block modified target area and environmental area;
FIG. 2 is an exemplary diagram of a multicore processor in an embodiment of the present invention;
FIG. 3 is a layout layer in an embodiment of the present invention;
FIG. 4 is a schematic top view of a cell in an embodiment of the invention;
FIG. 5 is a block diagram of an exemplary tree according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating exemplary auxiliary graphics for the border of the multiplexing region;
FIG. 7 is a diagram of a D-unit partition block according to an embodiment of the present invention;
FIG. 8 is a block diagram of a partition formed by subtracting the D unit from the B unit according to an embodiment of the present invention;
FIG. 9 is a block diagram of a partition formed by subtracting the B cell from the A cell and the D cell in the embodiment of the present invention;
FIG. 10 is a diagram of a modified merged unit tree according to an embodiment of the present invention;
FIG. 11 is a system block diagram of an accelerated layout processing system according to an embodiment of the present invention;
FIG. 12 is a schematic top view of a cell in another embodiment of the present invention;
FIG. 13 is a tree diagram illustrating exemplary units according to another embodiment of the present invention;
FIG. 14 is a diagram of a D-unit partition block according to another embodiment of the present invention;
FIG. 15 is a diagram of an E-unit partition block according to another embodiment of the present invention;
FIG. 16 is a block diagram of a partitioned area formed by subtracting the D unit from the A unit and the E unit according to another embodiment of the present invention;
FIG. 17 is a modified merged unit tree diagram according to another embodiment of the present invention.
Reference numbers in the figures: 101. an environmental area; 102. a target area; 103. a first storage unit; 104. a second storage unit; 105. a first processor core; 106. a second processor core; 107. a third processor core; 108. a fourth processor core 109, a first logic layer; 110. a second logic layer; 111. a third logic layer; 112. a fourth logic layer; 201. cell D target reserve area boundary; 202. cell B target reserve zone boundary; 301. a management node; 302. calculating a node; 303. and storing the nodes.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example (b): a method for accelerating layout processing comprises the following steps:
layout division and correction:
Step 2: traversal set V1If the cell has a unique parent cell, the cell is selected from V1Deleted in (1), the remaining unit set is marked as V2；
And step 3: analyzing the multiplexing unit set V one by one according to the optical action distance2Obtaining the influence area of the unit, other units and the unit on the unit graph to obtain the boundary B of the unit in the domain layering reusable area to be optically corrected1To optically modify the zone boundary B1As an auxiliary graphic L2Inserting into the top unit;
step 4, dividing the top unit block, subtracting the auxiliary graph L by the top unit2Obtaining a to-be-corrected area of the top unit in the covered area, and performing distributed parallel correction on the to-be-corrected area of the top unit;
and 5: to V2The unit auxiliary graphics L2Subtracting the area covered by the auxiliary graphics of all the subunits from the covered area to obtain the area to be corrected of the unit, and dividing the area to be corrected of the unit into blocks to be distributedFormula parallel correction;
layout merging step:
step 6: storing the correction result of each block to each unit node to which the original cutting block belongs, and combining the correction results of the blocks;
and 7: extracting a layout unit tree structure and reserving the unit set V1And deleting the residual unit nodes to obtain a new unit hierarchical structure.
In this embodiment, as shown in fig. 2, taking a multi-core processor as an example, a first processor core 105, a second processor core 106, a third processor core 107, and a fourth processor core 108 are examples of four multiplexed processor cores, and a first storage unit 103 and a second storage unit 104 are examples of memory units multiplexed in the first processor core 105, which are used to illustrate that unit multiplexing may exist in a self-oriented downward direction in an integrated circuit layout;
4 cores, the kernel unit is used as the minimum multiplexing unit, the OPC accumulated correction time of each area block is reduced by one fourth, actually, the internal structures such as the storage unit, the calculation unit and the like in the kernel also have unit multiplexing, and the effective accumulated correction time is reduced by more;
according to the invention, the mode of multiplexing unit region layering processing and flattening cutting of other units can effectively reduce the increase of environment regions caused by correcting the layout according to the original unit layers, and improve correction efficiency factors;
the adoption of the hierarchical unit tree to combine the corrected layouts can shorten the time of OPC verification, mask rule check and secondary correction; meanwhile, the storage space of the corrected graph can be reduced by the aid of the layered layout;
as shown in fig. 3, it is assumed that the integrated circuit layout includes 4 logic layers (a first logic layer 109, a second logic layer 110, a third logic layer 111, and a fourth logic layer 112) that need to be subjected to photolithography, and optical proximity correction processing may be performed on each layer;
selecting modified target layer first logical layer 109 (i.e., target layer L)1) Analyzing the layout level calling relationship from top to bottom, and screening the calling units to meet the requirement that the size of the units is larger than W2 to form target units; the top-down plan view and the dimensional relationship of the target units are shown in FIG. 4, the top unit is A, and the target units with the unit satisfying the size larger than W2 comprise A, B, C, D and E; for simplicity, other sets of units are replaced with F, which may contain multiple instances of units; wherein, the leaf nodes in the graph are not drawn (the leaf nodes are unit nodes which only contain basic figure elements and do not call other subunits in the layout);
the above W2 may refer to an area or a minimum side length or a length and a width;
drawing a unit instantiated tree diagram of a target unit as shown in FIG. 5 according to the calling relationship and instantiation analysis of the layout units, wherein the top unit of the layout calls 3 subunits B, C and D for A; a is generally called parent unit of B, C and D, and B, C and D are called child unit of A; wherein unit B is instantiated 2 times in parent unit A, and unit B calls child units D and E;
analyzing the unit tree diagram, wherein units with the instantiation number larger than 2 comprise B, D and E, and a set V1 is formed as { B, D and E };
it is understood that if a unit is multiplexed for many times in the layout instantiation, and only one parent unit is provided, the parent unit is necessarily multiplexed for many times, so that for such units, only the parent unit needs to be processed (the parent unit is processed to complete the processing of the child unit, and the child unit can be regarded as belonging to the parent unit); in this example, only one multiplexing unit E of the parent unit is removed, and the constituent unit V2 is { B, D };
analyzing the units in the multiplexing unit set V2 one by one, analyzing the influence area of other units and the unit on the unit graph in the layout example according to the optical action distance between the graphs, and determining the boundary (namely B) of the unit in the layout hierarchical reusable area to be optically corrected1) With the border as an auxiliary layer (i.e., L)2) Inserting the layout; specifically, as can be seen in fig. 4, the units D and C have overlapping regions, the overlapping regions are removed, and the remaining regions are removed from the environmental impact regions according to the optical action distance, so as to extract the effective multiplexing region in D, which is the case for the unit B; as shown in fig. 6, unit D target reserveThe domain boundary 201 is the target reserved area boundary of the cell D, the cell B target reserved area boundary 202 is the target reserved area of the cell B, and the cell D target reserved area boundary 201 and the cell B target reserved area boundary 202 are respectively inserted into the cell D and the cell B as auxiliary graphics; since the cell D is multiplexed 3 times in the layout, the target region auxiliary graph shown by the cell D target reserve region boundary 201 in the top-level plan view of fig. 6 has three instances, and similarly, the target region auxiliary graph shown by the cell B target reserve region boundary 202 has two instances;
partitioning blocks for top-level units and inner units in V2 according to auxiliary graphs, as shown in FIG. 7, dividing sub-units in unit D into multiple blocks according to the area covered by the auxiliary graphs in the units; as shown in fig. 8, the subunit D in B has an auxiliary layer, and a new region is formed by subtracting the auxiliary layer pattern in D from the auxiliary layer pattern in B, and the region is subjected to block segmentation; as shown in fig. 9, the area covered by the auxiliary layer graphics of all the sub-units is subtracted from the boundary of the top-level unit to obtain the area to be corrected of the top-level unit, and the area to be corrected is divided into blocks. Considering the environmental area in the actual graph cutting area of the block, comparing with the graph shown in FIG. 1, the cutting corrected block needs to be expanded outward by a certain distance to form a real cutting block; extracting the graph corresponding to the cutting block to a cluster, and performing distributed parallel optical correction calculation;
storing the correction results of the blocks into a top unit and a multiplexing unit respectively; after the correction, the combined graph unit tree structure keeps layering, and the unit tree nodes only keep the units formed by the top-level units and the multiplexing area to form a completely layered layout; the method comprises the steps of (the hierarchy of the layout can be divided into two types from the unit calling relationship, namely complete hierarchy and incomplete hierarchy, the complete hierarchy means that no graph is overlapped between any two units in the same layer of the layout, no graph is intersected with the frame of a sub-word unit in a father unit, and the incomplete hierarchy does not meet the conditions), and the efficiency of follow-up OPC verification, secondary correction and mask preparation is improved.
Rearranging the layout cell tree, reserving the top-level cell node and the multiplexing cell node in V2, and deleting other nodes; in this embodiment, since the cell calling is simple, the cell level does not change, and only the redundant node needs to be deleted, fig. 10 is a new complete layout cell tree; in some specific examples, the father node of the multiplexing unit does not belong to the multiplexing unit, and at this time, information such as the calling relationship of the reserved multiplexing unit node, the conversion unit hierarchical coordinates, and the like needs to be updated (for example, if there is only one unit B in this embodiment, as shown in fig. 12, the father node B unit of the multiplexing unit D is not a multiplexing unit, there is a new layout unit tree as shown in fig. 13, the blocks are respectively partitioned according to the auxiliary graph in the top-level unit and V2 according to the above scheme, as shown in fig. 14, the sub-unit in the unit D has no auxiliary layer, so the area covered by the auxiliary graph in the unit D is divided into a plurality of blocks according to the auxiliary graph in the unit, as shown in fig. 15, the sub-unit in the unit E has no auxiliary layer, so the area covered by the auxiliary graph in the unit D is divided into a plurality of blocks according to the auxiliary graph, obtaining a region to be corrected of a top unit, and dividing the region to be corrected into blocks; considering the environmental area in the actual graph cutting area of the block, comparing with the graph shown in FIG. 1, the cutting corrected block needs to be expanded outward by a certain distance to form a real cutting block; extracting the graphs corresponding to the cutting blocks to a cluster, performing distributed parallel optical correction calculation, and correspondingly storing the correction results of the blocks into a top unit and a multiplexing unit respectively; rearranging the layout cell tree, reserving the top-level cell node and the multiplexing cell node in V2, and deleting other nodes, wherein FIG. 17 is a new complete layout cell tree).
Specifically, the boundary of the modified area dividing block is not limited to any polygon.
Specifically, the average partition block size W1Greater than the inter-pattern optical working distance.
Specifically, the parallel correction in step 4 and step 5 is performed in parallel on a plurality of processors or a plurality of processor cores; compared with the unit hierarchical correction mentioned in the prior art, such as the unit correction from bottom to top step by step, the correction efficiency of the whole distributed parallel system is not considered, and the following reasons are that firstly, the number of incomplete layers is large in the layout calling unit relationship, the number of layout units is huge, the number of unit instantiations can reach hundreds of millions or even billions, and the unit graph overlap analysis time is too long; secondly, step-by-step unit correction is carried out, the correction result is multiplexed to the maximum extent on the surface, the problem that the environmental graph accounts for too much in the step 1 is caused by actually too small units, and the problem that the environmental area proportion of a part of divided blocks is increased certainly because a plurality of units are divided in a large unit, so that the efficiency factor is reduced.
Specifically, in step 7, the deletion of the unit tree node needs to update the call relationship of the reserved unit node and the corresponding information of the conversion unit.
Specifically, the block size W2At least the block size W14 times of the original layout, analyzing from the perspective of photoetching calculation efficiency factors, only extracting units which meet a certain size and are repeatedly called, multiplexing the result of optical correction, multiplexing one unit for multiple times in the instantiation of the layout, only one father unit, and only extracting the effective multiplexing area of the father unit; in addition, the optical correction generally distributes block data to different nodes for calculation through a cluster scheduler, and excessive and small blocks cause waste of calculation power, which is not beneficial to improving the overall correction efficiency.
The utility model provides a system for accelerating territory processing, includes a management node, a plurality of calculation node and a plurality of storage node, wherein, the management node is used for accomplishing the optical proximity correction of each block including the reading module that is used for loading original territory, the analysis module that is used for hierarchical analysis and cuts apart the territory, the processing module that is used for merging the correction result at least, the calculation node, the storage node is used for storing territory mask data and instruction program.
Specifically, the management node, the plurality of computing nodes and the storage node are interconnected through a network controller.
In the embodiment, the layout is subjected to hierarchical arrangement, block division, parallel correction, correction result combination and the like in the embodiment, which need to be finished in a computer processing system, the blocks are mutually independent, and the blocks can be independently finished in a plurality of computing nodes; fig. 11 is a diagram for optically modifying a hardware cluster, where a management node 301 is used to load an original layout, hierarchically analyze and divide the layout, merge modification results, and so on, calculate a node 302 to complete optical proximity modification of each block, and a storage node 303 is used to store layout mask data and an instruction program, and the nodes are interconnected through a network controller.
Working principle of determining a target layer L for performing an optical correction1And average partition block size W1According to target layer L1And the original unit tree T of the layout1Extracting the specific size W in the layout2And the number of instantiations is more than or equal to 21；
Traversal set V1If the cell has a unique parent cell, the cell is selected from V1Deleted in (1), the remaining unit set is marked as V2；
Analyzing the multiplex unit set V one by one2The middle unit analyzes the graph influence area of other units and the unit itself on the unit in the layout example according to the optical action distance, and determines the boundary B of the unit in the layout hierarchical reusable area to be optically corrected1. Will border B1As an auxiliary graphics layer L2An insertion unit;
according to the top unit and V2Dividing the blocks by the unit;
the top level cell partition is divided by subtracting the auxiliary graphics layer L from the top level cell boundary2Obtaining a region to be corrected of the top unit in the covered region, and dividing the region to be corrected into blocks for distributed parallel correction;
to V2The method for dividing each unit block is that the unit auxiliary graphics layer L2The covered area minus the area covered by the auxiliary graphics of all the sub-units forms the unit to be processedCorrecting the area, namely dividing the area to be corrected into blocks and performing distributed parallel correction;
storing the correction result of each block to each unit node to which the original cutting block belongs, and combining the correction results of each block;
and extracting a layout unit tree structure, reserving a set V1 and a top-level unit, and deleting other unit nodes to obtain a new unit hierarchical structure.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (8)
1. A method for accelerating layout processing is characterized in that: the method comprises the following steps:
layout division and correction:
step 1 determining a target layer L for performing optical correction1And average partition block size W1According to the target layer L1And the original unit tree T of the layout1Extracting the dimension W of the block larger than the block size in the layout2And the number of instantiations is more than or equal to 21；
Step 2: traversal set V1If the cell has a unique parent cell, the cell is selected from V1Deleted in (1), the remaining unit set is marked as V2；
And step 3: analyzing the multiplexing unit set V one by one according to the optical action distance2Obtaining the influence area of the unit, other units and the unit on the unit graph to obtain the boundary B of the unit in the domain layering reusable area to be optically corrected1To optically correct the zone boundariesB1As an auxiliary graphic L2Inserting into the top unit;
step 4, dividing the top unit block, subtracting the auxiliary graph L by the top unit2Obtaining a to-be-corrected area of the top unit in the covered area, and performing distributed parallel correction on the to-be-corrected area of the top unit;
and 5: to V2The unit auxiliary graphics L2Subtracting the area covered by the auxiliary graphs of all the subunits from the covered area to obtain the area to be corrected of the unit, and dividing the area to be corrected of the unit into blocks for distributed parallel correction;
layout merging step:
step 6: storing the correction result of each block to each unit node to which the original cutting block belongs, and combining the correction results of the blocks;
and 7: extracting a layout unit tree structure and reserving the unit set V1And deleting the residual unit nodes to obtain a new unit hierarchical structure.
2. A method for accelerating layout processing according to claim 1, wherein: the boundary of the modified area dividing block is not limited to any polygon.
3. A method for accelerating layout processing according to claim 1, wherein: the average partition block size W1Greater than the inter-pattern optical working distance.
4. A method for accelerating layout processing according to claim 1, wherein: the parallel correction in steps 4 and 5 is a parallel correction on a plurality of processors or a plurality of processor cores.
5. A method for accelerating layout processing according to claim 1, wherein: in step 7, the deletion of the unit tree node needs to update the call relationship of the reserved unit node and the corresponding information of the conversion unit.
6. A method for accelerating layout processing according to claim 1, wherein: the block size W2At least the block size W14 times of the total weight of the product.
7. A system for accelerating layout processing, comprising: including a management node, a plurality of calculation node and a plurality of storage node, wherein, the management node is used for accomplishing the optical proximity correction of each block including the reading module that is used for loading original territory, the analysis module that is used for hierarchical analysis and cuts apart the territory, the processing module that is used for merging the correction result at least, the calculation node, the storage node is used for storing territory mask data and instruction program.
8. A system for accelerating layout processing according to claim 7, wherein: the management node, the plurality of computing nodes and the storage node are interconnected through a network controller.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112462571A (en) * | 2020-12-04 | 2021-03-09 | 深圳清华大学研究院 | Periodic graphic array extraction method, computer device and storage medium |
| CN112987489A (en) * | 2021-02-22 | 2021-06-18 | 上海华力集成电路制造有限公司 | OPC correction method for layout with device auxiliary graph |
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| CN116757145A (en) * | 2023-08-16 | 2023-09-15 | 合肥奎芯集成电路设计有限公司 | Integrated circuit design layout processing method and device, electronic equipment and storage medium |
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