CN111458974B - Method and system for accelerating layout processing - Google Patents
Method and system for accelerating layout processing Download PDFInfo
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- CN111458974B CN111458974B CN202010444483.XA CN202010444483A CN111458974B CN 111458974 B CN111458974 B CN 111458974B CN 202010444483 A CN202010444483 A CN 202010444483A CN 111458974 B CN111458974 B CN 111458974B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a method and a system for accelerating layout processing, wherein the method comprises a layout dividing and correcting step and a layout merging step, the system comprises a management node, a plurality of calculation nodes and a plurality of storage nodes, hierarchical arrangement, block division, parallel correction, correction result merging and the like are required to be completed in a computer processing system, and blocks are mutually independent, so that the blocks can be independently completed in a plurality of calculation nodes; the invention utilizes the mode of multiplexing unit layering and flattening and dividing the layout of the other units, is used for accelerating the process of OPC full-chip parallel correction, improving the efficiency of parallel correction, multiplexing correction results, improving the manufacturing consistency of internal units, ensuring the performance of chips, combining the hierarchical unit trees, correcting and cutting blocks, shortening the time of OPC verification, mask rule inspection and secondary correction, and reducing the storage space of corrected data.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method and a system for accelerating layout processing.
Background
In the production of semiconductor devices, mask patterns are printed or realized on a semiconductor substrate by photolithography. With the reduction of the minimum feature size and the pitch of the integrated circuit, patterns close to each other in the layout have great distortion between the actually printed patterns and the expected patterns under the factors of dry diffraction of light, photoresist development etching and the like. To eliminate these distortions, one approach is to make Optical Proximity Correction (OPC) of the pattern on the mask when the line width on the wafer is less than the exposure wavelength. The optical proximity correction technology compensates transfer distortion of patterns in the photoetching process by correcting the design layout in advance.
Optical correction is a very time-consuming and resource-consuming task due to the large number of layout patterns. As the feature size of integrated circuits has further decreased, the gap between lithographic wavelength and line width has become larger, especially for processes below 22nm, and full-chip optical correction has become an indispensable step in the fabrication of chip masks.
Because the optical correction adopts a complex and accurate calculation model, the number of mask patterns of each layer can reach billions, each pattern needs to be corrected, and a single machine is difficult to finish. The full-chip optical correction needs to divide a physical layout into a plurality of small blocks according to positions, and each small block is calculated in a distributed parallel mode. Each patch modifies the pattern in the region according to the model. Since each block is independent of the other, a linearly increasing computational complexity can be maintained with distributed computing. After layout segmentation and correction, mask manufacturing rules possibly caused by splicing are violated, and meanwhile, the problems of overlarge polygon correction errors and the like are affected by an environment area, so that OPC is a process of repeated iteration and repeated correction. There is usually a post-OPC verification step to detect the verification correction result, and when the OPC verification detects that the corrected pattern has a problem, the area needs to be corrected again, so that an iterative manner of correction-verification-re-correction is adopted for each area.
Each cut-out area comprises two areas, affected by the optical scattering radius between the patterns: a target area and a surrounding area. As shown in fig. 1 of the specification, the target area 102 is a region reserved after correction, and the calculation result of the environment area 101 is discarded. The ambient region 101 is a modified pattern that assists in calculating the target region, which is sized depending on the lithographic scattering radius, typically on the order of microns for conventional 193nm lithographic wavelengths. In parallel division, the greater the number of divided blocks, the greater the specific gravity of the total environmental area, and the correction efficiency decreases synchronously. If a lithography calculation efficiency factor f= (total area of cumulative calculation and/or target area of cumulative calculation) is defined, the greater the F factor value, the higher the calculation efficiency is. For the mode of flattening and dividing the layout, assuming that the area calculated by each block photoetching is (n+m) and n+n, the area of the target area is N and the total dividing block number is N, then
Typically N is the area of the largest circumscribed frame of all the graphics of the layer, and the value of m represents the optical working distance. Depending on the circuit feature size and the lithographic wavelength.
Because the integrated circuit layout has the unit multiplexing, if the unit multiplexing is effectively utilized, the operation time can be reduced or the number of calculation nodes can be reduced. However, the original hierarchical unit structure is affected by other unit graphic elements and cannot be directly reused. The traditional method for parallel or serial correction of the flattened layout segmentation layout not only repeatedly corrects redundant parts, but also affects the consistency of correction.
In the prior art, some layout layering OPC correction techniques, such as extracting the 'no external influence area' in a unit from bottom to top according to the existing hierarchy of the layout, correct other areas in the unit together with a father unit, and do not consider the correction efficiency of the whole distributed parallel system. The reason is that in the step-by-step unit correction, although the N value is reduced by multiplexing the correction result, the specific gravity of the environment area of a part of the divided block is necessarily increased because of the divided area in the unit, and the efficiency factor is reduced.
If the corrected block combination is a flattened layout, layering of the layout cannot be reused in the follow-up OPC verification and secondary correction. The mask information amount stored in a flattened mode after correction is increased suddenly, and a single layer can reach TB level.
Disclosure of Invention
The invention aims to provide a method and a system for accelerating layout processing, which are used for solving the problems in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions: a method of accelerating layout processing, comprising:
layout dividing and correcting:
step 1: determining a target layer L for performing optical correction 1 And average partition block size W 1 According to the target layer L 1 And original unit tree T of layout 1 Extracting the size W larger than the block in the layout 2 And the number of instantiations is greater than or equal to 2, multiplexing unit set V 1 ；
Step 2: traversing set V 1 If the unit has a unique parent unit, then the unit is taken from V 1 The remaining set of units is marked V 2 ；
Step 3: analyzing the multiplexing unit set V one by one according to the optical action distance 2 The middle unit, other units and the influence area of the unit on the unit graph to obtain the layout layer of the unitSub-multiplexing the boundary B of the region to be optically modified 1 Boundary B of the area to be optically corrected 1 As an auxiliary pattern L 2 Inserting into the topping unit;
step 4: dividing the top unit blocks, and subtracting the auxiliary graph L from the top unit 2 The method comprises the steps of covering an area to be corrected of a top layer unit, and carrying out distributed parallel correction on the area to be corrected of the top layer unit;
step 5: for V 2 Each unit block of the unit auxiliary pattern L 2 Subtracting the covered areas of all the auxiliary patterns of the subunits from the covered areas to obtain the areas to be corrected of the units, and carrying out distributed parallel correction on the divided areas of the areas to be corrected of the units;
layout merging:
step 6: storing each block correction result to each unit node of the original cutting block, and combining the block correction results;
step 7: extracting a layout unit tree structure, and reserving the unit set V 1 And the top-level unit and the remaining unit nodes are deleted to obtain a new unit hierarchical structure.
Preferably, the boundary of the correction area dividing block is not limited to any polygon.
Preferably, the average partition block size W 1 Is larger than the optical action distance between patterns.
Preferably, the parallel correction in step 4 and step 5 is a parallel correction on multiple processors or multiple processor cores.
Preferably, in step 7, the unit tree node is deleted, and the calling relationship of the unit node and the corresponding information of the conversion unit are required to be updated.
Preferably, the block size W 2 At least the block size W 1 4 times of (2).
The system for accelerating layout processing comprises a management node, a plurality of calculation nodes and a plurality of storage nodes, wherein the management node at least comprises a reading module for loading an original layout, an analysis module for hierarchical analysis and layout segmentation, and a processing module for merging correction results, the calculation nodes are used for completing optical proximity correction of each block, and the storage nodes are used for storing layout mask data and instruction programs.
Preferably, the management nodes, the plurality of computing nodes and the storage nodes are interconnected through a network controller.
Compared with the prior art, the invention has the beneficial effects that:
the invention utilizes the mode of multiplexing unit layering and flattening and dividing the layout of the other units, is used for accelerating the process of OPC full-chip parallel correction, improving the efficiency of parallel correction, multiplexing correction results, improving the manufacturing consistency of internal units, ensuring the performance of chips, combining the hierarchical unit trees, correcting and cutting blocks, shortening the time of OPC verification, mask rule inspection and secondary correction, and reducing the storage space of corrected data.
Drawings
FIG. 1 is a block correction target area and an ambient area;
FIG. 2 is an exemplary diagram of a multi-core processor in an embodiment of the invention;
FIG. 3 is a layout layer in an embodiment of the present invention;
FIG. 4 is a schematic top view of a unit cell in an embodiment of the invention;
FIG. 5 is a diagram of a unitized tree according to one embodiment of the present invention;
FIG. 6 is a schematic diagram of a multiplex area boundary assist feature in an embodiment of the invention;
FIG. 7 is a schematic diagram of a D-unit partition block according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a region division block formed by subtracting D units from B units in an embodiment of the present invention;
FIG. 9 is a schematic diagram of a region division block formed by subtracting B cells from A cells and subtracting D cells according to an embodiment of the present invention;
FIG. 10 is a diagram of a modified and integrated unit tree in an embodiment of the invention;
FIG. 11 is a system block diagram of an accelerated layout processing system in accordance with an embodiment of the present invention;
FIG. 12 is a schematic top view of a unit cell in another embodiment of the invention;
FIG. 13 is a diagram of a unitized tree according to another embodiment of the present invention;
FIG. 14 is a schematic diagram of a D-unit partition block according to another embodiment of the present invention;
FIG. 15 is a schematic diagram of an E-cell partition block according to another embodiment of the present invention;
FIG. 16 is a schematic diagram of a segmented block formed by subtracting D and E units from an A unit according to another embodiment of the present invention;
FIG. 17 is a diagram of a modified and integrated unit tree according to another embodiment of the present invention.
Reference numerals in the drawings: 101. an environmental area; 102. a target area; 103. a first storage unit; 104. a second storage unit; 105. a first processor core; 106. a second processor core; 107. a third processor core; 108. a fourth processor core, 109, a first logic layer; 110. a second logic layer; 111. a third logic layer; 112. a fourth logic layer; 201. unit D target reserved area boundary; 202. unit B target reserved area boundary; 301. a management node; 302. calculating nodes; 303. and storing the nodes.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples: a method of accelerating layout processing, comprising:
layout dividing and correcting:
step 1: determining a target layer L for performing optical correction 1 And average partition block size W 1 According to the target layer L 1 And original unit tree T of layout 1 Extracting the size W larger than the block in the layout 2 And instantiateMultiplexing unit set V with number more than or equal to 2 1 ；
Step 2: traversing set V 1 If the unit has a unique parent unit, then the unit is taken from V 1 The remaining set of units is marked V 2 ；
Step 3: analyzing the multiplexing unit set V one by one according to the optical action distance 2 The middle unit, other units and the influence area of the unit on the unit graph can obtain the boundary B of the unit to be optically corrected, which can be multiplexed in the layout hierarchy 1 Boundary B of the area to be optically corrected 1 As an auxiliary pattern L 2 Inserting into the topping unit;
step 4: dividing the top unit blocks, and subtracting the auxiliary graph L from the top unit 2 The method comprises the steps of covering an area to be corrected of a top layer unit, and carrying out distributed parallel correction on the area to be corrected of the top layer unit;
step 5: for V 2 Each unit block of the unit auxiliary pattern L 2 Subtracting the covered areas of all the auxiliary patterns of the subunits from the covered areas to obtain the areas to be corrected of the units, and carrying out distributed parallel correction on the divided areas of the areas to be corrected of the units;
layout merging:
step 6: storing each block correction result to each unit node of the original cutting block, and combining the block correction results;
step 7: extracting a layout unit tree structure, and reserving the unit set V 1 And the top-level unit and the remaining unit nodes are deleted to obtain a new unit hierarchical structure.
In this embodiment, as shown in fig. 2, taking a multi-core processor as an example, a first processor core 105, a second processor core 106, a third processor core 107, a fourth processor core 108 is a multiplexed four-processor core instance, a first storage unit 103, and a second storage unit 104 is a multiplexed storage unit instance in the first processor core 105, where the figure is used to illustrate that there may be a unit multiplexing in the integrated circuit layout under self-orientation;
the 4 cores take the core unit as the minimum multiplexing unit, the OPC accumulated correction time of each area block is reduced by one fourth of the original OPC accumulated correction time, and in practice, the internal structures such as a storage unit, a calculation unit and the like in the core are also multiplexed by units, so that the effective accumulated correction time is reduced more;
the method for carrying out layering processing on the multiplexing unit areas and carrying out flattening cutting on the other units can effectively reduce the increase of the environment areas caused by correcting the layout according to the original unit layering, and improve the correction efficiency factor;
the hierarchical unit tree is adopted to merge the corrected layout, so that the time for OPC verification, mask rule inspection and secondary correction can be shortened; meanwhile, the hierarchical layout can reduce the storage space of the corrected graph;
as illustrated in fig. 3, assuming that the integrated circuit layout includes 4 logic layers (a first logic layer 109, a second logic layer 110, a third logic layer 111, and a fourth logic layer 112) that need to be subjected to photolithography, optical proximity correction processing may be performed separately for each layer;
the modified target layer first logical layer 109 (i.e., target layer L 1 ) Analyzing the layout hierarchical calling relation from top to bottom, screening units with the calling unit meeting the requirement of units with the size larger than W2, and forming target units; the top-down top view and the dimensional relationship of the target units are shown in fig. 4, the top-level unit is A, and the target units with the unit satisfying the size larger than W2 comprise A, B, C, D and E; for brevity, other sets of units are replaced with F, which may contain multiple instances of units; leaf nodes are not drawn in the figure (the leaf nodes are unit nodes which only contain basic graphic elements and do not call other sub-units in the layout);
w2 may refer to the area or minimum side length or length and width;
according to the call relation and instantiation analysis of the layout unit, a unit instantiation tree diagram of the target unit shown in fig. 5 can be drawn, and 3 subunits B, C and D are called for A by the top-level unit of the layout; a is generally referred to as a parent unit of B, C, D, and B, C, D is referred to as a child unit of a; wherein unit B is instantiated 2 times in parent unit A, unit B calls child units D and E;
analyzing a tree diagram of units, wherein the instantiation number of the units is greater than 2, and the units are B, D and E, so that a set V1 = { B, D and E };
it will be appreciated that if a unit is multiplexed multiple times in the layout instantiation and there is only one parent unit, then the parent unit must be multiplexed multiple times, so for such units, only the parent unit needs to be processed (processing the parent unit can complete the processing of the child unit, which can be considered as being affiliated with the parent unit); in this example, multiplex unit E with only one parent unit is eliminated, and the constituent unit is combined with v2= { B, D };
analyzing units in the multiplexing unit set V2 one by one, analyzing the influence area of other units and the units on the unit graph in the layout example according to the optical action distance between graphs, and determining the boundary (namely B 1 ) The boundary is taken as an auxiliary layer (namely L 2 ) Inserting a layout; specifically, as can be seen in fig. 4, units D and C have overlapping areas, the overlapping areas are removed, and the remaining areas are removed according to the optical distance, so that the effective multiplexing area in D is extracted, which is the case for unit B; as shown in fig. 6, the unit D target reserve area boundary 201 is a target reserve area boundary of the unit D, the unit B target reserve area boundary 202 is a target reserve area of the unit B, and the unit D target reserve area boundary 201 and the unit B target reserve area boundary 202 are inserted as auxiliary graphics into the unit D and the unit B, respectively; because the cell D is multiplexed 3 times in the layout, there are three examples of the target area auxiliary pattern shown by the cell D target retention area boundary 201 in the top-level plan view of fig. 6, and similarly, there are two examples of the target area auxiliary pattern shown by the cell B target retention area boundary 202;
the blocks are divided into a top unit and an inner unit in V2 according to the auxiliary graph, as shown in FIG. 7, the sub-units in the unit D have no auxiliary graph layer, so that the unit D is divided into a plurality of blocks according to the area covered by the auxiliary graph in the unit; as shown in fig. 8, the sub-unit D has an auxiliary layer, the auxiliary layer pattern in the sub-unit B minus the auxiliary layer pattern in the sub-unit D forms a new region, and the region is segmented; as shown in fig. 9, the boundary of the top unit subtracts the area covered by the auxiliary layer patterns of all the sub-units to obtain the area to be corrected of the top unit, and the area to be corrected is divided into blocks. The actual graph cutting area of the block needs to consider the environment area, and the corrected block is cut and enlarged outwards by a certain distance to form a real cutting block, which is similar to that shown in FIG. 1; extracting the graph corresponding to the cutting block, sending the graph to a cluster, and performing distributed parallel optical correction calculation;
storing the correction results of each block into a top layer unit and a multiplexing unit correspondingly; after correction, merging the graphic unit tree structure to keep layering, and only reserving units formed by top-layer units and multiplexing areas by unit tree nodes to form a full-layering layout; (the hierarchy of the layout can be divided into two types from the unit call relationship, namely, a complete hierarchy and an incomplete hierarchy, wherein the complete hierarchy refers to the fact that no graph overlap exists between any two units on the same layer of the layout, no graph of a parent unit intersects with the frame of a sub-word unit, and the incomplete hierarchy does not meet the conditions), so that the correction layout of the complete hierarchy improves the efficiency of the follow-up OPC verification, secondary correction and mask preparation.
Rearranging the layout unit tree, reserving top-level unit nodes and multiplexing unit nodes in V2, and deleting other nodes; in the embodiment, as the unit call is relatively simple, the unit level is not changed, and only redundant nodes need to be deleted, and fig. 10 is a new complete layout unit tree; in some special cases, the father node of the multiplexing unit does not belong to the multiplexing unit, at this time, the reserved calling relation of the multiplexing unit node is required to be updated, the information such as the hierarchical coordinates of the converting unit is required to be converted (for example, if only one of the units B is shown in fig. 12, the father node B of the multiplexing unit D is not a multiplexing unit, a new layout unit tree is shown in fig. 13, according to the scheme, the blocks in the top layer unit and the inner units in the V2 are respectively segmented according to the auxiliary graph, as shown in fig. 14, the sub-units in the unit D are not provided with auxiliary graph layers, so that the area covered by the auxiliary graph in the unit D is divided into a plurality of blocks, as shown in fig. 15, the sub-units in the unit E are not provided with auxiliary graph layers, so that the area covered by the auxiliary graph in the unit D is divided into a plurality of blocks, as shown in fig. 16, the area to be corrected is obtained by subtracting the auxiliary graph covered by the auxiliary graph of all sub-units of the unit, the top layer unit boundary of the top layer is divided into blocks, the area to be corrected to be the area to be corrected, the area to be divided into the area to be corrected is required to be considered in fig. 13, the area to be actually graph area to be cut, the area to be cut into the area to be actually is enlarged by considering the environment area, as shown in fig. 1, the area to be actually cut, the area is required to be a certain distance is to be cut, as shown in the area, the area is correspondingly cut, and the area to be cut and the area to be correspondingly cut and the area to be cut is correspondingly cut and the area is formed in the graph is divided into the top layer and the corresponding graph is saved to be a corresponding graph node and the corresponding graph is saved and the corresponding graph is respectively has the corresponding graph is saved and the corresponding graph node is in the node is saved.
Specifically, the boundary of the correction area dividing block is not limited to any polygon.
Specifically, the average partition block size W 1 Is larger than the optical action distance between patterns.
Specifically, the parallel correction in step 4 and step 5 is a parallel correction on multiple processors or multiple processor cores; compared with the unit layering correction mentioned in the prior art, for example, the unit correction from bottom to top is not considered, and the correction efficiency of the whole distributed parallel system is not considered, first, because in the relationship of layout calling units, the number of incomplete layers is large, the number of layout units is huge, the number of unit instantiations can reach hundreds of millions or even billions, and the unit graph overlapping analysis time is too long; secondly, the unit is corrected step by step, the surface is the largest multiplexing correction result, the actual too small unit causes the problem that the ratio of the environment graph is too large in the step 1, the large unit is divided into a plurality of blocks in the unit, the specific gravity of the environment area of a part of the divided blocks is necessarily increased, and the efficiency factor is reduced.
Specifically, in step 7, the unit tree node is deleted, and the calling relationship of the unit node and the corresponding information of the conversion unit are required to be updated.
Specifically, the block size W 2 At least a blockDimension W 1 4 times of the number of the units, only extracting the units which meet a certain size and are repeatedly called from the angle analysis of the photoetching calculation efficiency factor, multiplexing the optical correction result, wherein one unit is multiplexed for a plurality of times in the layout instantiation, only one father unit is provided, and only the effective multiplexing area of the father unit is extracted; since the surrounding environment pattern of the target area needs to be reserved for the block correction, if the duty ratio of the environment pattern is too large, the redundant calculation area is increased, in addition, the block data is generally distributed to different nodes for calculation through the cluster scheduler by the optical correction, and too many small blocks can cause the waste of calculation force, so that the overall correction efficiency is not facilitated to be improved.
The system for accelerating layout processing comprises a management node, a plurality of calculation nodes and a plurality of storage nodes, wherein the management node at least comprises a reading module for loading an original layout, an analysis module for hierarchical analysis and layout segmentation, and a processing module for merging correction results, the calculation nodes are used for completing optical proximity correction of each block, and the storage nodes are used for storing layout mask data and instruction programs.
Specifically, the management nodes, the plurality of computing nodes and the storage nodes are interconnected through a network controller.
In the embodiment, the layout is hierarchically arranged, the blocks are divided, the parallel correction is performed, the correction results are combined and the like are required to be completed in a computer processing system, the blocks are mutually independent, and the blocks can be independently completed in a plurality of computing nodes; fig. 11 shows an optical correction hardware cluster, a management node 301 is used for loading an original layout, performing hierarchical analysis and layout division, combining correction results, and the like, a calculation node 302 is used for completing optical proximity correction of each block, a storage node 303 is used for storing layout mask data and instruction programs, and each node is interconnected through a network controller.
Working principle: determining a target layer L for performing optical correction 1 And average partition block size W 1 According to the target layer L 1 And original unit tree T of layout 1 Extracting the W meeting the specific size in the layout 2 And instantiate a quantityMultiplexing unit set V of 2 or more 1 ；
Traversing set V 1 If the unit has a unique parent unit, then the unit is taken from V 1 The remaining set of units is marked V 2 ；
Analyzing the multiplex unit set V one by one 2 The middle unit analyzes the influence area of other units and the unit itself on the graph of the unit in the layout example according to the optical action distance, and determines the boundary B of the unit in the layout layering reusable area to be optically corrected 1 . Boundary B 1 As an auxiliary graphics layer L 2 An insertion unit;
according to the top layer unit and V 2 Dividing the middle unit into blocks;
the method for dividing the top unit blocks is to subtract the auxiliary graphics layer L from the top unit boundary 2 The covered area is used for obtaining an area to be corrected of the top unit, and the area to be corrected is divided into blocks for distributed parallel correction;
for V 2 The method of dividing each unit block in the picture layer is that the unit auxiliary pattern layer L 2 Subtracting the areas covered by the auxiliary graphics of all the subunits from the covered areas to form the areas to be corrected of the units, and carrying out distributed parallel correction on the dividing blocks of the areas to be corrected;
storing the correction results of each block to each unit node of the original cutting block, and combining the correction results of each block;
extracting a layout unit tree structure, reserving a set V1 and a top unit, deleting other unit nodes, and obtaining a new unit hierarchical structure.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (6)
1. A method for accelerating layout processing is characterized in that: comprising the following steps:
layout dividing and correcting:
step 1: determining a target layer L for performing optical correction 1 And average partition block size W 1 According to the target layer L 1 And original unit tree T of layout 1 Extracting the size W larger than the block in the layout 2 And the number of instantiations is greater than or equal to 2, multiplexing unit set V 1 ；
Step 2: traversing set V 1 If the unit has a unique parent unit, then the unit is taken from V 1 The remaining set of units is marked V 2 ；
Step 3: analyzing the multiplexing unit set V one by one according to the optical action distance 2 The middle unit, other units and the influence area of the unit on the unit graph can obtain the boundary B of the unit to be optically corrected, which can be multiplexed in the layout hierarchy 1 Boundary B of the area to be optically corrected 1 As an auxiliary pattern L 2 Inserting into the topping unit;
step 4: dividing the top unit blocks, and subtracting the auxiliary graph L from the top unit 2 The method comprises the steps of covering an area to be corrected of a top layer unit, and carrying out distributed parallel correction on the area to be corrected of the top layer unit;
step 5: for V 2 Each unit block of the unit auxiliary pattern L 2 Subtracting the covered areas of all the auxiliary patterns of the subunits from the covered areas to obtain the areas to be corrected of the units, and carrying out distributed parallel correction on the divided areas of the areas to be corrected of the units;
layout merging:
step 6: storing each block correction result to each unit node of the original cutting block, and combining the block correction results;
step 7: extracting the tree structure of the layout unit and preservingLeaving the set of units V 1 And the top-level unit, the remaining unit node deletes, obtain the new unit hierarchical structure;
the average partition block size W 1 Is larger than the optical action distance between the patterns;
the block size W 2 At least the block size W 1 4 times of (2).
2. A method of accelerating layout processing according to claim 1, wherein: the boundary of the correction area dividing block is not limited to any polygon.
3. A method of accelerating layout processing according to claim 1, wherein: the parallel correction in step 4 and step 5 is a parallel correction on multiple processors or multiple processor cores.
4. A method of accelerating layout processing according to claim 1, wherein: in step 7, the unit tree node is deleted, and the calling relation of the unit node and the corresponding information of the conversion unit are required to be updated.
5. A system for accelerating layout processing for implementing a method for accelerating layout processing of claim 1, wherein: the system comprises a management node, a plurality of calculation nodes and a plurality of storage nodes, wherein the management node at least comprises a reading module for loading an original layout, an analysis module for hierarchical analysis and layout segmentation, and a processing module for merging correction results, the calculation nodes are used for completing optical proximity correction of each block, and the storage nodes are used for storing layout mask data and instruction programs.
6. A system for accelerating layout processing as in claim 5, wherein: the management nodes, the plurality of computing nodes and the storage nodes are interconnected through a network controller.
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| CN112462571B (en) * | 2020-12-04 | 2023-05-23 | 深圳清华大学研究院 | Periodic pattern array extraction method, computer device and storage medium |
| CN112864023B (en) * | 2021-01-07 | 2022-04-29 | 长鑫存储技术有限公司 | Semiconductor mark manufacturing method and semiconductor mark |
| CN112987489B (en) * | 2021-02-22 | 2024-01-09 | 上海华力集成电路制造有限公司 | OPC correction method for layout with auxiliary graph of device |
| CN113779928B (en) * | 2021-09-03 | 2022-07-08 | 珠海市睿晶聚源科技有限公司 | Calculation method and system for rapid simulation photoetching process |
| CN113763398B (en) * | 2021-09-03 | 2022-08-16 | 珠海市睿晶聚源科技有限公司 | Layout decomposition processing method and electronic equipment |
| CN113761828B (en) * | 2021-09-03 | 2022-10-28 | 珠海市睿晶聚源科技有限公司 | Mask data, and mask data processing method and system |
| CN113779921B (en) * | 2021-09-09 | 2023-01-03 | 全芯智造技术有限公司 | Method, apparatus and computer-readable storage medium for processing integrated circuit layout |
| CN116107154B (en) * | 2023-04-13 | 2023-09-05 | 长鑫存储技术有限公司 | Mask data generation method, device, equipment and medium |
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