CN104937668B - 用在集成电路中的可扫描存储元件及相关联的操作方法 - Google Patents

用在集成电路中的可扫描存储元件及相关联的操作方法 Download PDF

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Publication number
CN104937668B
CN104937668B CN201480004861.5A CN201480004861A CN104937668B CN 104937668 B CN104937668 B CN 104937668B CN 201480004861 A CN201480004861 A CN 201480004861A CN 104937668 B CN104937668 B CN 104937668B
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China
Prior art keywords
scanning
node
input
coupled
switch
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CN201480004861.5A
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English (en)
Chinese (zh)
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CN104937668A (zh
Inventor
N·N·帕里克
P·蒂瓦里
A·杜贝
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Texas Instruments Inc
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Texas Instruments Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
CN201480004861.5A 2013-01-21 2014-01-21 用在集成电路中的可扫描存储元件及相关联的操作方法 Active CN104937668B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/746,153 2013-01-21
US13/746,153 US9097764B2 (en) 2013-01-21 2013-01-21 Scan chain in an integrated circuit
PCT/US2014/012314 WO2014113787A1 (en) 2013-01-21 2014-01-21 Scan chain in an integrated circuit

Publications (2)

Publication Number Publication Date
CN104937668A CN104937668A (zh) 2015-09-23
CN104937668B true CN104937668B (zh) 2018-12-07

Family

ID=51208739

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480004861.5A Active CN104937668B (zh) 2013-01-21 2014-01-21 用在集成电路中的可扫描存储元件及相关联的操作方法

Country Status (4)

Country Link
US (1) US9097764B2 (enExample)
JP (1) JP6577366B2 (enExample)
CN (1) CN104937668B (enExample)
WO (1) WO2014113787A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102280526B1 (ko) 2014-12-08 2021-07-21 삼성전자주식회사 저전력 작은-면적 고속 마스터-슬레이브 플립-플롭 회로와, 이를 포함하는 장치들
US10282347B2 (en) * 2015-04-08 2019-05-07 Louisana State University Research & Technology Foundation Architecture for configuration of a reconfigurable integrated circuit
US11011238B2 (en) * 2018-06-28 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Floating data line circuits and methods
US10890623B1 (en) 2019-09-04 2021-01-12 International Business Machines Corporation Power saving scannable latch output driver
US11750178B2 (en) * 2021-11-02 2023-09-05 Silicon Laboratories Inc. Flip-flop with input and output select and output masking that enables low power scan for retention

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6070259A (en) * 1998-01-15 2000-05-30 Lsi Logic Corporation Dynamic logic element having non-invasive scan chain insertion
CN1452316A (zh) * 2002-04-18 2003-10-29 松下电器产业株式会社 扫描路径电路和包括该扫描路径电路的半导体集成电路
CN101877248A (zh) * 2009-05-01 2010-11-03 索尼公司 半导体集成电路、信息处理装置和输出数据扩散方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7073111B2 (en) * 2002-06-10 2006-07-04 Texas Instruments Incorporated High speed interconnect circuit test method and apparatus
US6853212B2 (en) 2002-12-20 2005-02-08 Texas Instruments Incorporated Gated scan output flip-flop
US6963212B2 (en) * 2004-03-23 2005-11-08 Agilent Technologies, Inc. Self-testing input/output pad
US7262648B2 (en) 2004-08-03 2007-08-28 Marvell International Ltd. Two-latch clocked-LSSD flip-flop
US7793180B1 (en) * 2006-09-19 2010-09-07 Marvell International Ltd. Scan architecture for full custom blocks
JP2007143193A (ja) * 2007-02-19 2007-06-07 Matsushita Electric Ind Co Ltd フリップフロップ回路
US7622975B2 (en) * 2007-07-10 2009-11-24 Qualcomm Incorporated Circuit having a local power block for leakage reduction
JP5569176B2 (ja) * 2010-06-22 2014-08-13 富士通セミコンダクター株式会社 半導体集積回路
US8493118B2 (en) 2010-09-28 2013-07-23 Apple Inc. Low power scannable latch
US8493119B2 (en) * 2010-12-13 2013-07-23 Apple Inc. Scannable flip-flop with hold time improvements
US8904254B2 (en) * 2012-11-09 2014-12-02 Oracle International Corporation Combo dynamic flop with scan

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6070259A (en) * 1998-01-15 2000-05-30 Lsi Logic Corporation Dynamic logic element having non-invasive scan chain insertion
CN1452316A (zh) * 2002-04-18 2003-10-29 松下电器产业株式会社 扫描路径电路和包括该扫描路径电路的半导体集成电路
CN101877248A (zh) * 2009-05-01 2010-11-03 索尼公司 半导体集成电路、信息处理装置和输出数据扩散方法

Also Published As

Publication number Publication date
JP2016510550A (ja) 2016-04-07
WO2014113787A1 (en) 2014-07-24
JP6577366B2 (ja) 2019-09-18
US20140208176A1 (en) 2014-07-24
CN104937668A (zh) 2015-09-23
US9097764B2 (en) 2015-08-04

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